Lines Matching +full:reg +full:- +full:5 +full:ah
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
28 #include "hw-ops.h"
34 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
40 static void ath9k_hw_set_clockrate(struct ath_hw *ah) in ath9k_hw_set_clockrate() argument
42 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_clockrate()
43 struct ath9k_channel *chan = ah->curchan; in ath9k_hw_set_clockrate()
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) in ath9k_hw_set_clockrate()
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) in ath9k_hw_set_clockrate()
67 common->clockrate = clockrate; in ath9k_hw_set_clockrate()
70 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) in ath9k_hw_mac_to_clks() argument
72 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_mac_to_clks()
74 return usecs * common->clockrate; in ath9k_hw_mac_to_clks()
77 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) in ath9k_hw_wait() argument
84 if ((REG_READ(ah, reg) & mask) == val) in ath9k_hw_wait()
90 ath_dbg(ath9k_hw_common(ah), ANY, in ath9k_hw_wait()
91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", in ath9k_hw_wait()
92 timeout, reg, REG_READ(ah, reg), mask, val); in ath9k_hw_wait()
98 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, in ath9k_hw_synth_delay() argument
111 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, in ath9k_hw_write_array() argument
116 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_write_array()
117 for (r = 0; r < array->ia_rows; r++) { in ath9k_hw_write_array()
118 REG_WRITE(ah, INI_RA(array, r, 0), in ath9k_hw_write_array()
122 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_write_array()
125 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size) in ath9k_hw_read_array() argument
132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__); in ath9k_hw_read_array()
138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__); in ath9k_hw_read_array()
145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size); in ath9k_hw_read_array()
167 u16 ath9k_hw_computetxtime(struct ath_hw *ah, in ath9k_hw_computetxtime() argument
186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { in ath9k_hw_computetxtime()
194 } else if (ah->curchan && in ath9k_hw_computetxtime()
195 IS_CHAN_HALF_RATE(ah->curchan)) { in ath9k_hw_computetxtime()
212 ath_err(ath9k_hw_common(ah), in ath9k_hw_computetxtime()
222 void ath9k_hw_get_channel_centers(struct ath_hw *ah, in ath9k_hw_get_channel_centers() argument
229 centers->ctl_center = centers->ext_center = in ath9k_hw_get_channel_centers()
230 centers->synth_center = chan->channel; in ath9k_hw_get_channel_centers()
235 centers->synth_center = in ath9k_hw_get_channel_centers()
236 chan->channel + HT40_CHANNEL_CENTER_SHIFT; in ath9k_hw_get_channel_centers()
239 centers->synth_center = in ath9k_hw_get_channel_centers()
240 chan->channel - HT40_CHANNEL_CENTER_SHIFT; in ath9k_hw_get_channel_centers()
241 extoff = -1; in ath9k_hw_get_channel_centers()
244 centers->ctl_center = in ath9k_hw_get_channel_centers()
245 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); in ath9k_hw_get_channel_centers()
247 centers->ext_center = in ath9k_hw_get_channel_centers()
248 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); in ath9k_hw_get_channel_centers()
255 static bool ath9k_hw_read_revisions(struct ath_hw *ah) in ath9k_hw_read_revisions() argument
260 if (ah->get_mac_revision) in ath9k_hw_read_revisions()
261 ah->hw_version.macRev = ah->get_mac_revision(); in ath9k_hw_read_revisions()
263 switch (ah->hw_version.devid) { in ath9k_hw_read_revisions()
265 ah->hw_version.macVersion = AR_SREV_VERSION_9100; in ath9k_hw_read_revisions()
268 ah->hw_version.macVersion = AR_SREV_VERSION_9330; in ath9k_hw_read_revisions()
269 if (!ah->get_mac_revision) { in ath9k_hw_read_revisions()
270 val = REG_READ(ah, AR_SREV(ah)); in ath9k_hw_read_revisions()
271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); in ath9k_hw_read_revisions()
275 ah->hw_version.macVersion = AR_SREV_VERSION_9340; in ath9k_hw_read_revisions()
278 ah->hw_version.macVersion = AR_SREV_VERSION_9550; in ath9k_hw_read_revisions()
281 ah->hw_version.macVersion = AR_SREV_VERSION_9531; in ath9k_hw_read_revisions()
284 ah->hw_version.macVersion = AR_SREV_VERSION_9561; in ath9k_hw_read_revisions()
288 srev = REG_READ(ah, AR_SREV(ah)); in ath9k_hw_read_revisions()
290 if (srev == -1) { in ath9k_hw_read_revisions()
291 ath_err(ath9k_hw_common(ah), in ath9k_hw_read_revisions()
296 val = srev & AR_SREV_ID(ah); in ath9k_hw_read_revisions()
300 ah->hw_version.macVersion = in ath9k_hw_read_revisions()
302 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); in ath9k_hw_read_revisions()
304 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ath9k_hw_read_revisions()
305 ah->is_pciexpress = true; in ath9k_hw_read_revisions()
307 ah->is_pciexpress = (val & in ath9k_hw_read_revisions()
310 if (!AR_SREV_9100(ah)) in ath9k_hw_read_revisions()
311 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); in ath9k_hw_read_revisions()
313 ah->hw_version.macRev = val & AR_SREV_REVISION; in ath9k_hw_read_revisions()
315 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) in ath9k_hw_read_revisions()
316 ah->is_pciexpress = true; in ath9k_hw_read_revisions()
326 static void ath9k_hw_disablepcie(struct ath_hw *ah) in ath9k_hw_disablepcie() argument
328 if (!AR_SREV_5416(ah)) in ath9k_hw_disablepcie()
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ath9k_hw_disablepcie()
332 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_disablepcie()
333 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); in ath9k_hw_disablepcie()
334 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); in ath9k_hw_disablepcie()
335 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); in ath9k_hw_disablepcie()
336 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); in ath9k_hw_disablepcie()
337 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_disablepcie()
338 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_disablepcie()
339 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); in ath9k_hw_disablepcie()
341 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); in ath9k_hw_disablepcie()
345 static bool ath9k_hw_chip_test(struct ath_hw *ah) in ath9k_hw_chip_test() argument
347 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_chip_test()
355 if (!AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_chip_test()
365 regHold[i] = REG_READ(ah, addr); in ath9k_hw_chip_test()
368 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
369 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
372 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", in ath9k_hw_chip_test()
379 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
380 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
383 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", in ath9k_hw_chip_test()
388 REG_WRITE(ah, regAddr[i], regHold[i]); in ath9k_hw_chip_test()
395 static void ath9k_hw_init_config(struct ath_hw *ah) in ath9k_hw_init_config() argument
397 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_config()
399 ah->config.dma_beacon_response_time = 1; in ath9k_hw_init_config()
400 ah->config.sw_beacon_response_time = 6; in ath9k_hw_init_config()
401 ah->config.cwm_ignore_extcca = false; in ath9k_hw_init_config()
402 ah->config.analog_shiftreg = 1; in ath9k_hw_init_config()
404 ah->config.rx_intr_mitigation = true; in ath9k_hw_init_config()
406 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_init_config()
407 ah->config.rimt_last = 500; in ath9k_hw_init_config()
408 ah->config.rimt_first = 2000; in ath9k_hw_init_config()
410 ah->config.rimt_last = 250; in ath9k_hw_init_config()
411 ah->config.rimt_first = 700; in ath9k_hw_init_config()
414 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ath9k_hw_init_config()
415 ah->config.pll_pwrsave = 7; in ath9k_hw_init_config()
419 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). in ath9k_hw_init_config()
430 * This issue is not present on PCI-Express devices or pre-AR5416 in ath9k_hw_init_config()
434 ah->config.serialize_regmode = SER_REG_MODE_AUTO; in ath9k_hw_init_config()
436 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { in ath9k_hw_init_config()
437 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || in ath9k_hw_init_config()
438 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && in ath9k_hw_init_config()
439 !ah->is_pciexpress)) { in ath9k_hw_init_config()
440 ah->config.serialize_regmode = SER_REG_MODE_ON; in ath9k_hw_init_config()
442 ah->config.serialize_regmode = SER_REG_MODE_OFF; in ath9k_hw_init_config()
447 ah->config.serialize_regmode); in ath9k_hw_init_config()
449 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) in ath9k_hw_init_config()
450 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; in ath9k_hw_init_config()
452 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; in ath9k_hw_init_config()
455 static void ath9k_hw_init_defaults(struct ath_hw *ah) in ath9k_hw_init_defaults() argument
457 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); in ath9k_hw_init_defaults()
459 regulatory->country_code = CTRY_DEFAULT; in ath9k_hw_init_defaults()
460 regulatory->power_limit = MAX_COMBINED_POWER; in ath9k_hw_init_defaults()
462 ah->hw_version.magic = AR5416_MAGIC; in ath9k_hw_init_defaults()
463 ah->hw_version.subvendorid = 0; in ath9k_hw_init_defaults()
465 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | in ath9k_hw_init_defaults()
467 if (AR_SREV_9100(ah)) in ath9k_hw_init_defaults()
468 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; in ath9k_hw_init_defaults()
470 ah->slottime = 9; in ath9k_hw_init_defaults()
471 ah->globaltxtimeout = (u32) -1; in ath9k_hw_init_defaults()
472 ah->power_mode = ATH9K_PM_UNDEFINED; in ath9k_hw_init_defaults()
473 ah->htc_reset_init = true; in ath9k_hw_init_defaults()
475 ah->tpc_enabled = false; in ath9k_hw_init_defaults()
477 ah->ani_function = ATH9K_ANI_ALL; in ath9k_hw_init_defaults()
478 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_init_defaults()
479 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; in ath9k_hw_init_defaults()
481 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) in ath9k_hw_init_defaults()
482 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); in ath9k_hw_init_defaults()
484 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); in ath9k_hw_init_defaults()
487 static void ath9k_hw_init_macaddr(struct ath_hw *ah) in ath9k_hw_init_macaddr() argument
489 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_macaddr()
495 if (is_valid_ether_addr(common->macaddr)) in ath9k_hw_init_macaddr()
499 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); in ath9k_hw_init_macaddr()
500 common->macaddr[2 * i] = eeval >> 8; in ath9k_hw_init_macaddr()
501 common->macaddr[2 * i + 1] = eeval & 0xff; in ath9k_hw_init_macaddr()
504 if (is_valid_ether_addr(common->macaddr)) in ath9k_hw_init_macaddr()
508 common->macaddr); in ath9k_hw_init_macaddr()
510 eth_random_addr(common->macaddr); in ath9k_hw_init_macaddr()
512 common->macaddr); in ath9k_hw_init_macaddr()
517 static int ath9k_hw_post_init(struct ath_hw *ah) in ath9k_hw_post_init() argument
519 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_post_init()
522 if (common->bus_ops->ath_bus_type != ATH_USB) { in ath9k_hw_post_init()
523 if (!ath9k_hw_chip_test(ah)) in ath9k_hw_post_init()
524 return -ENODEV; in ath9k_hw_post_init()
527 if (!AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_post_init()
528 ecode = ar9002_hw_rf_claim(ah); in ath9k_hw_post_init()
533 ecode = ath9k_hw_eeprom_init(ah); in ath9k_hw_post_init()
537 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", in ath9k_hw_post_init()
538 ah->eep_ops->get_eeprom_ver(ah), in ath9k_hw_post_init()
539 ah->eep_ops->get_eeprom_rev(ah)); in ath9k_hw_post_init()
541 ath9k_hw_ani_init(ah); in ath9k_hw_post_init()
547 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_post_init()
548 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); in ath9k_hw_post_init()
550 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; in ath9k_hw_post_init()
551 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; in ath9k_hw_post_init()
558 static int ath9k_hw_attach_ops(struct ath_hw *ah) in ath9k_hw_attach_ops() argument
560 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_attach_ops()
561 return ar9002_hw_attach_ops(ah); in ath9k_hw_attach_ops()
563 ar9003_hw_attach_ops(ah); in ath9k_hw_attach_ops()
568 static int __ath9k_hw_init(struct ath_hw *ah) in __ath9k_hw_init() argument
570 struct ath_common *common = ath9k_hw_common(ah); in __ath9k_hw_init()
573 if (!ath9k_hw_read_revisions(ah)) { in __ath9k_hw_init()
575 return -EOPNOTSUPP; in __ath9k_hw_init()
578 switch (ah->hw_version.macVersion) { in __ath9k_hw_init()
600 ah->hw_version.macVersion, ah->hw_version.macRev); in __ath9k_hw_init()
601 return -EOPNOTSUPP; in __ath9k_hw_init()
605 * Read back AR_WA(ah) into a permanent copy and set bits 14 and 17. in __ath9k_hw_init()
607 * read the reg when chip is asleep. in __ath9k_hw_init()
609 if (AR_SREV_9300_20_OR_LATER(ah)) { in __ath9k_hw_init()
610 ah->WARegVal = REG_READ(ah, AR_WA(ah)); in __ath9k_hw_init()
611 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | in __ath9k_hw_init()
615 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { in __ath9k_hw_init()
617 return -EIO; in __ath9k_hw_init()
620 if (AR_SREV_9565(ah)) { in __ath9k_hw_init()
621 ah->WARegVal |= AR_WA_BIT22; in __ath9k_hw_init()
622 REG_WRITE(ah, AR_WA(ah), ah->WARegVal); in __ath9k_hw_init()
625 ath9k_hw_init_defaults(ah); in __ath9k_hw_init()
626 ath9k_hw_init_config(ah); in __ath9k_hw_init()
628 r = ath9k_hw_attach_ops(ah); in __ath9k_hw_init()
632 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { in __ath9k_hw_init()
634 return -EIO; in __ath9k_hw_init()
637 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || in __ath9k_hw_init()
638 AR_SREV_9330(ah) || AR_SREV_9550(ah)) in __ath9k_hw_init()
639 ah->is_pciexpress = false; in __ath9k_hw_init()
641 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); in __ath9k_hw_init()
642 ath9k_hw_init_cal_settings(ah); in __ath9k_hw_init()
644 if (!ah->is_pciexpress) in __ath9k_hw_init()
645 ath9k_hw_disablepcie(ah); in __ath9k_hw_init()
647 r = ath9k_hw_post_init(ah); in __ath9k_hw_init()
651 ath9k_hw_init_mode_gain_regs(ah); in __ath9k_hw_init()
652 r = ath9k_hw_fill_cap_info(ah); in __ath9k_hw_init()
656 ath9k_hw_init_macaddr(ah); in __ath9k_hw_init()
657 ath9k_hw_init_hang_checks(ah); in __ath9k_hw_init()
659 common->state = ATH_HW_INITIALIZED; in __ath9k_hw_init()
664 int ath9k_hw_init(struct ath_hw *ah) in ath9k_hw_init() argument
667 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init()
670 switch (ah->hw_version.devid) { in ath9k_hw_init()
694 if (common->bus_ops->ath_bus_type == ATH_USB) in ath9k_hw_init()
697 ah->hw_version.devid); in ath9k_hw_init()
698 return -EOPNOTSUPP; in ath9k_hw_init()
701 ret = __ath9k_hw_init(ah); in ath9k_hw_init()
709 ath_dynack_init(ah); in ath9k_hw_init()
715 static void ath9k_hw_init_qos(struct ath_hw *ah) in ath9k_hw_init_qos() argument
717 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_init_qos()
719 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); in ath9k_hw_init_qos()
720 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); in ath9k_hw_init_qos()
722 REG_WRITE(ah, AR_QOS_NO_ACK, in ath9k_hw_init_qos()
724 SM(5, AR_QOS_NO_ACK_BIT_OFF) | in ath9k_hw_init_qos()
727 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); in ath9k_hw_init_qos()
728 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); in ath9k_hw_init_qos()
729 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); in ath9k_hw_init_qos()
730 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); in ath9k_hw_init_qos()
731 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); in ath9k_hw_init_qos()
733 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_init_qos()
736 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) in ar9003_get_pll_sqsum_dvc() argument
738 struct ath_common *common = ath9k_hw_common(ah); in ar9003_get_pll_sqsum_dvc()
741 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
743 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
745 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { in ar9003_get_pll_sqsum_dvc()
757 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; in ar9003_get_pll_sqsum_dvc()
761 static void ath9k_hw_init_pll(struct ath_hw *ah, in ath9k_hw_init_pll() argument
766 pll = ath9k_hw_compute_pll_control(ah, chan); in ath9k_hw_init_pll()
768 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { in ath9k_hw_init_pll()
770 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
774 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
777 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, in ath9k_hw_init_pll()
779 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, in ath9k_hw_init_pll()
781 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, in ath9k_hw_init_pll()
784 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
786 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
788 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
792 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, in ath9k_hw_init_pll()
795 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
798 } else if (AR_SREV_9330(ah)) { in ath9k_hw_init_pll()
801 if (ah->is_clk_25mhz) { in ath9k_hw_init_pll()
812 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); in ath9k_hw_init_pll()
815 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, in ath9k_hw_init_pll()
818 REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah), in ath9k_hw_init_pll()
823 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); in ath9k_hw_init_pll()
826 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); in ath9k_hw_init_pll()
827 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); in ath9k_hw_init_pll()
830 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, in ath9k_hw_init_pll()
832 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ath9k_hw_init_pll()
833 AR_SREV_9561(ah)) { in ath9k_hw_init_pll()
836 REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah), in ath9k_hw_init_pll()
840 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); in ath9k_hw_init_pll()
843 if (ah->is_clk_25mhz) { in ath9k_hw_init_pll()
844 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ath9k_hw_init_pll()
854 if (AR_SREV_9340(ah)) { in ath9k_hw_init_pll()
857 refdiv = 5; in ath9k_hw_init_pll()
860 pll2_divfrac = (AR_SREV_9531(ah) || in ath9k_hw_init_pll()
861 AR_SREV_9561(ah)) ? in ath9k_hw_init_pll()
867 regval = REG_READ(ah, AR_PHY_PLL_MODE); in ath9k_hw_init_pll()
868 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) in ath9k_hw_init_pll()
872 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); in ath9k_hw_init_pll()
875 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | in ath9k_hw_init_pll()
879 regval = REG_READ(ah, AR_PHY_PLL_MODE); in ath9k_hw_init_pll()
880 if (AR_SREV_9340(ah)) in ath9k_hw_init_pll()
886 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ath9k_hw_init_pll()
893 if (AR_SREV_9531(ah)) in ath9k_hw_init_pll()
901 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); in ath9k_hw_init_pll()
903 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) in ath9k_hw_init_pll()
904 REG_WRITE(ah, AR_PHY_PLL_MODE, in ath9k_hw_init_pll()
905 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); in ath9k_hw_init_pll()
907 REG_WRITE(ah, AR_PHY_PLL_MODE, in ath9k_hw_init_pll()
908 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); in ath9k_hw_init_pll()
913 if (AR_SREV_9565(ah)) in ath9k_hw_init_pll()
915 REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah), pll); in ath9k_hw_init_pll()
917 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ath9k_hw_init_pll()
918 AR_SREV_9550(ah)) in ath9k_hw_init_pll()
922 if (AR_SREV_9271(ah)) { in ath9k_hw_init_pll()
924 REG_WRITE(ah, 0x50040, 0x304); in ath9k_hw_init_pll()
929 REG_WRITE(ah, AR_RTC_SLEEP_CLK(ah), AR_RTC_FORCE_DERIVED_CLK); in ath9k_hw_init_pll()
932 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, in ath9k_hw_init_interrupt_masks() argument
943 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ath9k_hw_init_interrupt_masks()
944 AR_SREV_9561(ah)) in ath9k_hw_init_interrupt_masks()
947 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_init_interrupt_masks()
949 if (ah->config.rx_intr_mitigation) { in ath9k_hw_init_interrupt_masks()
957 if (ah->config.rx_intr_mitigation) { in ath9k_hw_init_interrupt_masks()
966 if (ah->config.tx_intr_mitigation) { in ath9k_hw_init_interrupt_masks()
974 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_init_interrupt_masks()
976 REG_WRITE(ah, AR_IMR, imr_reg); in ath9k_hw_init_interrupt_masks()
977 ah->imrs2_reg |= AR_IMR_S2_GTT; in ath9k_hw_init_interrupt_masks()
978 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_init_interrupt_masks()
980 if (ah->msi_enabled) { in ath9k_hw_init_interrupt_masks()
981 ah->msi_reg = REG_READ(ah, AR_PCIE_MSI(ah)); in ath9k_hw_init_interrupt_masks()
982 ah->msi_reg |= AR_PCIE_MSI_HW_DBI_WR_EN; in ath9k_hw_init_interrupt_masks()
983 ah->msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64; in ath9k_hw_init_interrupt_masks()
984 REG_WRITE(ah, AR_INTCFG, msi_cfg); in ath9k_hw_init_interrupt_masks()
985 ath_dbg(ath9k_hw_common(ah), ANY, in ath9k_hw_init_interrupt_masks()
987 REG_READ(ah, AR_INTCFG), msi_cfg); in ath9k_hw_init_interrupt_masks()
990 if (!AR_SREV_9100(ah)) { in ath9k_hw_init_interrupt_masks()
991 REG_WRITE(ah, AR_INTR_SYNC_CAUSE(ah), 0xFFFFFFFF); in ath9k_hw_init_interrupt_masks()
992 REG_WRITE(ah, AR_INTR_SYNC_ENABLE(ah), sync_default); in ath9k_hw_init_interrupt_masks()
993 REG_WRITE(ah, AR_INTR_SYNC_MASK(ah), 0); in ath9k_hw_init_interrupt_masks()
996 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_init_interrupt_masks()
998 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_init_interrupt_masks()
999 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE(ah), 0); in ath9k_hw_init_interrupt_masks()
1000 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK(ah), 0); in ath9k_hw_init_interrupt_masks()
1001 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE(ah), 0); in ath9k_hw_init_interrupt_masks()
1002 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK(ah), 0); in ath9k_hw_init_interrupt_masks()
1006 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) in ath9k_hw_set_sifs_time() argument
1008 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); in ath9k_hw_set_sifs_time()
1010 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); in ath9k_hw_set_sifs_time()
1013 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) in ath9k_hw_setslottime() argument
1015 u32 val = ath9k_hw_mac_to_clks(ah, us); in ath9k_hw_setslottime()
1017 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); in ath9k_hw_setslottime()
1020 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) in ath9k_hw_set_ack_timeout() argument
1022 u32 val = ath9k_hw_mac_to_clks(ah, us); in ath9k_hw_set_ack_timeout()
1024 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); in ath9k_hw_set_ack_timeout()
1027 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) in ath9k_hw_set_cts_timeout() argument
1029 u32 val = ath9k_hw_mac_to_clks(ah, us); in ath9k_hw_set_cts_timeout()
1031 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); in ath9k_hw_set_cts_timeout()
1034 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) in ath9k_hw_set_global_txtimeout() argument
1037 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", in ath9k_hw_set_global_txtimeout()
1039 ah->globaltxtimeout = (u32) -1; in ath9k_hw_set_global_txtimeout()
1042 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); in ath9k_hw_set_global_txtimeout()
1043 ah->globaltxtimeout = tu; in ath9k_hw_set_global_txtimeout()
1048 void ath9k_hw_init_global_settings(struct ath_hw *ah) in ath9k_hw_init_global_settings() argument
1050 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_global_settings()
1051 const struct ath9k_channel *chan = ah->curchan; in ath9k_hw_init_global_settings()
1056 u32 reg; in ath9k_hw_init_global_settings() local
1058 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", in ath9k_hw_init_global_settings()
1059 ah->misc_mode); in ath9k_hw_init_global_settings()
1064 if (ah->misc_mode != 0) in ath9k_hw_init_global_settings()
1065 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); in ath9k_hw_init_global_settings()
1067 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ath9k_hw_init_global_settings()
1082 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ath9k_hw_init_global_settings()
1091 rx_lat = (rx_lat * 4) - 1; in ath9k_hw_init_global_settings()
1093 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ath9k_hw_init_global_settings()
1101 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { in ath9k_hw_init_global_settings()
1103 reg = AR_USEC_ASYNC_FIFO; in ath9k_hw_init_global_settings()
1105 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ in ath9k_hw_init_global_settings()
1106 common->clockrate; in ath9k_hw_init_global_settings()
1107 reg = REG_READ(ah, AR_USEC); in ath9k_hw_init_global_settings()
1109 rx_lat = MS(reg, AR_USEC_RX_LAT); in ath9k_hw_init_global_settings()
1110 tx_lat = MS(reg, AR_USEC_TX_LAT); in ath9k_hw_init_global_settings()
1112 slottime = ah->slottime; in ath9k_hw_init_global_settings()
1115 /* As defined by IEEE 802.11-2007 17.3.8.6 */ in ath9k_hw_init_global_settings()
1116 slottime += 3 * ah->coverage_class; in ath9k_hw_init_global_settings()
1129 acktimeout += 64 - sifstime - ah->slottime; in ath9k_hw_init_global_settings()
1130 ctstimeout += 48 - sifstime - ah->slottime; in ath9k_hw_init_global_settings()
1133 if (ah->dynack.enabled) { in ath9k_hw_init_global_settings()
1134 acktimeout = ah->dynack.ackto; in ath9k_hw_init_global_settings()
1136 slottime = (acktimeout - 3) / 2; in ath9k_hw_init_global_settings()
1138 ah->dynack.ackto = acktimeout; in ath9k_hw_init_global_settings()
1141 ath9k_hw_set_sifs_time(ah, sifstime); in ath9k_hw_init_global_settings()
1142 ath9k_hw_setslottime(ah, slottime); in ath9k_hw_init_global_settings()
1143 ath9k_hw_set_ack_timeout(ah, acktimeout); in ath9k_hw_init_global_settings()
1144 ath9k_hw_set_cts_timeout(ah, ctstimeout); in ath9k_hw_init_global_settings()
1145 if (ah->globaltxtimeout != (u32) -1) in ath9k_hw_init_global_settings()
1146 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); in ath9k_hw_init_global_settings()
1148 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); in ath9k_hw_init_global_settings()
1149 REG_RMW(ah, AR_USEC, in ath9k_hw_init_global_settings()
1150 (common->clockrate - 1) | in ath9k_hw_init_global_settings()
1156 REG_RMW(ah, AR_TXSIFS, in ath9k_hw_init_global_settings()
1162 void ath9k_hw_deinit(struct ath_hw *ah) in ath9k_hw_deinit() argument
1164 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_deinit()
1166 if (common->state < ATH_HW_INITIALIZED) in ath9k_hw_deinit()
1169 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); in ath9k_hw_deinit()
1177 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) in ath9k_regd_get_ctl() argument
1179 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); in ath9k_regd_get_ctl()
1193 static inline void ath9k_hw_set_dma(struct ath_hw *ah) in ath9k_hw_set_dma() argument
1195 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_dma()
1198 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_dma()
1203 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_dma()
1204 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); in ath9k_hw_set_dma()
1209 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); in ath9k_hw_set_dma()
1211 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_dma()
1214 * Restore TX Trigger Level to its pre-reset value. in ath9k_hw_set_dma()
1218 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_dma()
1219 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); in ath9k_hw_set_dma()
1221 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_dma()
1226 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); in ath9k_hw_set_dma()
1231 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); in ath9k_hw_set_dma()
1233 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_dma()
1234 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); in ath9k_hw_set_dma()
1235 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); in ath9k_hw_set_dma()
1237 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - in ath9k_hw_set_dma()
1238 ah->caps.rx_status_len); in ath9k_hw_set_dma()
1245 if (AR_SREV_9285(ah)) { in ath9k_hw_set_dma()
1251 } else if (AR_SREV_9340_13_OR_LATER(ah)) { in ath9k_hw_set_dma()
1258 if (!AR_SREV_9271(ah)) in ath9k_hw_set_dma()
1259 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); in ath9k_hw_set_dma()
1261 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_dma()
1263 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_dma()
1264 ath9k_hw_reset_txstatus_ring(ah); in ath9k_hw_set_dma()
1267 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) in ath9k_hw_set_operating_mode() argument
1272 ENABLE_REG_RMW_BUFFER(ah); in ath9k_hw_set_operating_mode()
1275 if (!AR_SREV_9340_13(ah)) { in ath9k_hw_set_operating_mode()
1277 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1287 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1290 if (!ah->is_monitoring) in ath9k_hw_set_operating_mode()
1294 REG_RMW(ah, AR_STA_ID1, set, mask); in ath9k_hw_set_operating_mode()
1295 REG_RMW_BUFFER_FLUSH(ah); in ath9k_hw_set_operating_mode()
1298 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, in ath9k_hw_get_delta_slope_vals() argument
1303 for (coef_exp = 31; coef_exp > 0; coef_exp--) in ath9k_hw_get_delta_slope_vals()
1307 coef_exp = 14 - (coef_exp - COEF_SCALE_S); in ath9k_hw_get_delta_slope_vals()
1309 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); in ath9k_hw_get_delta_slope_vals()
1311 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); in ath9k_hw_get_delta_slope_vals()
1312 *coef_exponent = coef_exp - 16; in ath9k_hw_get_delta_slope_vals()
1317 * - doing a cold reset
1318 * - we have pending frames in the TX queues.
1320 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) in ath9k_hw_ar9330_reset_war() argument
1325 npend = ath9k_hw_numtxpending(ah, i); in ath9k_hw_ar9330_reset_war()
1330 if (ah->external_reset && in ath9k_hw_ar9330_reset_war()
1334 ath_dbg(ath9k_hw_common(ah), RESET, in ath9k_hw_ar9330_reset_war()
1337 reset_err = ah->external_reset(); in ath9k_hw_ar9330_reset_war()
1339 ath_err(ath9k_hw_common(ah), in ath9k_hw_ar9330_reset_war()
1345 REG_WRITE(ah, AR_RTC_RESET(ah), 1); in ath9k_hw_ar9330_reset_war()
1351 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) in ath9k_hw_set_reset() argument
1356 if (AR_SREV_9100(ah)) { in ath9k_hw_set_reset()
1357 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK(ah), in ath9k_hw_set_reset()
1359 (void)REG_READ(ah, AR_RTC_DERIVED_CLK(ah)); in ath9k_hw_set_reset()
1362 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_reset()
1364 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_reset()
1365 REG_WRITE(ah, AR_WA(ah), ah->WARegVal); in ath9k_hw_set_reset()
1369 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset()
1372 if (AR_SREV_9100(ah)) { in ath9k_hw_set_reset()
1376 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE(ah)); in ath9k_hw_set_reset()
1377 if (AR_SREV_9340(ah)) in ath9k_hw_set_reset()
1385 REG_WRITE(ah, AR_INTR_SYNC_ENABLE(ah), 0); in ath9k_hw_set_reset()
1388 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset()
1390 REG_WRITE(ah, AR_RC, val); in ath9k_hw_set_reset()
1392 } else if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset()
1393 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset()
1400 if (AR_SREV_9330(ah)) { in ath9k_hw_set_reset()
1401 if (!ath9k_hw_ar9330_reset_war(ah, type)) in ath9k_hw_set_reset()
1405 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_set_reset()
1406 ar9003_mci_check_gpm_offset(ah); in ath9k_hw_set_reset()
1409 * RTC_RC reg read in ath9k_hw_set_reset()
1411 if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) { in ath9k_hw_set_reset()
1412 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); in ath9k_hw_set_reset()
1413 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK, in ath9k_hw_set_reset()
1415 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); in ath9k_hw_set_reset()
1418 REG_WRITE(ah, AR_RTC_RC(ah), rst_flags); in ath9k_hw_set_reset()
1420 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_reset()
1422 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset()
1424 else if (AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1429 REG_WRITE(ah, AR_RTC_RC(ah), 0); in ath9k_hw_set_reset()
1430 if (!ath9k_hw_wait(ah, AR_RTC_RC(ah), AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { in ath9k_hw_set_reset()
1431 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); in ath9k_hw_set_reset()
1435 if (!AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1436 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset()
1438 if (AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1444 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) in ath9k_hw_set_reset_power_on() argument
1446 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_reset_power_on()
1448 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_reset_power_on()
1449 REG_WRITE(ah, AR_WA(ah), ah->WARegVal); in ath9k_hw_set_reset_power_on()
1453 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset_power_on()
1456 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset_power_on()
1457 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset_power_on()
1459 REG_WRITE(ah, AR_RTC_RESET(ah), 0); in ath9k_hw_set_reset_power_on()
1461 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_reset_power_on()
1465 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset_power_on()
1466 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset_power_on()
1468 REG_WRITE(ah, AR_RTC_RESET(ah), 1); in ath9k_hw_set_reset_power_on()
1470 if (!ath9k_hw_wait(ah, in ath9k_hw_set_reset_power_on()
1471 AR_RTC_STATUS(ah), in ath9k_hw_set_reset_power_on()
1472 AR_RTC_STATUS_M(ah), in ath9k_hw_set_reset_power_on()
1475 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); in ath9k_hw_set_reset_power_on()
1479 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); in ath9k_hw_set_reset_power_on()
1482 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) in ath9k_hw_set_reset_reg() argument
1486 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_reset_reg()
1487 REG_WRITE(ah, AR_WA(ah), ah->WARegVal); in ath9k_hw_set_reset_reg()
1491 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), in ath9k_hw_set_reset_reg()
1494 if (!ah->reset_power_on) in ath9k_hw_set_reset_reg()
1499 ret = ath9k_hw_set_reset_power_on(ah); in ath9k_hw_set_reset_reg()
1501 ah->reset_power_on = true; in ath9k_hw_set_reset_reg()
1505 ret = ath9k_hw_set_reset(ah, type); in ath9k_hw_set_reset_reg()
1514 static bool ath9k_hw_chip_reset(struct ath_hw *ah, in ath9k_hw_chip_reset() argument
1519 if (AR_SREV_9280(ah)) { in ath9k_hw_chip_reset()
1520 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) in ath9k_hw_chip_reset()
1524 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || in ath9k_hw_chip_reset()
1525 (REG_READ(ah, AR_CR) & AR_CR_RXE(ah))) in ath9k_hw_chip_reset()
1528 if (!ath9k_hw_set_reset_reg(ah, reset_type)) in ath9k_hw_chip_reset()
1531 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_chip_reset()
1534 ah->chip_fullsleep = false; in ath9k_hw_chip_reset()
1536 if (AR_SREV_9330(ah)) in ath9k_hw_chip_reset()
1537 ar9003_hw_internal_regulator_apply(ah); in ath9k_hw_chip_reset()
1538 ath9k_hw_init_pll(ah, chan); in ath9k_hw_chip_reset()
1543 static bool ath9k_hw_channel_change(struct ath_hw *ah, in ath9k_hw_channel_change() argument
1546 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_channel_change()
1547 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_channel_change()
1553 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { in ath9k_hw_channel_change()
1554 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; in ath9k_hw_channel_change()
1560 if (ath9k_hw_numtxpending(ah, qnum)) { in ath9k_hw_channel_change()
1567 if (!ath9k_hw_rfbus_req(ah)) { in ath9k_hw_channel_change()
1573 ath9k_hw_mark_phy_inactive(ah); in ath9k_hw_channel_change()
1574 udelay(5); in ath9k_hw_channel_change()
1577 ath9k_hw_init_pll(ah, chan); in ath9k_hw_channel_change()
1579 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { in ath9k_hw_channel_change()
1585 ath9k_hw_set_channel_regs(ah, chan); in ath9k_hw_channel_change()
1587 r = ath9k_hw_rf_set_freq(ah, chan); in ath9k_hw_channel_change()
1592 ath9k_hw_set_clockrate(ah); in ath9k_hw_channel_change()
1593 ath9k_hw_apply_txpower(ah, chan, false); in ath9k_hw_channel_change()
1595 ath9k_hw_set_delta_slope(ah, chan); in ath9k_hw_channel_change()
1596 ath9k_hw_spur_mitigate_freq(ah, chan); in ath9k_hw_channel_change()
1599 ah->eep_ops->set_board_values(ah, chan); in ath9k_hw_channel_change()
1601 ath9k_hw_init_bb(ah, chan); in ath9k_hw_channel_change()
1602 ath9k_hw_rfbus_done(ah); in ath9k_hw_channel_change()
1605 ah->ah_flags |= AH_FASTCC; in ath9k_hw_channel_change()
1606 ath9k_hw_init_cal(ah, chan); in ath9k_hw_channel_change()
1607 ah->ah_flags &= ~AH_FASTCC; in ath9k_hw_channel_change()
1613 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) in ath9k_hw_apply_gpio_override() argument
1615 u32 gpio_mask = ah->gpio_mask; in ath9k_hw_apply_gpio_override()
1622 ath9k_hw_gpio_request_out(ah, i, NULL, in ath9k_hw_apply_gpio_override()
1624 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); in ath9k_hw_apply_gpio_override()
1628 void ath9k_hw_check_nav(struct ath_hw *ah) in ath9k_hw_check_nav() argument
1630 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_check_nav()
1633 val = REG_READ(ah, AR_NAV); in ath9k_hw_check_nav()
1636 REG_WRITE(ah, AR_NAV, 0); in ath9k_hw_check_nav()
1641 bool ath9k_hw_check_alive(struct ath_hw *ah) in ath9k_hw_check_alive() argument
1644 u32 reg, last_val; in ath9k_hw_check_alive() local
1647 if (REG_READ(ah, AR_CFG) == 0xdeadbeef) in ath9k_hw_check_alive()
1650 if (AR_SREV_9300(ah)) in ath9k_hw_check_alive()
1651 return !ath9k_hw_detect_mac_hang(ah); in ath9k_hw_check_alive()
1653 if (AR_SREV_9285_12_OR_LATER(ah)) in ath9k_hw_check_alive()
1656 last_val = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_check_alive()
1658 reg = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_check_alive()
1659 if (reg != last_val) in ath9k_hw_check_alive()
1663 last_val = reg; in ath9k_hw_check_alive()
1664 if ((reg & 0x7E7FFFEF) == 0x00702400) in ath9k_hw_check_alive()
1667 switch (reg & 0x7E000B00) { in ath9k_hw_check_alive()
1675 } while (count-- > 0); in ath9k_hw_check_alive()
1681 static void ath9k_hw_init_mfp(struct ath_hw *ah) in ath9k_hw_init_mfp() argument
1684 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_init_mfp()
1687 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, in ath9k_hw_init_mfp()
1689 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah)) in ath9k_hw_init_mfp()
1690 ah->sw_mgmt_crypto_tx = true; in ath9k_hw_init_mfp()
1692 ah->sw_mgmt_crypto_tx = false; in ath9k_hw_init_mfp()
1693 ah->sw_mgmt_crypto_rx = false; in ath9k_hw_init_mfp()
1694 } else if (AR_SREV_9160_10_OR_LATER(ah)) { in ath9k_hw_init_mfp()
1696 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp()
1698 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp()
1700 ah->sw_mgmt_crypto_tx = true; in ath9k_hw_init_mfp()
1701 ah->sw_mgmt_crypto_rx = true; in ath9k_hw_init_mfp()
1703 ah->sw_mgmt_crypto_tx = true; in ath9k_hw_init_mfp()
1704 ah->sw_mgmt_crypto_rx = true; in ath9k_hw_init_mfp()
1708 static void ath9k_hw_reset_opmode(struct ath_hw *ah, in ath9k_hw_reset_opmode() argument
1711 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_reset_opmode()
1713 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_reset_opmode()
1715 REG_RMW(ah, AR_STA_ID1, macStaId1 in ath9k_hw_reset_opmode()
1717 | ah->sta_id1_defaults, in ath9k_hw_reset_opmode()
1720 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); in ath9k_hw_reset_opmode()
1721 ath9k_hw_write_associd(ah); in ath9k_hw_reset_opmode()
1722 REG_WRITE(ah, AR_ISR, ~0); in ath9k_hw_reset_opmode()
1723 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); in ath9k_hw_reset_opmode()
1725 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_reset_opmode()
1727 ath9k_hw_set_operating_mode(ah, ah->opmode); in ath9k_hw_reset_opmode()
1730 static void ath9k_hw_init_queues(struct ath_hw *ah) in ath9k_hw_init_queues() argument
1734 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_init_queues()
1737 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); in ath9k_hw_init_queues()
1739 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_init_queues()
1741 ah->intr_txqs = 0; in ath9k_hw_init_queues()
1743 ath9k_hw_resettxqueue(ah, i); in ath9k_hw_init_queues()
1749 static void ath9k_hw_init_desc(struct ath_hw *ah) in ath9k_hw_init_desc() argument
1751 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_desc()
1753 if (AR_SREV_9100(ah)) { in ath9k_hw_init_desc()
1755 mask = REG_READ(ah, AR_CFG); in ath9k_hw_init_desc()
1761 REG_WRITE(ah, AR_CFG, mask); in ath9k_hw_init_desc()
1763 REG_READ(ah, AR_CFG)); in ath9k_hw_init_desc()
1766 if (common->bus_ops->ath_bus_type == ATH_USB) { in ath9k_hw_init_desc()
1768 if (AR_SREV_9271(ah)) in ath9k_hw_init_desc()
1769 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); in ath9k_hw_init_desc()
1771 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_init_desc()
1774 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || in ath9k_hw_init_desc()
1775 AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ath9k_hw_init_desc()
1776 AR_SREV_9561(ah)) in ath9k_hw_init_desc()
1777 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); in ath9k_hw_init_desc()
1779 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_init_desc()
1788 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) in ath9k_hw_do_fastcc() argument
1790 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_do_fastcc()
1791 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_do_fastcc()
1794 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) in ath9k_hw_do_fastcc()
1797 if (ah->chip_fullsleep) in ath9k_hw_do_fastcc()
1800 if (!ah->curchan) in ath9k_hw_do_fastcc()
1803 if (chan->channel == ah->curchan->channel) in ath9k_hw_do_fastcc()
1806 if ((ah->curchan->channelFlags | chan->channelFlags) & in ath9k_hw_do_fastcc()
1811 * If cross-band fcc is not supoprted, bail out if channelFlags differ. in ath9k_hw_do_fastcc()
1813 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && in ath9k_hw_do_fastcc()
1814 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) in ath9k_hw_do_fastcc()
1817 if (!ath9k_hw_check_alive(ah)) in ath9k_hw_do_fastcc()
1822 * re-using are present. in ath9k_hw_do_fastcc()
1824 if (AR_SREV_9462(ah) && (ah->caldata && in ath9k_hw_do_fastcc()
1825 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || in ath9k_hw_do_fastcc()
1826 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || in ath9k_hw_do_fastcc()
1827 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) in ath9k_hw_do_fastcc()
1830 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", in ath9k_hw_do_fastcc()
1831 ah->curchan->channel, chan->channel); in ath9k_hw_do_fastcc()
1833 ret = ath9k_hw_channel_change(ah, chan); in ath9k_hw_do_fastcc()
1837 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_do_fastcc()
1838 ar9003_mci_2g5g_switch(ah, false); in ath9k_hw_do_fastcc()
1840 ath9k_hw_loadnf(ah, ah->curchan); in ath9k_hw_do_fastcc()
1841 ath9k_hw_start_nfcal(ah, true); in ath9k_hw_do_fastcc()
1843 if (AR_SREV_9271(ah)) in ath9k_hw_do_fastcc()
1844 ar9002_hw_load_ani_reg(ah, chan); in ath9k_hw_do_fastcc()
1848 return -EINVAL; in ath9k_hw_do_fastcc()
1859 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, in ath9k_hw_reset() argument
1862 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_reset()
1871 bool save_fullsleep = ah->chip_fullsleep; in ath9k_hw_reset()
1873 if (ath9k_hw_mci_is_enabled(ah)) { in ath9k_hw_reset()
1874 start_mci_reset = ar9003_mci_start_reset(ah, chan); in ath9k_hw_reset()
1879 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_reset()
1880 return -EIO; in ath9k_hw_reset()
1882 if (ah->curchan && !ah->chip_fullsleep) in ath9k_hw_reset()
1883 ath9k_hw_getnf(ah, ah->curchan); in ath9k_hw_reset()
1885 ah->caldata = caldata; in ath9k_hw_reset()
1886 if (caldata && (chan->channel != caldata->channel || in ath9k_hw_reset()
1887 chan->channelFlags != caldata->channelFlags)) { in ath9k_hw_reset()
1890 ath9k_init_nfcal_hist_buffer(ah, chan); in ath9k_hw_reset()
1892 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags); in ath9k_hw_reset()
1894 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); in ath9k_hw_reset()
1897 r = ath9k_hw_do_fastcc(ah, chan); in ath9k_hw_reset()
1902 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
1903 ar9003_mci_stop_bt(ah, save_fullsleep); in ath9k_hw_reset()
1905 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); in ath9k_hw_reset()
1909 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; in ath9k_hw_reset()
1913 tsf = ath9k_hw_gettsf64(ah); in ath9k_hw_reset()
1915 saveLedState = REG_READ(ah, AR_CFG_LED) & in ath9k_hw_reset()
1919 ath9k_hw_mark_phy_inactive(ah); in ath9k_hw_reset()
1921 ah->paprd_table_write_done = false; in ath9k_hw_reset()
1924 if (AR_SREV_9271(ah) && ah->htc_reset_init) { in ath9k_hw_reset()
1925 REG_WRITE(ah, in ath9k_hw_reset()
1931 if (!ath9k_hw_chip_reset(ah, chan)) { in ath9k_hw_reset()
1933 return -EINVAL; in ath9k_hw_reset()
1937 if (AR_SREV_9271(ah) && ah->htc_reset_init) { in ath9k_hw_reset()
1938 ah->htc_reset_init = false; in ath9k_hw_reset()
1939 REG_WRITE(ah, in ath9k_hw_reset()
1947 ath9k_hw_settsf64(ah, tsf + tsf_offset); in ath9k_hw_reset()
1949 if (AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_reset()
1950 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah), AR_GPIO_JTAG_DISABLE); in ath9k_hw_reset()
1952 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_reset()
1953 ar9002_hw_enable_async_fifo(ah); in ath9k_hw_reset()
1955 r = ath9k_hw_process_ini(ah, chan); in ath9k_hw_reset()
1959 ath9k_hw_set_rfmode(ah, chan); in ath9k_hw_reset()
1961 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
1962 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); in ath9k_hw_reset()
1969 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { in ath9k_hw_reset()
1971 ath9k_hw_settsf64(ah, tsf + tsf_offset); in ath9k_hw_reset()
1974 ath9k_hw_init_mfp(ah); in ath9k_hw_reset()
1976 ath9k_hw_set_delta_slope(ah, chan); in ath9k_hw_reset()
1977 ath9k_hw_spur_mitigate_freq(ah, chan); in ath9k_hw_reset()
1978 ah->eep_ops->set_board_values(ah, chan); in ath9k_hw_reset()
1980 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); in ath9k_hw_reset()
1982 r = ath9k_hw_rf_set_freq(ah, chan); in ath9k_hw_reset()
1986 ath9k_hw_set_clockrate(ah); in ath9k_hw_reset()
1988 ath9k_hw_init_queues(ah); in ath9k_hw_reset()
1989 ath9k_hw_init_interrupt_masks(ah, ah->opmode); in ath9k_hw_reset()
1990 ath9k_hw_ani_cache_ini_regs(ah); in ath9k_hw_reset()
1991 ath9k_hw_init_qos(ah); in ath9k_hw_reset()
1993 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) in ath9k_hw_reset()
1994 ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill"); in ath9k_hw_reset()
1996 ath9k_hw_init_global_settings(ah); in ath9k_hw_reset()
1998 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { in ath9k_hw_reset()
1999 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, in ath9k_hw_reset()
2001 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, in ath9k_hw_reset()
2003 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_reset()
2007 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); in ath9k_hw_reset()
2009 ath9k_hw_set_dma(ah); in ath9k_hw_reset()
2011 if (!ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
2012 REG_WRITE(ah, AR_OBS(ah), 8); in ath9k_hw_reset()
2014 ENABLE_REG_RMW_BUFFER(ah); in ath9k_hw_reset()
2015 if (ah->config.rx_intr_mitigation) { in ath9k_hw_reset()
2016 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); in ath9k_hw_reset()
2017 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); in ath9k_hw_reset()
2020 if (ah->config.tx_intr_mitigation) { in ath9k_hw_reset()
2021 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); in ath9k_hw_reset()
2022 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); in ath9k_hw_reset()
2024 REG_RMW_BUFFER_FLUSH(ah); in ath9k_hw_reset()
2026 ath9k_hw_init_bb(ah, chan); in ath9k_hw_reset()
2029 clear_bit(TXIQCAL_DONE, &caldata->cal_flags); in ath9k_hw_reset()
2030 clear_bit(TXCLCAL_DONE, &caldata->cal_flags); in ath9k_hw_reset()
2032 if (!ath9k_hw_init_cal(ah, chan)) in ath9k_hw_reset()
2033 return -EIO; in ath9k_hw_reset()
2035 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) in ath9k_hw_reset()
2036 return -EIO; in ath9k_hw_reset()
2038 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_reset()
2040 ath9k_hw_restore_chainmask(ah); in ath9k_hw_reset()
2041 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); in ath9k_hw_reset()
2043 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_reset()
2045 ath9k_hw_gen_timer_start_tsf2(ah); in ath9k_hw_reset()
2047 ath9k_hw_init_desc(ah); in ath9k_hw_reset()
2049 if (ath9k_hw_btcoex_is_enabled(ah)) in ath9k_hw_reset()
2050 ath9k_hw_btcoex_enable(ah); in ath9k_hw_reset()
2052 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
2053 ar9003_mci_check_bt(ah); in ath9k_hw_reset()
2055 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_reset()
2056 ath9k_hw_loadnf(ah, chan); in ath9k_hw_reset()
2057 ath9k_hw_start_nfcal(ah, true); in ath9k_hw_reset()
2060 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_reset()
2061 ar9003_hw_bb_watchdog_config(ah); in ath9k_hw_reset()
2063 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) in ath9k_hw_reset()
2064 ar9003_hw_disable_phy_restart(ah); in ath9k_hw_reset()
2066 ath9k_hw_apply_gpio_override(ah); in ath9k_hw_reset()
2068 if (AR_SREV_9565(ah) && common->bt_ant_diversity) in ath9k_hw_reset()
2069 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); in ath9k_hw_reset()
2071 if (ah->hw->conf.radar_enabled) { in ath9k_hw_reset()
2073 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); in ath9k_hw_reset()
2074 ath9k_hw_set_radar_params(ah); in ath9k_hw_reset()
2086 * Notify Power Mgt is disabled in self-generated frames.
2089 static void ath9k_set_power_sleep(struct ath_hw *ah) in ath9k_set_power_sleep() argument
2091 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_set_power_sleep()
2093 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_set_power_sleep()
2094 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
2095 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
2096 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); in ath9k_set_power_sleep()
2098 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); in ath9k_set_power_sleep()
2106 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_sleep()
2108 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_set_power_sleep()
2111 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) in ath9k_set_power_sleep()
2112 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); in ath9k_set_power_sleep()
2115 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { in ath9k_set_power_sleep()
2116 REG_CLR_BIT(ah, AR_RTC_RESET(ah), AR_RTC_RESET_EN); in ath9k_set_power_sleep()
2120 /* Clear Bit 14 of AR_WA(ah) after putting chip into Full Sleep mode. */ in ath9k_set_power_sleep()
2121 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_set_power_sleep()
2122 REG_WRITE(ah, AR_WA(ah), ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_sleep()
2126 * Notify Power Management is enabled in self-generating
2130 static void ath9k_set_power_network_sleep(struct ath_hw *ah) in ath9k_set_power_network_sleep() argument
2132 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_set_power_network_sleep()
2134 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_set_power_network_sleep()
2136 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { in ath9k_set_power_network_sleep()
2138 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), in ath9k_set_power_network_sleep()
2146 * re-enter network sleep mode frequently, which in in ath9k_set_power_network_sleep()
2151 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_set_power_network_sleep()
2152 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, in ath9k_set_power_network_sleep()
2158 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_network_sleep()
2160 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_set_power_network_sleep()
2164 /* Clear Bit 14 of AR_WA(ah) after putting chip into Net Sleep mode. */ in ath9k_set_power_network_sleep()
2165 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_set_power_network_sleep()
2166 REG_WRITE(ah, AR_WA(ah), ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_network_sleep()
2169 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) in ath9k_hw_set_power_awake() argument
2174 /* Set Bits 14 and 17 of AR_WA(ah) before powering on the chip. */ in ath9k_hw_set_power_awake()
2175 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_power_awake()
2176 REG_WRITE(ah, AR_WA(ah), ah->WARegVal); in ath9k_hw_set_power_awake()
2180 if ((REG_READ(ah, AR_RTC_STATUS(ah)) & in ath9k_hw_set_power_awake()
2181 AR_RTC_STATUS_M(ah)) == AR_RTC_STATUS_SHUTDOWN) { in ath9k_hw_set_power_awake()
2182 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { in ath9k_hw_set_power_awake()
2185 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_power_awake()
2186 ath9k_hw_init_pll(ah, NULL); in ath9k_hw_set_power_awake()
2188 if (AR_SREV_9100(ah)) in ath9k_hw_set_power_awake()
2189 REG_SET_BIT(ah, AR_RTC_RESET(ah), in ath9k_hw_set_power_awake()
2192 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE(ah), in ath9k_hw_set_power_awake()
2194 if (AR_SREV_9100(ah)) in ath9k_hw_set_power_awake()
2199 for (i = POWER_UP_TIME / 50; i > 0; i--) { in ath9k_hw_set_power_awake()
2200 val = REG_READ(ah, AR_RTC_STATUS(ah)) & AR_RTC_STATUS_M(ah); in ath9k_hw_set_power_awake()
2204 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE(ah), in ath9k_hw_set_power_awake()
2208 ath_err(ath9k_hw_common(ah), in ath9k_hw_set_power_awake()
2214 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_set_power_awake()
2215 ar9003_mci_set_power_awake(ah); in ath9k_hw_set_power_awake()
2217 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_hw_set_power_awake()
2222 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) in ath9k_hw_setpower() argument
2224 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_setpower()
2228 "FULL-SLEEP", in ath9k_hw_setpower()
2233 if (ah->power_mode == mode) in ath9k_hw_setpower()
2236 ath_dbg(common, RESET, "%s -> %s\n", in ath9k_hw_setpower()
2237 modes[ah->power_mode], modes[mode]); in ath9k_hw_setpower()
2241 status = ath9k_hw_set_power_awake(ah); in ath9k_hw_setpower()
2244 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_setpower()
2245 ar9003_mci_set_full_sleep(ah); in ath9k_hw_setpower()
2247 ath9k_set_power_sleep(ah); in ath9k_hw_setpower()
2248 ah->chip_fullsleep = true; in ath9k_hw_setpower()
2251 ath9k_set_power_network_sleep(ah); in ath9k_hw_setpower()
2257 ah->power_mode = mode; in ath9k_hw_setpower()
2265 if (!(ah->ah_flags & AH_UNPLUGGED)) in ath9k_hw_setpower()
2276 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) in ath9k_hw_beaconinit() argument
2280 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_beaconinit()
2282 switch (ah->opmode) { in ath9k_hw_beaconinit()
2284 REG_SET_BIT(ah, AR_TXCFG, in ath9k_hw_beaconinit()
2289 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); in ath9k_hw_beaconinit()
2290 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - in ath9k_hw_beaconinit()
2291 TU_TO_USEC(ah->config.dma_beacon_response_time)); in ath9k_hw_beaconinit()
2292 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - in ath9k_hw_beaconinit()
2293 TU_TO_USEC(ah->config.sw_beacon_response_time)); in ath9k_hw_beaconinit()
2298 ath_dbg(ath9k_hw_common(ah), BEACON, in ath9k_hw_beaconinit()
2299 "%s: unsupported opmode: %d\n", __func__, ah->opmode); in ath9k_hw_beaconinit()
2303 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2304 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2305 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2307 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_beaconinit()
2309 REG_SET_BIT(ah, AR_TIMER_MODE, flags); in ath9k_hw_beaconinit()
2313 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, in ath9k_hw_set_sta_beacon_timers() argument
2317 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_set_sta_beacon_timers()
2318 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_sta_beacon_timers()
2320 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_sta_beacon_timers()
2322 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); in ath9k_hw_set_sta_beacon_timers()
2323 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); in ath9k_hw_set_sta_beacon_timers()
2324 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); in ath9k_hw_set_sta_beacon_timers()
2326 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_sta_beacon_timers()
2328 REG_RMW_FIELD(ah, AR_RSSI_THR, in ath9k_hw_set_sta_beacon_timers()
2329 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); in ath9k_hw_set_sta_beacon_timers()
2331 beaconintval = bs->bs_intval; in ath9k_hw_set_sta_beacon_timers()
2333 if (bs->bs_sleepduration > beaconintval) in ath9k_hw_set_sta_beacon_timers()
2334 beaconintval = bs->bs_sleepduration; in ath9k_hw_set_sta_beacon_timers()
2336 dtimperiod = bs->bs_dtimperiod; in ath9k_hw_set_sta_beacon_timers()
2337 if (bs->bs_sleepduration > dtimperiod) in ath9k_hw_set_sta_beacon_timers()
2338 dtimperiod = bs->bs_sleepduration; in ath9k_hw_set_sta_beacon_timers()
2341 nextTbtt = bs->bs_nextdtim; in ath9k_hw_set_sta_beacon_timers()
2343 nextTbtt = bs->bs_nexttbtt; in ath9k_hw_set_sta_beacon_timers()
2345 ath_dbg(common, BEACON, "next DTIM %u\n", bs->bs_nextdtim); in ath9k_hw_set_sta_beacon_timers()
2350 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_sta_beacon_timers()
2352 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); in ath9k_hw_set_sta_beacon_timers()
2353 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); in ath9k_hw_set_sta_beacon_timers()
2355 REG_WRITE(ah, AR_SLEEP1, in ath9k_hw_set_sta_beacon_timers()
2359 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) in ath9k_hw_set_sta_beacon_timers()
2364 REG_WRITE(ah, AR_SLEEP2, in ath9k_hw_set_sta_beacon_timers()
2367 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); in ath9k_hw_set_sta_beacon_timers()
2368 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); in ath9k_hw_set_sta_beacon_timers()
2370 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_sta_beacon_timers()
2372 REG_SET_BIT(ah, AR_TIMER_MODE, in ath9k_hw_set_sta_beacon_timers()
2377 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); in ath9k_hw_set_sta_beacon_timers()
2395 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2396 * @ah: the atheros hardware data structure
2407 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) in ath9k_hw_dfs_tested() argument
2410 switch (ah->hw_version.macVersion) { in ath9k_hw_dfs_tested()
2421 static void ath9k_gpio_cap_init(struct ath_hw *ah) in ath9k_gpio_cap_init() argument
2423 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_gpio_cap_init()
2425 if (AR_SREV_9271(ah)) { in ath9k_gpio_cap_init()
2426 pCap->num_gpio_pins = AR9271_NUM_GPIO; in ath9k_gpio_cap_init()
2427 pCap->gpio_mask = AR9271_GPIO_MASK; in ath9k_gpio_cap_init()
2428 } else if (AR_DEVID_7010(ah)) { in ath9k_gpio_cap_init()
2429 pCap->num_gpio_pins = AR7010_NUM_GPIO; in ath9k_gpio_cap_init()
2430 pCap->gpio_mask = AR7010_GPIO_MASK; in ath9k_gpio_cap_init()
2431 } else if (AR_SREV_9287(ah)) { in ath9k_gpio_cap_init()
2432 pCap->num_gpio_pins = AR9287_NUM_GPIO; in ath9k_gpio_cap_init()
2433 pCap->gpio_mask = AR9287_GPIO_MASK; in ath9k_gpio_cap_init()
2434 } else if (AR_SREV_9285(ah)) { in ath9k_gpio_cap_init()
2435 pCap->num_gpio_pins = AR9285_NUM_GPIO; in ath9k_gpio_cap_init()
2436 pCap->gpio_mask = AR9285_GPIO_MASK; in ath9k_gpio_cap_init()
2437 } else if (AR_SREV_9280(ah)) { in ath9k_gpio_cap_init()
2438 pCap->num_gpio_pins = AR9280_NUM_GPIO; in ath9k_gpio_cap_init()
2439 pCap->gpio_mask = AR9280_GPIO_MASK; in ath9k_gpio_cap_init()
2440 } else if (AR_SREV_9300(ah)) { in ath9k_gpio_cap_init()
2441 pCap->num_gpio_pins = AR9300_NUM_GPIO; in ath9k_gpio_cap_init()
2442 pCap->gpio_mask = AR9300_GPIO_MASK; in ath9k_gpio_cap_init()
2443 } else if (AR_SREV_9330(ah)) { in ath9k_gpio_cap_init()
2444 pCap->num_gpio_pins = AR9330_NUM_GPIO; in ath9k_gpio_cap_init()
2445 pCap->gpio_mask = AR9330_GPIO_MASK; in ath9k_gpio_cap_init()
2446 } else if (AR_SREV_9340(ah)) { in ath9k_gpio_cap_init()
2447 pCap->num_gpio_pins = AR9340_NUM_GPIO; in ath9k_gpio_cap_init()
2448 pCap->gpio_mask = AR9340_GPIO_MASK; in ath9k_gpio_cap_init()
2449 } else if (AR_SREV_9462(ah)) { in ath9k_gpio_cap_init()
2450 pCap->num_gpio_pins = AR9462_NUM_GPIO; in ath9k_gpio_cap_init()
2451 pCap->gpio_mask = AR9462_GPIO_MASK; in ath9k_gpio_cap_init()
2452 } else if (AR_SREV_9485(ah)) { in ath9k_gpio_cap_init()
2453 pCap->num_gpio_pins = AR9485_NUM_GPIO; in ath9k_gpio_cap_init()
2454 pCap->gpio_mask = AR9485_GPIO_MASK; in ath9k_gpio_cap_init()
2455 } else if (AR_SREV_9531(ah)) { in ath9k_gpio_cap_init()
2456 pCap->num_gpio_pins = AR9531_NUM_GPIO; in ath9k_gpio_cap_init()
2457 pCap->gpio_mask = AR9531_GPIO_MASK; in ath9k_gpio_cap_init()
2458 } else if (AR_SREV_9550(ah)) { in ath9k_gpio_cap_init()
2459 pCap->num_gpio_pins = AR9550_NUM_GPIO; in ath9k_gpio_cap_init()
2460 pCap->gpio_mask = AR9550_GPIO_MASK; in ath9k_gpio_cap_init()
2461 } else if (AR_SREV_9561(ah)) { in ath9k_gpio_cap_init()
2462 pCap->num_gpio_pins = AR9561_NUM_GPIO; in ath9k_gpio_cap_init()
2463 pCap->gpio_mask = AR9561_GPIO_MASK; in ath9k_gpio_cap_init()
2464 } else if (AR_SREV_9565(ah)) { in ath9k_gpio_cap_init()
2465 pCap->num_gpio_pins = AR9565_NUM_GPIO; in ath9k_gpio_cap_init()
2466 pCap->gpio_mask = AR9565_GPIO_MASK; in ath9k_gpio_cap_init()
2467 } else if (AR_SREV_9580(ah)) { in ath9k_gpio_cap_init()
2468 pCap->num_gpio_pins = AR9580_NUM_GPIO; in ath9k_gpio_cap_init()
2469 pCap->gpio_mask = AR9580_GPIO_MASK; in ath9k_gpio_cap_init()
2471 pCap->num_gpio_pins = AR_NUM_GPIO; in ath9k_gpio_cap_init()
2472 pCap->gpio_mask = AR_GPIO_MASK; in ath9k_gpio_cap_init()
2476 int ath9k_hw_fill_cap_info(struct ath_hw *ah) in ath9k_hw_fill_cap_info() argument
2478 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_fill_cap_info()
2479 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); in ath9k_hw_fill_cap_info()
2480 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_fill_cap_info()
2485 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); in ath9k_hw_fill_cap_info()
2486 regulatory->current_rd = eeval; in ath9k_hw_fill_cap_info()
2488 if (ah->opmode != NL80211_IFTYPE_AP && in ath9k_hw_fill_cap_info()
2489 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { in ath9k_hw_fill_cap_info()
2490 if (regulatory->current_rd == 0x64 || in ath9k_hw_fill_cap_info()
2491 regulatory->current_rd == 0x65) in ath9k_hw_fill_cap_info()
2492 regulatory->current_rd += 5; in ath9k_hw_fill_cap_info()
2493 else if (regulatory->current_rd == 0x41) in ath9k_hw_fill_cap_info()
2494 regulatory->current_rd = 0x43; in ath9k_hw_fill_cap_info()
2496 regulatory->current_rd); in ath9k_hw_fill_cap_info()
2499 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); in ath9k_hw_fill_cap_info()
2502 if (ah->disable_5ghz) in ath9k_hw_fill_cap_info()
2503 ath_warn(common, "disabling 5GHz band\n"); in ath9k_hw_fill_cap_info()
2505 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; in ath9k_hw_fill_cap_info()
2509 if (ah->disable_2ghz) in ath9k_hw_fill_cap_info()
2512 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; in ath9k_hw_fill_cap_info()
2515 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) { in ath9k_hw_fill_cap_info()
2517 return -EINVAL; in ath9k_hw_fill_cap_info()
2520 ath9k_gpio_cap_init(ah); in ath9k_hw_fill_cap_info()
2522 if (AR_SREV_9485(ah) || in ath9k_hw_fill_cap_info()
2523 AR_SREV_9285(ah) || in ath9k_hw_fill_cap_info()
2524 AR_SREV_9330(ah) || in ath9k_hw_fill_cap_info()
2525 AR_SREV_9565(ah)) in ath9k_hw_fill_cap_info()
2526 pCap->chip_chainmask = 1; in ath9k_hw_fill_cap_info()
2527 else if (!AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2528 pCap->chip_chainmask = 7; in ath9k_hw_fill_cap_info()
2529 else if (!AR_SREV_9300_20_OR_LATER(ah) || in ath9k_hw_fill_cap_info()
2530 AR_SREV_9340(ah) || in ath9k_hw_fill_cap_info()
2531 AR_SREV_9462(ah) || in ath9k_hw_fill_cap_info()
2532 AR_SREV_9531(ah)) in ath9k_hw_fill_cap_info()
2533 pCap->chip_chainmask = 3; in ath9k_hw_fill_cap_info()
2535 pCap->chip_chainmask = 7; in ath9k_hw_fill_cap_info()
2537 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); in ath9k_hw_fill_cap_info()
2542 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && in ath9k_hw_fill_cap_info()
2544 !(AR_SREV_9271(ah))) in ath9k_hw_fill_cap_info()
2546 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; in ath9k_hw_fill_cap_info()
2547 else if (AR_SREV_9100(ah)) in ath9k_hw_fill_cap_info()
2548 pCap->rx_chainmask = 0x7; in ath9k_hw_fill_cap_info()
2551 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); in ath9k_hw_fill_cap_info()
2553 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask); in ath9k_hw_fill_cap_info()
2554 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask); in ath9k_hw_fill_cap_info()
2555 ah->txchainmask = pCap->tx_chainmask; in ath9k_hw_fill_cap_info()
2556 ah->rxchainmask = pCap->rx_chainmask; in ath9k_hw_fill_cap_info()
2558 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; in ath9k_hw_fill_cap_info()
2561 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2562 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; in ath9k_hw_fill_cap_info()
2564 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; in ath9k_hw_fill_cap_info()
2566 if (ah->hw_version.devid != AR2427_DEVID_PCIE) in ath9k_hw_fill_cap_info()
2567 pCap->hw_caps |= ATH9K_HW_CAP_HT; in ath9k_hw_fill_cap_info()
2569 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; in ath9k_hw_fill_cap_info()
2571 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) in ath9k_hw_fill_cap_info()
2572 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; in ath9k_hw_fill_cap_info()
2574 pCap->rts_aggr_limit = (8 * 1024); in ath9k_hw_fill_cap_info()
2577 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); in ath9k_hw_fill_cap_info()
2578 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { in ath9k_hw_fill_cap_info()
2579 ah->rfkill_gpio = in ath9k_hw_fill_cap_info()
2580 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); in ath9k_hw_fill_cap_info()
2581 ah->rfkill_polarity = in ath9k_hw_fill_cap_info()
2582 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); in ath9k_hw_fill_cap_info()
2584 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; in ath9k_hw_fill_cap_info()
2587 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2588 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; in ath9k_hw_fill_cap_info()
2590 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; in ath9k_hw_fill_cap_info()
2592 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) in ath9k_hw_fill_cap_info()
2593 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; in ath9k_hw_fill_cap_info()
2595 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; in ath9k_hw_fill_cap_info()
2597 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_fill_cap_info()
2598 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; in ath9k_hw_fill_cap_info()
2599 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && in ath9k_hw_fill_cap_info()
2600 !AR_SREV_9561(ah) && !AR_SREV_9565(ah)) in ath9k_hw_fill_cap_info()
2601 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; in ath9k_hw_fill_cap_info()
2603 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; in ath9k_hw_fill_cap_info()
2604 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; in ath9k_hw_fill_cap_info()
2605 pCap->rx_status_len = sizeof(struct ar9003_rxs); in ath9k_hw_fill_cap_info()
2606 pCap->tx_desc_len = sizeof(struct ar9003_txc); in ath9k_hw_fill_cap_info()
2607 pCap->txs_len = sizeof(struct ar9003_txs); in ath9k_hw_fill_cap_info()
2609 pCap->tx_desc_len = sizeof(struct ath_desc); in ath9k_hw_fill_cap_info()
2610 if (AR_SREV_9280_20(ah)) in ath9k_hw_fill_cap_info()
2611 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; in ath9k_hw_fill_cap_info()
2614 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2615 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; in ath9k_hw_fill_cap_info()
2617 if (AR_SREV_9561(ah)) in ath9k_hw_fill_cap_info()
2618 ah->ent_mode = 0x3BDA000; in ath9k_hw_fill_cap_info()
2619 else if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2620 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); in ath9k_hw_fill_cap_info()
2622 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) in ath9k_hw_fill_cap_info()
2623 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; in ath9k_hw_fill_cap_info()
2625 if (AR_SREV_9285(ah)) { in ath9k_hw_fill_cap_info()
2626 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { in ath9k_hw_fill_cap_info()
2628 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ath9k_hw_fill_cap_info()
2630 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; in ath9k_hw_fill_cap_info()
2636 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_fill_cap_info()
2637 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) in ath9k_hw_fill_cap_info()
2638 pCap->hw_caps |= ATH9K_HW_CAP_APM; in ath9k_hw_fill_cap_info()
2641 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { in ath9k_hw_fill_cap_info()
2642 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ath9k_hw_fill_cap_info()
2644 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; in ath9k_hw_fill_cap_info()
2649 if (ath9k_hw_dfs_tested(ah)) in ath9k_hw_fill_cap_info()
2650 pCap->hw_caps |= ATH9K_HW_CAP_DFS; in ath9k_hw_fill_cap_info()
2652 tx_chainmask = pCap->tx_chainmask; in ath9k_hw_fill_cap_info()
2653 rx_chainmask = pCap->rx_chainmask; in ath9k_hw_fill_cap_info()
2656 pCap->max_txchains++; in ath9k_hw_fill_cap_info()
2658 pCap->max_rxchains++; in ath9k_hw_fill_cap_info()
2664 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_fill_cap_info()
2665 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) in ath9k_hw_fill_cap_info()
2666 pCap->hw_caps |= ATH9K_HW_CAP_MCI; in ath9k_hw_fill_cap_info()
2668 if (AR_SREV_9462_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2669 pCap->hw_caps |= ATH9K_HW_CAP_RTT; in ath9k_hw_fill_cap_info()
2672 if (AR_SREV_9300_20_OR_LATER(ah) && in ath9k_hw_fill_cap_info()
2673 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) in ath9k_hw_fill_cap_info()
2674 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; in ath9k_hw_fill_cap_info()
2677 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2678 ah->wow.max_patterns = MAX_NUM_PATTERN; in ath9k_hw_fill_cap_info()
2680 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY; in ath9k_hw_fill_cap_info()
2690 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type) in ath9k_hw_gpio_cfg_output_mux() argument
2696 addr = AR_GPIO_OUTPUT_MUX3(ah); in ath9k_hw_gpio_cfg_output_mux()
2697 else if (gpio > 5) in ath9k_hw_gpio_cfg_output_mux()
2698 addr = AR_GPIO_OUTPUT_MUX2(ah); in ath9k_hw_gpio_cfg_output_mux()
2700 addr = AR_GPIO_OUTPUT_MUX1(ah); in ath9k_hw_gpio_cfg_output_mux()
2702 gpio_shift = (gpio % 6) * 5; in ath9k_hw_gpio_cfg_output_mux()
2704 if (AR_SREV_9280_20_OR_LATER(ah) || in ath9k_hw_gpio_cfg_output_mux()
2705 (addr != AR_GPIO_OUTPUT_MUX1(ah))) { in ath9k_hw_gpio_cfg_output_mux()
2706 REG_RMW(ah, addr, (type << gpio_shift), in ath9k_hw_gpio_cfg_output_mux()
2709 tmp = REG_READ(ah, addr); in ath9k_hw_gpio_cfg_output_mux()
2713 REG_WRITE(ah, addr, tmp); in ath9k_hw_gpio_cfg_output_mux()
2719 static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out, in ath9k_hw_gpio_cfg_soc() argument
2724 if (ah->caps.gpio_requested & BIT(gpio)) in ath9k_hw_gpio_cfg_soc()
2727 err = devm_gpio_request_one(ah->dev, gpio, out ? GPIOF_OUT_INIT_LOW : GPIOF_IN, label); in ath9k_hw_gpio_cfg_soc()
2729 ath_err(ath9k_hw_common(ah), "request GPIO%d failed:%d\n", in ath9k_hw_gpio_cfg_soc()
2734 ah->caps.gpio_requested |= BIT(gpio); in ath9k_hw_gpio_cfg_soc()
2737 static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out, in ath9k_hw_gpio_cfg_wmac() argument
2742 if (AR_DEVID_7010(ah)) { in ath9k_hw_gpio_cfg_wmac()
2745 REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift, in ath9k_hw_gpio_cfg_wmac()
2747 } else if (AR_SREV_SOC(ah)) { in ath9k_hw_gpio_cfg_wmac()
2749 REG_RMW(ah, AR_GPIO_OE_OUT(ah), gpio_set << gpio_shift, in ath9k_hw_gpio_cfg_wmac()
2755 REG_RMW(ah, AR_GPIO_OE_OUT(ah), gpio_set << gpio_shift, in ath9k_hw_gpio_cfg_wmac()
2759 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); in ath9k_hw_gpio_cfg_wmac()
2763 static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out, in ath9k_hw_gpio_request() argument
2766 WARN_ON(gpio >= ah->caps.num_gpio_pins); in ath9k_hw_gpio_request()
2768 if (BIT(gpio) & ah->caps.gpio_mask) in ath9k_hw_gpio_request()
2769 ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type); in ath9k_hw_gpio_request()
2770 else if (AR_SREV_SOC(ah)) in ath9k_hw_gpio_request()
2771 ath9k_hw_gpio_cfg_soc(ah, gpio, out, label); in ath9k_hw_gpio_request()
2776 void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label) in ath9k_hw_gpio_request_in() argument
2778 ath9k_hw_gpio_request(ah, gpio, false, label, 0); in ath9k_hw_gpio_request_in()
2782 void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label, in ath9k_hw_gpio_request_out() argument
2785 ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type); in ath9k_hw_gpio_request_out()
2789 void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio) in ath9k_hw_gpio_free() argument
2791 if (!AR_SREV_SOC(ah)) in ath9k_hw_gpio_free()
2794 WARN_ON(gpio >= ah->caps.num_gpio_pins); in ath9k_hw_gpio_free()
2796 if (ah->caps.gpio_requested & BIT(gpio)) in ath9k_hw_gpio_free()
2797 ah->caps.gpio_requested &= ~BIT(gpio); in ath9k_hw_gpio_free()
2801 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) in ath9k_hw_gpio_get() argument
2806 (MS(REG_READ(ah, AR_GPIO_IN_OUT(ah)), x##_GPIO_IN_VAL) & BIT(y)) in ath9k_hw_gpio_get()
2808 WARN_ON(gpio >= ah->caps.num_gpio_pins); in ath9k_hw_gpio_get()
2810 if (BIT(gpio) & ah->caps.gpio_mask) { in ath9k_hw_gpio_get()
2811 if (AR_SREV_9271(ah)) in ath9k_hw_gpio_get()
2813 else if (AR_SREV_9287(ah)) in ath9k_hw_gpio_get()
2815 else if (AR_SREV_9285(ah)) in ath9k_hw_gpio_get()
2817 else if (AR_SREV_9280(ah)) in ath9k_hw_gpio_get()
2819 else if (AR_DEVID_7010(ah)) in ath9k_hw_gpio_get()
2820 val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio); in ath9k_hw_gpio_get()
2821 else if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_gpio_get()
2822 val = REG_READ(ah, AR_GPIO_IN(ah)) & BIT(gpio); in ath9k_hw_gpio_get()
2825 } else if (BIT(gpio) & ah->caps.gpio_requested) { in ath9k_hw_gpio_get()
2835 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) in ath9k_hw_set_gpio() argument
2837 WARN_ON(gpio >= ah->caps.num_gpio_pins); in ath9k_hw_set_gpio()
2839 if (AR_DEVID_7010(ah) || AR_SREV_9271(ah)) in ath9k_hw_set_gpio()
2844 if (BIT(gpio) & ah->caps.gpio_mask) { in ath9k_hw_set_gpio()
2845 u32 out_addr = AR_DEVID_7010(ah) ? in ath9k_hw_set_gpio()
2846 AR7010_GPIO_OUT : AR_GPIO_IN_OUT(ah); in ath9k_hw_set_gpio()
2848 REG_RMW(ah, out_addr, val << gpio, BIT(gpio)); in ath9k_hw_set_gpio()
2849 } else if (BIT(gpio) & ah->caps.gpio_requested) { in ath9k_hw_set_gpio()
2857 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) in ath9k_hw_setantenna() argument
2859 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); in ath9k_hw_setantenna()
2867 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) in ath9k_hw_getrxfilter() argument
2869 u32 bits = REG_READ(ah, AR_RX_FILTER); in ath9k_hw_getrxfilter()
2870 u32 phybits = REG_READ(ah, AR_PHY_ERR); in ath9k_hw_getrxfilter()
2881 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) in ath9k_hw_setrxfilter() argument
2885 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_setrxfilter()
2887 REG_WRITE(ah, AR_RX_FILTER, bits); in ath9k_hw_setrxfilter()
2894 REG_WRITE(ah, AR_PHY_ERR, phybits); in ath9k_hw_setrxfilter()
2897 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); in ath9k_hw_setrxfilter()
2899 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); in ath9k_hw_setrxfilter()
2901 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_setrxfilter()
2905 bool ath9k_hw_phy_disable(struct ath_hw *ah) in ath9k_hw_phy_disable() argument
2907 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_phy_disable()
2908 ar9003_mci_bt_gain_ctrl(ah); in ath9k_hw_phy_disable()
2910 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) in ath9k_hw_phy_disable()
2913 ath9k_hw_init_pll(ah, NULL); in ath9k_hw_phy_disable()
2914 ah->htc_reset_init = true; in ath9k_hw_phy_disable()
2919 bool ath9k_hw_disable(struct ath_hw *ah) in ath9k_hw_disable() argument
2921 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_disable()
2924 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) in ath9k_hw_disable()
2927 ath9k_hw_init_pll(ah, NULL); in ath9k_hw_disable()
2932 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) in get_antenna_gain() argument
2941 return ah->eep_ops->get_eeprom(ah, gain_param); in get_antenna_gain()
2944 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, in ath9k_hw_apply_txpower() argument
2947 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); in ath9k_hw_apply_txpower() local
2956 ctl = ath9k_regd_get_ctl(reg, chan); in ath9k_hw_apply_txpower()
2958 channel = chan->chan; in ath9k_hw_apply_txpower()
2959 chan_pwr = min_t(int, channel->max_power * 2, MAX_COMBINED_POWER); in ath9k_hw_apply_txpower()
2960 new_pwr = min_t(int, chan_pwr, reg->power_limit); in ath9k_hw_apply_txpower()
2962 ah->eep_ops->set_txpower(ah, chan, ctl, in ath9k_hw_apply_txpower()
2963 get_antenna_gain(ah, chan), new_pwr, test); in ath9k_hw_apply_txpower()
2966 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) in ath9k_hw_set_txpowerlimit() argument
2968 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); in ath9k_hw_set_txpowerlimit() local
2969 struct ath9k_channel *chan = ah->curchan; in ath9k_hw_set_txpowerlimit()
2970 struct ieee80211_channel *channel = chan->chan; in ath9k_hw_set_txpowerlimit()
2972 reg->power_limit = min_t(u32, limit, MAX_COMBINED_POWER); in ath9k_hw_set_txpowerlimit()
2974 channel->max_power = MAX_COMBINED_POWER / 2; in ath9k_hw_set_txpowerlimit()
2976 ath9k_hw_apply_txpower(ah, chan, test); in ath9k_hw_set_txpowerlimit()
2979 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); in ath9k_hw_set_txpowerlimit()
2983 void ath9k_hw_setopmode(struct ath_hw *ah) in ath9k_hw_setopmode() argument
2985 ath9k_hw_set_operating_mode(ah, ah->opmode); in ath9k_hw_setopmode()
2989 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) in ath9k_hw_setmcastfilter() argument
2991 REG_WRITE(ah, AR_MCAST_FIL0, filter0); in ath9k_hw_setmcastfilter()
2992 REG_WRITE(ah, AR_MCAST_FIL1, filter1); in ath9k_hw_setmcastfilter()
2996 void ath9k_hw_write_associd(struct ath_hw *ah) in ath9k_hw_write_associd() argument
2998 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_write_associd()
3000 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); in ath9k_hw_write_associd()
3001 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | in ath9k_hw_write_associd()
3002 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); in ath9k_hw_write_associd()
3008 u64 ath9k_hw_gettsf64(struct ath_hw *ah) in ath9k_hw_gettsf64() argument
3013 tsf_upper1 = REG_READ(ah, AR_TSF_U32); in ath9k_hw_gettsf64()
3015 tsf_lower = REG_READ(ah, AR_TSF_L32); in ath9k_hw_gettsf64()
3016 tsf_upper2 = REG_READ(ah, AR_TSF_U32); in ath9k_hw_gettsf64()
3028 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) in ath9k_hw_settsf64() argument
3030 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); in ath9k_hw_settsf64()
3031 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); in ath9k_hw_settsf64()
3035 void ath9k_hw_reset_tsf(struct ath_hw *ah) in ath9k_hw_reset_tsf() argument
3037 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, in ath9k_hw_reset_tsf()
3039 ath_dbg(ath9k_hw_common(ah), RESET, in ath9k_hw_reset_tsf()
3042 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); in ath9k_hw_reset_tsf()
3046 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) in ath9k_hw_set_tsfadjust() argument
3049 ah->misc_mode |= AR_PCU_TX_ADD_TSF; in ath9k_hw_set_tsfadjust()
3051 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; in ath9k_hw_set_tsfadjust()
3055 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) in ath9k_hw_set11nmac2040() argument
3059 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) in ath9k_hw_set11nmac2040()
3064 REG_WRITE(ah, AR_2040_MODE, macmode); in ath9k_hw_set11nmac2040()
3088 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3098 u32 ath9k_hw_gettsf32(struct ath_hw *ah) in ath9k_hw_gettsf32() argument
3100 return REG_READ(ah, AR_TSF_L32); in ath9k_hw_gettsf32()
3104 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah) in ath9k_hw_gen_timer_start_tsf2() argument
3106 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_start_tsf2()
3108 if (timer_table->tsf2_enabled) { in ath9k_hw_gen_timer_start_tsf2()
3109 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN); in ath9k_hw_gen_timer_start_tsf2()
3110 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE); in ath9k_hw_gen_timer_start_tsf2()
3114 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, in ath_gen_timer_alloc() argument
3120 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_alloc()
3128 !AR_SREV_9300_20_OR_LATER(ah)) in ath_gen_timer_alloc()
3136 timer_table->timers[timer_index] = timer; in ath_gen_timer_alloc()
3137 timer->index = timer_index; in ath_gen_timer_alloc()
3138 timer->trigger = trigger; in ath_gen_timer_alloc()
3139 timer->overflow = overflow; in ath_gen_timer_alloc()
3140 timer->arg = arg; in ath_gen_timer_alloc()
3142 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) { in ath_gen_timer_alloc()
3143 timer_table->tsf2_enabled = true; in ath_gen_timer_alloc()
3144 ath9k_hw_gen_timer_start_tsf2(ah); in ath_gen_timer_alloc()
3151 void ath9k_hw_gen_timer_start(struct ath_hw *ah, in ath9k_hw_gen_timer_start() argument
3156 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_start()
3159 timer_table->timer_mask |= BIT(timer->index); in ath9k_hw_gen_timer_start()
3164 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, in ath9k_hw_gen_timer_start()
3166 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, in ath9k_hw_gen_timer_start()
3168 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, in ath9k_hw_gen_timer_start()
3169 gen_tmr_configuration[timer->index].mode_mask); in ath9k_hw_gen_timer_start()
3171 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_gen_timer_start()
3174 * to use. But we still follow the old rule, 0 - 7 use tsf and in ath9k_hw_gen_timer_start()
3175 * 8 - 15 use tsf2. in ath9k_hw_gen_timer_start()
3177 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) in ath9k_hw_gen_timer_start()
3178 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_start()
3179 (1 << timer->index)); in ath9k_hw_gen_timer_start()
3181 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_start()
3182 (1 << timer->index)); in ath9k_hw_gen_timer_start()
3185 if (timer->trigger) in ath9k_hw_gen_timer_start()
3186 mask |= SM(AR_GENTMR_BIT(timer->index), in ath9k_hw_gen_timer_start()
3188 if (timer->overflow) in ath9k_hw_gen_timer_start()
3189 mask |= SM(AR_GENTMR_BIT(timer->index), in ath9k_hw_gen_timer_start()
3192 REG_SET_BIT(ah, AR_IMR_S5, mask); in ath9k_hw_gen_timer_start()
3194 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { in ath9k_hw_gen_timer_start()
3195 ah->imask |= ATH9K_INT_GENTIMER; in ath9k_hw_gen_timer_start()
3196 ath9k_hw_set_interrupts(ah); in ath9k_hw_gen_timer_start()
3201 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) in ath9k_hw_gen_timer_stop() argument
3203 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_stop()
3206 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, in ath9k_hw_gen_timer_stop()
3207 gen_tmr_configuration[timer->index].mode_mask); in ath9k_hw_gen_timer_stop()
3209 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_gen_timer_stop()
3213 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { in ath9k_hw_gen_timer_stop()
3214 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_stop()
3215 (1 << timer->index)); in ath9k_hw_gen_timer_stop()
3220 REG_CLR_BIT(ah, AR_IMR_S5, in ath9k_hw_gen_timer_stop()
3221 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | in ath9k_hw_gen_timer_stop()
3222 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); in ath9k_hw_gen_timer_stop()
3224 timer_table->timer_mask &= ~BIT(timer->index); in ath9k_hw_gen_timer_stop()
3226 if (timer_table->timer_mask == 0) { in ath9k_hw_gen_timer_stop()
3227 ah->imask &= ~ATH9K_INT_GENTIMER; in ath9k_hw_gen_timer_stop()
3228 ath9k_hw_set_interrupts(ah); in ath9k_hw_gen_timer_stop()
3233 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) in ath_gen_timer_free() argument
3235 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_free()
3238 timer_table->timers[timer->index] = NULL; in ath_gen_timer_free()
3246 void ath_gen_timer_isr(struct ath_hw *ah) in ath_gen_timer_isr() argument
3248 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_isr()
3254 trigger_mask = ah->intr_gen_timer_trigger; in ath_gen_timer_isr()
3255 thresh_mask = ah->intr_gen_timer_thresh; in ath_gen_timer_isr()
3256 trigger_mask &= timer_table->timer_mask; in ath_gen_timer_isr()
3257 thresh_mask &= timer_table->timer_mask; in ath_gen_timer_isr()
3259 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) { in ath_gen_timer_isr()
3260 timer = timer_table->timers[index]; in ath_gen_timer_isr()
3263 if (!timer->overflow) in ath_gen_timer_isr()
3267 timer->overflow(timer->arg); in ath_gen_timer_isr()
3270 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) { in ath_gen_timer_isr()
3271 timer = timer_table->timers[index]; in ath_gen_timer_isr()
3274 if (!timer->trigger) in ath_gen_timer_isr()
3276 timer->trigger(timer->arg); in ath_gen_timer_isr()
3294 /* Single-chip solutions */
3355 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) in ath9k_hw_name() argument
3359 /* chipsets >= AR9280 are single-chip */ in ath9k_hw_name()
3360 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_name()
3363 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), in ath9k_hw_name()
3364 ah->hw_version.macRev); in ath9k_hw_name()
3369 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), in ath9k_hw_name()
3370 ah->hw_version.macRev, in ath9k_hw_name()
3371 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev in ath9k_hw_name()
3373 ah->hw_version.phyRev); in ath9k_hw_name()