Lines Matching +full:reg +full:- +full:5 +full:ah
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
20 #define AR_EEPROM_MODAL_SPURS 5
80 #define CTL_2GHT20 5
109 #define FREQ2FBIN(x, y) (u8)((y) ? ((x) - 2300) : (((x) - 4800) / 5))
110 #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
111 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
114 _ah->eep_ops->get_eeprom(_ah, EEP_OL_PWRCTRL))
116 _ah->eep_ops->get_eeprom(_ah, EEP_OL_PWRCTRL))
122 #define EEP_RFSILENT_GPIO_SEL ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00fc : 0x001c)
159 #define AR5416_PD_GAIN_ICEPTS 5
165 #define AR5416_PWR_TABLE_OFFSET_DB -5
214 #define AR9287_PWR_TABLE_OFFSET_DB -5
226 #define LNA_CTL_LOCAL_BIAS BIT(5)
382 u8 pwrPdg[2][5];
383 u8 vpdPdg[2][5];
384 u8 pcdac[2][5];
385 u8 empty[2][5];
537 u8 pwrPdg[2][5];
538 u8 vpdPdg[2][5];
539 u8 pcdac[2][5];
540 u8 empty[2][5];
667 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
668 u8 (*get_eepmisc)(struct ath_hw *ah);
671 void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val);
672 void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
679 bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data);
680 int ath9k_hw_nvram_swap_data(struct ath_hw *ah, bool *swap_needed, int size);
681 bool ath9k_hw_nvram_validate_checksum(struct ath_hw *ah, int size);
682 bool ath9k_hw_nvram_check_version(struct ath_hw *ah, int version, int minrev);
683 void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
688 void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
694 void ath9k_hw_get_target_powers(struct ath_hw *ah,
702 u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit,
704 void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
705 int ath9k_hw_eeprom_init(struct ath_hw *ah);
707 void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
720 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); in ath9k_hw_fbin2freq()