Lines Matching +full:reg +full:- +full:5 +full:ah
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
18 #include "hw-ops.h"
72 /* Addr 5G 2G */
89 static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt) in ar5008_write_bank6() argument
91 struct ar5416IniArray *array = &ah->iniBank6; in ar5008_write_bank6()
92 u32 *data = ah->analogBank6Data; in ar5008_write_bank6()
95 ENABLE_REGWRITE_BUFFER(ah); in ar5008_write_bank6()
97 for (r = 0; r < array->ia_rows; r++) { in ar5008_write_bank6()
98 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); in ar5008_write_bank6()
102 REGWRITE_BUFFER_FLUSH(ah); in ar5008_write_bank6()
106 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
119 arrayEntry = (firstBit - 1) / 8; in ar5008_hw_phy_modify_rx_buffer()
120 bitPosition = (firstBit - 1) % 8; in ar5008_hw_phy_modify_rx_buffer()
125 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << in ar5008_hw_phy_modify_rx_buffer()
130 bitsLeft -= 8 - bitPosition; in ar5008_hw_phy_modify_rx_buffer()
131 tmp32 = tmp32 >> (8 - bitPosition); in ar5008_hw_phy_modify_rx_buffer()
164 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) in ar5008_hw_force_bias() argument
166 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_force_bias()
171 if (!AR_SREV_5416(ah) || synth_freq >= 3000) in ar5008_hw_force_bias()
174 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); in ar5008_hw_force_bias()
183 /* pre-reverse this field */ in ar5008_hw_force_bias()
190 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); in ar5008_hw_force_bias()
193 ar5008_write_bank6(ah, ®_writes); in ar5008_hw_force_bias()
197 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
201 * cache in ah->analogBank6Data.
203 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar5008_hw_set_channel() argument
205 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_set_channel()
213 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar5008_hw_set_channel()
219 if (((freq - 2192) % 5) == 0) { in ar5008_hw_set_channel()
220 channelSel = ((freq - 672) * 2 - 3040) / 10; in ar5008_hw_set_channel()
222 } else if (((freq - 2224) % 5) == 0) { in ar5008_hw_set_channel()
223 channelSel = ((freq - 704) * 2 - 3040) / 10; in ar5008_hw_set_channel()
227 return -EINVAL; in ar5008_hw_set_channel()
233 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar5008_hw_set_channel()
236 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
239 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
245 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8); in ar5008_hw_set_channel()
249 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8); in ar5008_hw_set_channel()
250 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) in ar5008_hw_set_channel()
254 } else if ((freq % 5) == 0) { in ar5008_hw_set_channel()
255 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); in ar5008_hw_set_channel()
259 return -EINVAL; in ar5008_hw_set_channel()
262 ar5008_hw_force_bias(ah, freq); in ar5008_hw_set_channel()
266 (1 << 5) | 0x1; in ar5008_hw_set_channel()
268 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
270 ah->curchan = chan; in ar5008_hw_set_channel()
275 void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah, in ar5008_hw_cmn_spur_mitigate() argument
295 cur_bin = -6000; in ar5008_hw_cmn_spur_mitigate()
297 lower = bin - 100; in ar5008_hw_cmn_spur_mitigate()
312 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ar5008_hw_cmn_spur_mitigate()
313 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ar5008_hw_cmn_spur_mitigate()
318 lower = bin - 120; in ar5008_hw_cmn_spur_mitigate()
323 volatile int tmp_v = abs(cur_vit_mask - bin); in ar5008_hw_cmn_spur_mitigate()
334 cur_vit_mask -= 100; in ar5008_hw_cmn_spur_mitigate()
345 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
346 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
356 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
357 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
367 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
368 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
372 | (mask_m[4] << 22) | (mask_m[5] << 20) in ar5008_hw_cmn_spur_mitigate()
378 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
379 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
386 | (mask_p[6] << 10) | (mask_p[5] << 8) in ar5008_hw_cmn_spur_mitigate()
389 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
390 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
400 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
401 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
411 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
412 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
422 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
423 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
427 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
429 * For non single-chip solutions. Converts to baseband spur frequency given the
432 static void ar5008_hw_spur_mitigate(struct ath_hw *ah, in ar5008_hw_spur_mitigate() argument
447 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); in ar5008_hw_spur_mitigate()
450 cur_bb_spur = cur_bb_spur - (chan->channel * 10); in ar5008_hw_spur_mitigate()
451 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { in ar5008_hw_spur_mitigate()
462 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar5008_hw_spur_mitigate()
468 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); in ar5008_hw_spur_mitigate()
475 REG_WRITE(ah, AR_PHY_SPUR_REG, new); in ar5008_hw_spur_mitigate()
486 REG_WRITE(ah, AR_PHY_TIMING11, new); in ar5008_hw_spur_mitigate()
488 ar5008_hw_cmn_spur_mitigate(ah, chan, bin); in ar5008_hw_spur_mitigate()
492 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
493 * @ah: atheros hardware structure
497 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah) in ar5008_hw_rf_alloc_ext_banks() argument
499 int size = ah->iniBank6.ia_rows * sizeof(u32); in ar5008_hw_rf_alloc_ext_banks()
501 if (AR_SREV_9280_20_OR_LATER(ah)) in ar5008_hw_rf_alloc_ext_banks()
504 ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL); in ar5008_hw_rf_alloc_ext_banks()
505 if (!ah->analogBank6Data) in ar5008_hw_rf_alloc_ext_banks()
506 return -ENOMEM; in ar5008_hw_rf_alloc_ext_banks()
513 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
514 * @ah: atheros hardware structure
522 * rf device. This is not required for single-chip devices.
524 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah, in ar5008_hw_set_rf_regs() argument
539 if (AR_SREV_9280_20_OR_LATER(ah)) in ar5008_hw_set_rf_regs()
543 eepMinorRev = ah->eep_ops->get_eeprom_rev(ah); in ar5008_hw_set_rf_regs()
545 for (i = 0; i < ah->iniBank6.ia_rows; i++) in ar5008_hw_set_rf_regs()
546 ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex); in ar5008_hw_set_rf_regs()
548 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */ in ar5008_hw_set_rf_regs()
551 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); in ar5008_hw_set_rf_regs()
552 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); in ar5008_hw_set_rf_regs()
553 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, in ar5008_hw_set_rf_regs()
555 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, in ar5008_hw_set_rf_regs()
558 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); in ar5008_hw_set_rf_regs()
559 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); in ar5008_hw_set_rf_regs()
560 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, in ar5008_hw_set_rf_regs()
562 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, in ar5008_hw_set_rf_regs()
572 ar5008_write_bank6(ah, ®Writes); in ar5008_hw_set_rf_regs()
578 static void ar5008_hw_init_bb(struct ath_hw *ah, in ar5008_hw_init_bb() argument
583 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_init_bb()
585 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar5008_hw_init_bb()
587 ath9k_hw_synth_delay(ah, chan, synthDelay); in ar5008_hw_init_bb()
590 static void ar5008_hw_init_chain_masks(struct ath_hw *ah) in ar5008_hw_init_chain_masks() argument
594 rx_chainmask = ah->rxchainmask; in ar5008_hw_init_chain_masks()
595 tx_chainmask = ah->txchainmask; in ar5008_hw_init_chain_masks()
600 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
604 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { in ar5008_hw_init_chain_masks()
605 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); in ar5008_hw_init_chain_masks()
606 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); in ar5008_hw_init_chain_masks()
613 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_init_chain_masks()
614 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); in ar5008_hw_init_chain_masks()
615 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); in ar5008_hw_init_chain_masks()
618 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_init_chain_masks()
622 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); in ar5008_hw_init_chain_masks()
624 REGWRITE_BUFFER_FLUSH(ah); in ar5008_hw_init_chain_masks()
627 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
630 if (AR_SREV_9100(ah)) in ar5008_hw_init_chain_masks()
631 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
632 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); in ar5008_hw_init_chain_masks()
635 static void ar5008_hw_override_ini(struct ath_hw *ah, in ar5008_hw_override_ini() argument
645 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar5008_hw_override_ini()
647 if (AR_SREV_9280_20_OR_LATER(ah)) { in ar5008_hw_override_ini()
655 val = REG_READ(ah, AR_PCU_MISC_MODE2) & in ar5008_hw_override_ini()
658 if (!AR_SREV_9271(ah)) in ar5008_hw_override_ini()
661 if (AR_SREV_9287_11_OR_LATER(ah)) in ar5008_hw_override_ini()
666 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); in ar5008_hw_override_ini()
669 if (AR_SREV_9280_20_OR_LATER(ah)) in ar5008_hw_override_ini()
675 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); in ar5008_hw_override_ini()
681 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { in ar5008_hw_override_ini()
682 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); in ar5008_hw_override_ini()
684 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); in ar5008_hw_override_ini()
688 static void ar5008_hw_set_channel_regs(struct ath_hw *ah, in ar5008_hw_set_channel_regs() argument
694 if (AR_SREV_9285_12_OR_LATER(ah)) in ar5008_hw_set_channel_regs()
695 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & in ar5008_hw_set_channel_regs()
708 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_set_channel_regs()
709 REG_WRITE(ah, AR_PHY_TURBO, phymode); in ar5008_hw_set_channel_regs()
713 ath9k_hw_set11nmac2040(ah, chan); in ar5008_hw_set_channel_regs()
715 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); in ar5008_hw_set_channel_regs()
716 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ar5008_hw_set_channel_regs()
718 REGWRITE_BUFFER_FLUSH(ah); in ar5008_hw_set_channel_regs()
722 static int ar5008_hw_process_ini(struct ath_hw *ah, in ar5008_hw_process_ini() argument
725 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_process_ini()
741 REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar5008_hw_process_ini()
744 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); in ar5008_hw_process_ini()
745 if (ah->eep_ops->set_addac) in ar5008_hw_process_ini()
746 ah->eep_ops->set_addac(ah, chan); in ar5008_hw_process_ini()
748 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); in ar5008_hw_process_ini()
749 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); in ar5008_hw_process_ini()
751 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_process_ini()
753 for (i = 0; i < ah->iniModes.ia_rows; i++) { in ar5008_hw_process_ini()
754 u32 reg = INI_RA(&ah->iniModes, i, 0); in ar5008_hw_process_ini() local
755 u32 val = INI_RA(&ah->iniModes, i, modesIndex); in ar5008_hw_process_ini()
757 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup) in ar5008_hw_process_ini()
760 REG_WRITE(ah, reg, val); in ar5008_hw_process_ini()
762 if (reg >= 0x7800 && reg < 0x78a0 in ar5008_hw_process_ini()
763 && ah->config.analog_shiftreg in ar5008_hw_process_ini()
764 && (common->bus_ops->ath_bus_type != ATH_USB)) { in ar5008_hw_process_ini()
771 REGWRITE_BUFFER_FLUSH(ah); in ar5008_hw_process_ini()
773 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) in ar5008_hw_process_ini()
774 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); in ar5008_hw_process_ini()
776 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || in ar5008_hw_process_ini()
777 AR_SREV_9287_11_OR_LATER(ah)) in ar5008_hw_process_ini()
778 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); in ar5008_hw_process_ini()
780 if (AR_SREV_9271_10(ah)) { in ar5008_hw_process_ini()
781 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); in ar5008_hw_process_ini()
782 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa); in ar5008_hw_process_ini()
785 ENABLE_REGWRITE_BUFFER(ah); in ar5008_hw_process_ini()
788 for (i = 0; i < ah->iniCommon.ia_rows; i++) { in ar5008_hw_process_ini()
789 u32 reg = INI_RA(&ah->iniCommon, i, 0); in ar5008_hw_process_ini() local
790 u32 val = INI_RA(&ah->iniCommon, i, 1); in ar5008_hw_process_ini()
792 REG_WRITE(ah, reg, val); in ar5008_hw_process_ini()
794 if (reg >= 0x7800 && reg < 0x78a0 in ar5008_hw_process_ini()
795 && ah->config.analog_shiftreg in ar5008_hw_process_ini()
796 && (common->bus_ops->ath_bus_type != ATH_USB)) { in ar5008_hw_process_ini()
803 REGWRITE_BUFFER_FLUSH(ah); in ar5008_hw_process_ini()
805 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); in ar5008_hw_process_ini()
807 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar5008_hw_process_ini()
808 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, in ar5008_hw_process_ini()
811 ar5008_hw_override_ini(ah, chan); in ar5008_hw_process_ini()
812 ar5008_hw_set_channel_regs(ah, chan); in ar5008_hw_process_ini()
813 ar5008_hw_init_chain_masks(ah); in ar5008_hw_process_ini()
814 ath9k_olc_init(ah); in ar5008_hw_process_ini()
815 ath9k_hw_apply_txpower(ah, chan, false); in ar5008_hw_process_ini()
818 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { in ar5008_hw_process_ini()
819 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n"); in ar5008_hw_process_ini()
820 return -EIO; in ar5008_hw_process_ini()
826 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) in ar5008_hw_set_rfmode() argument
838 if (!AR_SREV_9280_20_OR_LATER(ah)) in ar5008_hw_set_rfmode()
842 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar5008_hw_set_rfmode()
845 REG_WRITE(ah, AR_PHY_MODE, rfMode); in ar5008_hw_set_rfmode()
848 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah) in ar5008_hw_mark_phy_inactive() argument
850 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); in ar5008_hw_mark_phy_inactive()
853 static void ar5008_hw_set_delta_slope(struct ath_hw *ah, in ar5008_hw_set_delta_slope() argument
865 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar5008_hw_set_delta_slope()
868 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar5008_hw_set_delta_slope()
871 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar5008_hw_set_delta_slope()
873 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar5008_hw_set_delta_slope()
878 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar5008_hw_set_delta_slope()
881 REG_RMW_FIELD(ah, AR_PHY_HALFGI, in ar5008_hw_set_delta_slope()
883 REG_RMW_FIELD(ah, AR_PHY_HALFGI, in ar5008_hw_set_delta_slope()
887 static bool ar5008_hw_rfbus_req(struct ath_hw *ah) in ar5008_hw_rfbus_req() argument
889 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); in ar5008_hw_rfbus_req()
890 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, in ar5008_hw_rfbus_req()
894 static void ar5008_hw_rfbus_done(struct ath_hw *ah) in ar5008_hw_rfbus_done() argument
896 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_rfbus_done()
898 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); in ar5008_hw_rfbus_done()
900 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); in ar5008_hw_rfbus_done()
903 static void ar5008_restore_chainmask(struct ath_hw *ah) in ar5008_restore_chainmask() argument
905 int rx_chainmask = ah->rxchainmask; in ar5008_restore_chainmask()
908 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); in ar5008_restore_chainmask()
909 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); in ar5008_restore_chainmask()
913 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah, in ar9160_hw_compute_pll_control() argument
933 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah, in ar5008_hw_compute_pll_control() argument
953 static bool ar5008_hw_ani_control_new(struct ath_hw *ah, in ar5008_hw_ani_control_new() argument
957 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_ani_control_new()
958 struct ath9k_channel *chan = ah->curchan; in ar5008_hw_ani_control_new()
959 struct ar5416AniState *aniState = &ah->ani; in ar5008_hw_ani_control_new()
962 switch (cmd & ah->ani_function) { in ar5008_hw_ani_control_new()
977 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; in ar5008_hw_ani_control_new()
979 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; in ar5008_hw_ani_control_new()
981 aniState->iniDef.m1Thresh : m1Thresh_off; in ar5008_hw_ani_control_new()
983 aniState->iniDef.m2Thresh : m2Thresh_off; in ar5008_hw_ani_control_new()
985 aniState->iniDef.m2CountThr : m2CountThr_off; in ar5008_hw_ani_control_new()
987 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; in ar5008_hw_ani_control_new()
989 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; in ar5008_hw_ani_control_new()
991 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; in ar5008_hw_ani_control_new()
993 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; in ar5008_hw_ani_control_new()
995 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; in ar5008_hw_ani_control_new()
997 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1000 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1003 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar5008_hw_ani_control_new()
1005 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar5008_hw_ani_control_new()
1007 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar5008_hw_ani_control_new()
1009 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1013 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar5008_hw_ani_control_new()
1015 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar5008_hw_ani_control_new()
1017 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar5008_hw_ani_control_new()
1019 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar5008_hw_ani_control_new()
1023 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1026 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1029 if (on != aniState->ofdmWeakSigDetect) { in ar5008_hw_ani_control_new()
1032 chan->channel, in ar5008_hw_ani_control_new()
1033 aniState->ofdmWeakSigDetect ? in ar5008_hw_ani_control_new()
1037 ah->stats.ast_ani_ofdmon++; in ar5008_hw_ani_control_new()
1039 ah->stats.ast_ani_ofdmoff++; in ar5008_hw_ani_control_new()
1040 aniState->ofdmWeakSigDetect = on; in ar5008_hw_ani_control_new()
1048 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, in ar5008_hw_ani_control_new()
1050 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, in ar5008_hw_ani_control_new()
1053 if (level != aniState->firstepLevel) { in ar5008_hw_ani_control_new()
1056 chan->channel, in ar5008_hw_ani_control_new()
1057 aniState->firstepLevel, in ar5008_hw_ani_control_new()
1061 aniState->iniDef.firstep); in ar5008_hw_ani_control_new()
1064 chan->channel, in ar5008_hw_ani_control_new()
1065 aniState->firstepLevel, in ar5008_hw_ani_control_new()
1069 aniState->iniDef.firstepLow); in ar5008_hw_ani_control_new()
1070 if (level > aniState->firstepLevel) in ar5008_hw_ani_control_new()
1071 ah->stats.ast_ani_stepup++; in ar5008_hw_ani_control_new()
1072 else if (level < aniState->firstepLevel) in ar5008_hw_ani_control_new()
1073 ah->stats.ast_ani_stepdown++; in ar5008_hw_ani_control_new()
1074 aniState->firstepLevel = level; in ar5008_hw_ani_control_new()
1082 REG_RMW_FIELD(ah, AR_PHY_TIMING5, in ar5008_hw_ani_control_new()
1085 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, in ar5008_hw_ani_control_new()
1086 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value - 1); in ar5008_hw_ani_control_new()
1088 if (level != aniState->spurImmunityLevel) { in ar5008_hw_ani_control_new()
1091 chan->channel, in ar5008_hw_ani_control_new()
1092 aniState->spurImmunityLevel, in ar5008_hw_ani_control_new()
1096 aniState->iniDef.cycpwrThr1); in ar5008_hw_ani_control_new()
1099 chan->channel, in ar5008_hw_ani_control_new()
1100 aniState->spurImmunityLevel, in ar5008_hw_ani_control_new()
1104 aniState->iniDef.cycpwrThr1Ext); in ar5008_hw_ani_control_new()
1105 if (level > aniState->spurImmunityLevel) in ar5008_hw_ani_control_new()
1106 ah->stats.ast_ani_spurup++; in ar5008_hw_ani_control_new()
1107 else if (level < aniState->spurImmunityLevel) in ar5008_hw_ani_control_new()
1108 ah->stats.ast_ani_spurdown++; in ar5008_hw_ani_control_new()
1109 aniState->spurImmunityLevel = level; in ar5008_hw_ani_control_new()
1127 aniState->spurImmunityLevel, in ar5008_hw_ani_control_new()
1128 aniState->ofdmWeakSigDetect ? "on" : "off", in ar5008_hw_ani_control_new()
1129 aniState->firstepLevel, in ar5008_hw_ani_control_new()
1130 aniState->mrcCCK ? "on" : "off", in ar5008_hw_ani_control_new()
1131 aniState->listenTime, in ar5008_hw_ani_control_new()
1132 aniState->ofdmPhyErrCount, in ar5008_hw_ani_control_new()
1133 aniState->cckPhyErrCount); in ar5008_hw_ani_control_new()
1137 static void ar5008_hw_do_getnf(struct ath_hw *ah, in ar5008_hw_do_getnf() argument
1142 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); in ar5008_hw_do_getnf()
1145 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); in ar5008_hw_do_getnf()
1148 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); in ar5008_hw_do_getnf()
1151 if (!IS_CHAN_HT40(ah->curchan)) in ar5008_hw_do_getnf()
1154 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); in ar5008_hw_do_getnf()
1157 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); in ar5008_hw_do_getnf()
1160 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); in ar5008_hw_do_getnf()
1161 nfarray[5] = sign_extend32(nf, 8); in ar5008_hw_do_getnf()
1169 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) in ar5008_hw_ani_cache_ini_regs() argument
1171 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_ani_cache_ini_regs()
1172 struct ath9k_channel *chan = ah->curchan; in ar5008_hw_ani_cache_ini_regs()
1173 struct ar5416AniState *aniState = &ah->ani; in ar5008_hw_ani_cache_ini_regs()
1177 iniDef = &aniState->iniDef; in ar5008_hw_ani_cache_ini_regs()
1180 ah->hw_version.macVersion, in ar5008_hw_ani_cache_ini_regs()
1181 ah->hw_version.macRev, in ar5008_hw_ani_cache_ini_regs()
1182 ah->opmode, in ar5008_hw_ani_cache_ini_regs()
1183 chan->channel); in ar5008_hw_ani_cache_ini_regs()
1185 val = REG_READ(ah, AR_PHY_SFCORR); in ar5008_hw_ani_cache_ini_regs()
1186 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); in ar5008_hw_ani_cache_ini_regs()
1187 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); in ar5008_hw_ani_cache_ini_regs()
1188 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); in ar5008_hw_ani_cache_ini_regs()
1190 val = REG_READ(ah, AR_PHY_SFCORR_LOW); in ar5008_hw_ani_cache_ini_regs()
1191 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); in ar5008_hw_ani_cache_ini_regs()
1192 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); in ar5008_hw_ani_cache_ini_regs()
1193 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); in ar5008_hw_ani_cache_ini_regs()
1195 val = REG_READ(ah, AR_PHY_SFCORR_EXT); in ar5008_hw_ani_cache_ini_regs()
1196 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); in ar5008_hw_ani_cache_ini_regs()
1197 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); in ar5008_hw_ani_cache_ini_regs()
1198 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); in ar5008_hw_ani_cache_ini_regs()
1199 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); in ar5008_hw_ani_cache_ini_regs()
1200 iniDef->firstep = REG_READ_FIELD(ah, in ar5008_hw_ani_cache_ini_regs()
1203 iniDef->firstepLow = REG_READ_FIELD(ah, in ar5008_hw_ani_cache_ini_regs()
1206 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, in ar5008_hw_ani_cache_ini_regs()
1209 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, in ar5008_hw_ani_cache_ini_regs()
1214 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; in ar5008_hw_ani_cache_ini_regs()
1215 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; in ar5008_hw_ani_cache_ini_regs()
1216 aniState->ofdmWeakSigDetect = true; in ar5008_hw_ani_cache_ini_regs()
1217 aniState->mrcCCK = false; /* not available on pre AR9003 */ in ar5008_hw_ani_cache_ini_regs()
1220 static void ar5008_hw_set_nf_limits(struct ath_hw *ah) in ar5008_hw_set_nf_limits() argument
1222 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; in ar5008_hw_set_nf_limits()
1223 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; in ar5008_hw_set_nf_limits()
1224 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; in ar5008_hw_set_nf_limits()
1225 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; in ar5008_hw_set_nf_limits()
1226 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; in ar5008_hw_set_nf_limits()
1227 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; in ar5008_hw_set_nf_limits()
1230 static void ar5008_hw_set_radar_params(struct ath_hw *ah, in ar5008_hw_set_radar_params() argument
1236 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); in ar5008_hw_set_radar_params()
1241 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); in ar5008_hw_set_radar_params()
1242 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); in ar5008_hw_set_radar_params()
1243 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); in ar5008_hw_set_radar_params()
1244 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); in ar5008_hw_set_radar_params()
1245 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); in ar5008_hw_set_radar_params()
1247 radar_1 = REG_READ(ah, AR_PHY_RADAR_1); in ar5008_hw_set_radar_params()
1252 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); in ar5008_hw_set_radar_params()
1253 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); in ar5008_hw_set_radar_params()
1254 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); in ar5008_hw_set_radar_params()
1256 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); in ar5008_hw_set_radar_params()
1257 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); in ar5008_hw_set_radar_params()
1258 if (conf->ext_channel) in ar5008_hw_set_radar_params()
1259 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar5008_hw_set_radar_params()
1261 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar5008_hw_set_radar_params()
1264 static void ar5008_hw_set_radar_conf(struct ath_hw *ah) in ar5008_hw_set_radar_conf() argument
1266 struct ath_hw_radar_conf *conf = &ah->radar_conf; in ar5008_hw_set_radar_conf()
1268 conf->fir_power = -33; in ar5008_hw_set_radar_conf()
1269 conf->radar_rssi = 20; in ar5008_hw_set_radar_conf()
1270 conf->pulse_height = 10; in ar5008_hw_set_radar_conf()
1271 conf->pulse_rssi = 15; in ar5008_hw_set_radar_conf()
1272 conf->pulse_inband = 15; in ar5008_hw_set_radar_conf()
1273 conf->pulse_maxlen = 255; in ar5008_hw_set_radar_conf()
1274 conf->pulse_inband_step = 12; in ar5008_hw_set_radar_conf()
1275 conf->radar_inband = 8; in ar5008_hw_set_radar_conf()
1278 static void ar5008_hw_init_txpower_cck(struct ath_hw *ah, int16_t *rate_array) in ar5008_hw_init_txpower_cck() argument
1280 #define CCK_DELTA(_ah, x) ((OLC_FOR_AR9280_20_LATER(_ah)) ? max((x) - 2, 0) : (x)) in ar5008_hw_init_txpower_cck()
1281 ah->tx_power[0] = CCK_DELTA(ah, rate_array[rate1l]); in ar5008_hw_init_txpower_cck()
1282 ah->tx_power[1] = CCK_DELTA(ah, min(rate_array[rate2l], in ar5008_hw_init_txpower_cck()
1284 ah->tx_power[2] = CCK_DELTA(ah, min(rate_array[rate5_5l], in ar5008_hw_init_txpower_cck()
1286 ah->tx_power[3] = CCK_DELTA(ah, min(rate_array[rate11l], in ar5008_hw_init_txpower_cck()
1291 static void ar5008_hw_init_txpower_ofdm(struct ath_hw *ah, int16_t *rate_array, in ar5008_hw_init_txpower_ofdm() argument
1297 ah->tx_power[i] = rate_array[idx]; in ar5008_hw_init_txpower_ofdm()
1302 static void ar5008_hw_init_txpower_ht(struct ath_hw *ah, int16_t *rate_array, in ar5008_hw_init_txpower_ht() argument
1309 ah->tx_power[i] = rate_array[mcs_idx] + ht40_delta; in ar5008_hw_init_txpower_ht()
1312 memcpy(&ah->tx_power[ds_offset], &ah->tx_power[ss_offset], in ar5008_hw_init_txpower_ht()
1316 void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array, in ar5008_hw_init_rate_txpower() argument
1320 ar5008_hw_init_txpower_ofdm(ah, rate_array, in ar5008_hw_init_rate_txpower()
1323 ar5008_hw_init_txpower_ht(ah, rate_array, in ar5008_hw_init_rate_txpower()
1330 ar5008_hw_init_txpower_cck(ah, rate_array); in ar5008_hw_init_rate_txpower()
1331 ar5008_hw_init_txpower_ofdm(ah, rate_array, in ar5008_hw_init_rate_txpower()
1334 ar5008_hw_init_txpower_ht(ah, rate_array, in ar5008_hw_init_rate_txpower()
1343 int ar5008_hw_attach_phy_ops(struct ath_hw *ah) in ar5008_hw_attach_phy_ops() argument
1345 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar5008_hw_attach_phy_ops()
1356 ret = ar5008_hw_rf_alloc_ext_banks(ah); in ar5008_hw_attach_phy_ops()
1360 priv_ops->rf_set_freq = ar5008_hw_set_channel; in ar5008_hw_attach_phy_ops()
1361 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate; in ar5008_hw_attach_phy_ops()
1363 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs; in ar5008_hw_attach_phy_ops()
1364 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs; in ar5008_hw_attach_phy_ops()
1365 priv_ops->init_bb = ar5008_hw_init_bb; in ar5008_hw_attach_phy_ops()
1366 priv_ops->process_ini = ar5008_hw_process_ini; in ar5008_hw_attach_phy_ops()
1367 priv_ops->set_rfmode = ar5008_hw_set_rfmode; in ar5008_hw_attach_phy_ops()
1368 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive; in ar5008_hw_attach_phy_ops()
1369 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope; in ar5008_hw_attach_phy_ops()
1370 priv_ops->rfbus_req = ar5008_hw_rfbus_req; in ar5008_hw_attach_phy_ops()
1371 priv_ops->rfbus_done = ar5008_hw_rfbus_done; in ar5008_hw_attach_phy_ops()
1372 priv_ops->restore_chainmask = ar5008_restore_chainmask; in ar5008_hw_attach_phy_ops()
1373 priv_ops->do_getnf = ar5008_hw_do_getnf; in ar5008_hw_attach_phy_ops()
1374 priv_ops->set_radar_params = ar5008_hw_set_radar_params; in ar5008_hw_attach_phy_ops()
1376 priv_ops->ani_control = ar5008_hw_ani_control_new; in ar5008_hw_attach_phy_ops()
1377 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs; in ar5008_hw_attach_phy_ops()
1379 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) in ar5008_hw_attach_phy_ops()
1380 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control; in ar5008_hw_attach_phy_ops()
1382 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control; in ar5008_hw_attach_phy_ops()
1384 ar5008_hw_set_nf_limits(ah); in ar5008_hw_attach_phy_ops()
1385 ar5008_hw_set_radar_conf(ah); in ar5008_hw_attach_phy_ops()
1386 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs)); in ar5008_hw_attach_phy_ops()