Lines Matching +full:reg +full:- +full:5 +full:ah
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
5 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
33 #include "reg.h"
42 * Here we handle the low-level functions related to baseband
48 * - Channel setting/switching
50 * - Automatic Gain Control (AGC) calibration
52 * - Noise Floor calibration
54 * - I/Q imbalance calibration (QAM correction)
56 * - Calibration due to thermal changes (gain_F)
58 * - Spur noise mitigation
60 * - RF/PHY initialization for the various operating modes and bwmodes
62 * - Antenna control
64 * - TX power control per channel/rate/packet type
77 * ath5k_hw_radio_revision() - Get the PHY Chip revision
78 * @ah: The &struct ath5k_hw
81 * Returns the revision number of a 2GHz, 5GHz or single chip
85 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum nl80211_band band) in ath5k_hw_radio_revision() argument
96 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
99 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
108 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); in ath5k_hw_radio_revision()
111 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); in ath5k_hw_radio_revision()
113 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_radio_revision()
114 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(256)) >> 28) & 0xf; in ath5k_hw_radio_revision()
117 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; in ath5k_hw_radio_revision()
122 /* Reset to the 5GHz mode */ in ath5k_hw_radio_revision()
123 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
129 * ath5k_channel_ok() - Check if a channel is supported by the hw
130 * @ah: The &struct ath5k_hw
137 ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel) in ath5k_channel_ok() argument
139 u16 freq = channel->center_freq; in ath5k_channel_ok()
142 if (channel->band == NL80211_BAND_2GHZ) { in ath5k_channel_ok()
143 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && in ath5k_channel_ok()
144 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) in ath5k_channel_ok()
146 } else if (channel->band == NL80211_BAND_5GHZ) in ath5k_channel_ok()
147 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && in ath5k_channel_ok()
148 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) in ath5k_channel_ok()
155 * ath5k_hw_chan_has_spur_noise() - Check if channel is sensitive to spur noise
156 * @ah: The &struct ath5k_hw
160 ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, in ath5k_hw_chan_has_spur_noise() argument
165 if ((ah->ah_radio == AR5K_RF5112) || in ath5k_hw_chan_has_spur_noise()
166 (ah->ah_radio == AR5K_RF5413) || in ath5k_hw_chan_has_spur_noise()
167 (ah->ah_radio == AR5K_RF2413) || in ath5k_hw_chan_has_spur_noise()
168 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) in ath5k_hw_chan_has_spur_noise()
173 if ((channel->center_freq % refclk_freq != 0) && in ath5k_hw_chan_has_spur_noise()
174 ((channel->center_freq % refclk_freq < 10) || in ath5k_hw_chan_has_spur_noise()
175 (channel->center_freq % refclk_freq > 22))) in ath5k_hw_chan_has_spur_noise()
182 * ath5k_hw_rfb_op() - Perform an operation on the given RF Buffer
183 * @ah: The &struct ath5k_hw
194 ath5k_hw_rfb_op(struct ath5k_hw *ah, const struct ath5k_rf_reg *rf_regs, in ath5k_hw_rfb_op() argument
206 rfb = ah->ah_rf_banks; in ath5k_hw_rfb_op()
208 for (i = 0; i < ah->ah_rf_regs_count; i++) { in ath5k_hw_rfb_op()
221 bank = rfreg->bank; in ath5k_hw_rfb_op()
222 num_bits = rfreg->field.len; in ath5k_hw_rfb_op()
223 first_bit = rfreg->field.pos; in ath5k_hw_rfb_op()
224 col = rfreg->field.col; in ath5k_hw_rfb_op()
230 offset = ah->ah_offset[bank]; in ath5k_hw_rfb_op()
238 entry = ((first_bit - 1) / 8) + offset; in ath5k_hw_rfb_op()
239 position = (first_bit - 1) % 8; in ath5k_hw_rfb_op()
250 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << in ath5k_hw_rfb_op()
256 data >>= (8 - position); in ath5k_hw_rfb_op()
260 bits_shifted += last_bit - position; in ath5k_hw_rfb_op()
263 bits_left -= 8 - position; in ath5k_hw_rfb_op()
272 * ath5k_hw_write_ofdm_timings() - set OFDM timings on AR5212
273 * @ah: the &struct ath5k_hw
286 ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, in ath5k_hw_write_ofdm_timings() argument
293 BUG_ON(!(ah->ah_version == AR5K_AR5212) || in ath5k_hw_write_ofdm_timings()
294 (channel->hw_value == AR5K_MODE_11B)); in ath5k_hw_write_ofdm_timings()
297 * ALGO: coef = (5 * clock / carrier_freq) / 2 in ath5k_hw_write_ofdm_timings()
300 switch (ah->ah_bwmode) { in ath5k_hw_write_ofdm_timings()
314 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq; in ath5k_hw_write_ofdm_timings()
317 * ALGO: coef_exp = 14 - highest set bit position */ in ath5k_hw_write_ofdm_timings()
322 return -EINVAL; in ath5k_hw_write_ofdm_timings()
325 coef_exp = 14 - (coef_exp - 24); in ath5k_hw_write_ofdm_timings()
331 (1 << (24 - coef_exp - 1)); in ath5k_hw_write_ofdm_timings()
335 ds_coef_man = coef_man >> (24 - coef_exp); in ath5k_hw_write_ofdm_timings()
336 ds_coef_exp = coef_exp - 16; in ath5k_hw_write_ofdm_timings()
338 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, in ath5k_hw_write_ofdm_timings()
340 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, in ath5k_hw_write_ofdm_timings()
347 * ath5k_hw_phy_disable() - Disable PHY
348 * @ah: The &struct ath5k_hw
350 int ath5k_hw_phy_disable(struct ath5k_hw *ah) in ath5k_hw_phy_disable() argument
353 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); in ath5k_hw_phy_disable()
359 * ath5k_hw_wait_for_synth() - Wait for synth to settle
360 * @ah: The &struct ath5k_hw
364 ath5k_hw_wait_for_synth(struct ath5k_hw *ah, in ath5k_hw_wait_for_synth() argument
368 * On 5211+ read activation -> rx delay in ath5k_hw_wait_for_synth()
371 if (ah->ah_version != AR5K_AR5210) { in ath5k_hw_wait_for_synth()
373 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & in ath5k_hw_wait_for_synth()
375 delay = (channel->hw_value == AR5K_MODE_11B) ? in ath5k_hw_wait_for_synth()
377 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ) in ath5k_hw_wait_for_synth()
379 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ) in ath5k_hw_wait_for_synth()
401 * auto adjustment on hw -notice they have a much smaller BANK 7 and
402 * no gain optimization ladder-.
409 * "http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
413 * "http://madwifi-project.org/ticket/1659"
418 * ath5k_hw_rfgain_opt_init() - Initialize ah_gain during attach
419 * @ah: The &struct ath5k_hw
421 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) in ath5k_hw_rfgain_opt_init() argument
424 switch (ah->ah_radio) { in ath5k_hw_rfgain_opt_init()
426 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; in ath5k_hw_rfgain_opt_init()
427 ah->ah_gain.g_low = 20; in ath5k_hw_rfgain_opt_init()
428 ah->ah_gain.g_high = 35; in ath5k_hw_rfgain_opt_init()
429 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_rfgain_opt_init()
432 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; in ath5k_hw_rfgain_opt_init()
433 ah->ah_gain.g_low = 20; in ath5k_hw_rfgain_opt_init()
434 ah->ah_gain.g_high = 85; in ath5k_hw_rfgain_opt_init()
435 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_rfgain_opt_init()
438 return -EINVAL; in ath5k_hw_rfgain_opt_init()
445 * ath5k_hw_request_rfgain_probe() - Request a PAPD probe packet
446 * @ah: The &struct ath5k_hw
458 ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) in ath5k_hw_request_rfgain_probe() argument
463 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) in ath5k_hw_request_rfgain_probe()
468 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, in ath5k_hw_request_rfgain_probe()
472 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; in ath5k_hw_request_rfgain_probe()
477 * ath5k_hw_rf_gainf_corr() - Calculate Gain_F measurement correction
478 * @ah: The &struct ath5k_hw
484 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) in ath5k_hw_rf_gainf_corr() argument
492 if ((ah->ah_radio != AR5K_RF5112) || in ath5k_hw_rf_gainf_corr()
493 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) in ath5k_hw_rf_gainf_corr()
498 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); in ath5k_hw_rf_gainf_corr()
500 g_step = &go->go_step[ah->ah_gain.g_step_idx]; in ath5k_hw_rf_gainf_corr()
502 if (ah->ah_rf_banks == NULL) in ath5k_hw_rf_gainf_corr()
505 ah->ah_gain.g_f_corr = 0; in ath5k_hw_rf_gainf_corr()
508 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) in ath5k_hw_rf_gainf_corr()
512 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); in ath5k_hw_rf_gainf_corr()
515 mix = g_step->gos_param[0]; in ath5k_hw_rf_gainf_corr()
519 ah->ah_gain.g_f_corr = step * 2; in ath5k_hw_rf_gainf_corr()
522 ah->ah_gain.g_f_corr = (step - 5) * 2; in ath5k_hw_rf_gainf_corr()
525 ah->ah_gain.g_f_corr = step; in ath5k_hw_rf_gainf_corr()
528 ah->ah_gain.g_f_corr = 0; in ath5k_hw_rf_gainf_corr()
532 return ah->ah_gain.g_f_corr; in ath5k_hw_rf_gainf_corr()
536 * ath5k_hw_rf_check_gainf_readback() - Validate Gain_F feedback from detector
537 * @ah: The &struct ath5k_hw
547 ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) in ath5k_hw_rf_check_gainf_readback() argument
552 if (ah->ah_rf_banks == NULL) in ath5k_hw_rf_check_gainf_readback()
555 if (ah->ah_radio == AR5K_RF5111) { in ath5k_hw_rf_check_gainf_readback()
558 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); in ath5k_hw_rf_check_gainf_readback()
560 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, in ath5k_hw_rf_check_gainf_readback()
568 ah->ah_gain.g_high = level[3] - in ath5k_hw_rf_check_gainf_readback()
569 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); in ath5k_hw_rf_check_gainf_readback()
570 ah->ah_gain.g_low = level[0] + in ath5k_hw_rf_check_gainf_readback()
575 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); in ath5k_hw_rf_check_gainf_readback()
577 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, in ath5k_hw_rf_check_gainf_readback()
586 ah->ah_gain.g_high = 55; in ath5k_hw_rf_check_gainf_readback()
590 return (ah->ah_gain.g_current >= level[0] && in ath5k_hw_rf_check_gainf_readback()
591 ah->ah_gain.g_current <= level[1]) || in ath5k_hw_rf_check_gainf_readback()
592 (ah->ah_gain.g_current >= level[2] && in ath5k_hw_rf_check_gainf_readback()
593 ah->ah_gain.g_current <= level[3]); in ath5k_hw_rf_check_gainf_readback()
597 * ath5k_hw_rf_gainf_adjust() - Perform Gain_F adjustment
598 * @ah: The &struct ath5k_hw
604 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) in ath5k_hw_rf_gainf_adjust() argument
610 switch (ah->ah_radio) { in ath5k_hw_rf_gainf_adjust()
621 g_step = &go->go_step[ah->ah_gain.g_step_idx]; in ath5k_hw_rf_gainf_adjust()
623 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { in ath5k_hw_rf_gainf_adjust()
626 if (ah->ah_gain.g_step_idx == 0) in ath5k_hw_rf_gainf_adjust()
627 return -1; in ath5k_hw_rf_gainf_adjust()
629 for (ah->ah_gain.g_target = ah->ah_gain.g_current; in ath5k_hw_rf_gainf_adjust()
630 ah->ah_gain.g_target >= ah->ah_gain.g_high && in ath5k_hw_rf_gainf_adjust()
631 ah->ah_gain.g_step_idx > 0; in ath5k_hw_rf_gainf_adjust()
632 g_step = &go->go_step[ah->ah_gain.g_step_idx]) in ath5k_hw_rf_gainf_adjust()
633 ah->ah_gain.g_target -= 2 * in ath5k_hw_rf_gainf_adjust()
634 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - in ath5k_hw_rf_gainf_adjust()
635 g_step->gos_gain); in ath5k_hw_rf_gainf_adjust()
641 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { in ath5k_hw_rf_gainf_adjust()
644 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) in ath5k_hw_rf_gainf_adjust()
645 return -2; in ath5k_hw_rf_gainf_adjust()
647 for (ah->ah_gain.g_target = ah->ah_gain.g_current; in ath5k_hw_rf_gainf_adjust()
648 ah->ah_gain.g_target <= ah->ah_gain.g_low && in ath5k_hw_rf_gainf_adjust()
649 ah->ah_gain.g_step_idx < go->go_steps_count - 1; in ath5k_hw_rf_gainf_adjust()
650 g_step = &go->go_step[ah->ah_gain.g_step_idx]) in ath5k_hw_rf_gainf_adjust()
651 ah->ah_gain.g_target -= 2 * in ath5k_hw_rf_gainf_adjust()
652 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - in ath5k_hw_rf_gainf_adjust()
653 g_step->gos_gain); in ath5k_hw_rf_gainf_adjust()
660 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_rf_gainf_adjust()
662 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, in ath5k_hw_rf_gainf_adjust()
663 ah->ah_gain.g_target); in ath5k_hw_rf_gainf_adjust()
669 * ath5k_hw_gainf_calibrate() - Do a gain_F calibration
670 * @ah: The &struct ath5k_hw
679 ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) in ath5k_hw_gainf_calibrate() argument
682 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_gainf_calibrate()
684 if (ah->ah_rf_banks == NULL || in ath5k_hw_gainf_calibrate()
685 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) in ath5k_hw_gainf_calibrate()
690 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) in ath5k_hw_gainf_calibrate()
695 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); in ath5k_hw_gainf_calibrate()
699 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; in ath5k_hw_gainf_calibrate()
705 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) in ath5k_hw_gainf_calibrate()
706 ah->ah_gain.g_current += in ath5k_hw_gainf_calibrate()
707 ee->ee_cck_ofdm_gain_delta; in ath5k_hw_gainf_calibrate()
709 ah->ah_gain.g_current += in ath5k_hw_gainf_calibrate()
715 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { in ath5k_hw_gainf_calibrate()
716 ath5k_hw_rf_gainf_corr(ah); in ath5k_hw_gainf_calibrate()
717 ah->ah_gain.g_current = in ath5k_hw_gainf_calibrate()
718 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? in ath5k_hw_gainf_calibrate()
719 (ah->ah_gain.g_current - ah->ah_gain.g_f_corr) : in ath5k_hw_gainf_calibrate()
726 if (ath5k_hw_rf_check_gainf_readback(ah) && in ath5k_hw_gainf_calibrate()
727 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && in ath5k_hw_gainf_calibrate()
728 ath5k_hw_rf_gainf_adjust(ah)) { in ath5k_hw_gainf_calibrate()
729 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; in ath5k_hw_gainf_calibrate()
731 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_gainf_calibrate()
736 return ah->ah_gain.g_state; in ath5k_hw_gainf_calibrate()
740 * ath5k_hw_rfgain_init() - Write initial RF gain settings to hw
741 * @ah: The &struct ath5k_hw
750 ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum nl80211_band band) in ath5k_hw_rfgain_init() argument
755 switch (ah->ah_radio) { in ath5k_hw_rfgain_init()
782 return -EINVAL; in ath5k_hw_rfgain_init()
789 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index], in ath5k_hw_rfgain_init()
802 * ath5k_hw_rfregs_init() - Initialize RF register settings
803 * @ah: The &struct ath5k_hw
811 ath5k_hw_rfregs_init(struct ath5k_hw *ah, in ath5k_hw_rfregs_init() argument
819 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_rfregs_init()
822 int i, obdb = -1, bank = -1; in ath5k_hw_rfregs_init()
824 switch (ah->ah_radio) { in ath5k_hw_rfregs_init()
827 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); in ath5k_hw_rfregs_init()
829 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); in ath5k_hw_rfregs_init()
833 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { in ath5k_hw_rfregs_init()
835 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); in ath5k_hw_rfregs_init()
837 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); in ath5k_hw_rfregs_init()
840 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); in ath5k_hw_rfregs_init()
842 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); in ath5k_hw_rfregs_init()
848 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); in ath5k_hw_rfregs_init()
850 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); in ath5k_hw_rfregs_init()
854 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); in ath5k_hw_rfregs_init()
856 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); in ath5k_hw_rfregs_init()
860 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); in ath5k_hw_rfregs_init()
862 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); in ath5k_hw_rfregs_init()
866 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); in ath5k_hw_rfregs_init()
868 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); in ath5k_hw_rfregs_init()
872 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); in ath5k_hw_rfregs_init()
873 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { in ath5k_hw_rfregs_init()
875 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); in ath5k_hw_rfregs_init()
878 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); in ath5k_hw_rfregs_init()
882 return -EINVAL; in ath5k_hw_rfregs_init()
886 * ah->ah_rf_banks based on ah->ah_rf_banks_size in ath5k_hw_rfregs_init()
888 if (ah->ah_rf_banks == NULL) { in ath5k_hw_rfregs_init()
889 ah->ah_rf_banks = kmalloc_array(ah->ah_rf_banks_size, in ath5k_hw_rfregs_init()
892 if (ah->ah_rf_banks == NULL) { in ath5k_hw_rfregs_init()
893 ATH5K_ERR(ah, "out of memory\n"); in ath5k_hw_rfregs_init()
894 return -ENOMEM; in ath5k_hw_rfregs_init()
899 rfb = ah->ah_rf_banks; in ath5k_hw_rfregs_init()
901 for (i = 0; i < ah->ah_rf_banks_size; i++) { in ath5k_hw_rfregs_init()
903 ATH5K_ERR(ah, "invalid bank\n"); in ath5k_hw_rfregs_init()
904 return -EINVAL; in ath5k_hw_rfregs_init()
910 ah->ah_offset[bank] = i; in ath5k_hw_rfregs_init()
917 if (channel->band == NL80211_BAND_2GHZ) { in ath5k_hw_rfregs_init()
919 if (channel->hw_value == AR5K_MODE_11B) in ath5k_hw_rfregs_init()
926 * in eeprom on ee->ee_ob[ee_mode][0] in ath5k_hw_rfregs_init()
930 * 802.11a on ee->ee_ob[ee_mode][1] */ in ath5k_hw_rfregs_init()
931 if ((ah->ah_radio == AR5K_RF5111) || in ath5k_hw_rfregs_init()
932 (ah->ah_radio == AR5K_RF5112)) in ath5k_hw_rfregs_init()
937 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], in ath5k_hw_rfregs_init()
940 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], in ath5k_hw_rfregs_init()
943 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ in ath5k_hw_rfregs_init()
944 } else if ((channel->band == NL80211_BAND_5GHZ) || in ath5k_hw_rfregs_init()
945 (ah->ah_radio == AR5K_RF5111)) { in ath5k_hw_rfregs_init()
950 obdb = channel->center_freq >= 5725 ? 3 : in ath5k_hw_rfregs_init()
951 (channel->center_freq >= 5500 ? 2 : in ath5k_hw_rfregs_init()
952 (channel->center_freq >= 5260 ? 1 : in ath5k_hw_rfregs_init()
953 (channel->center_freq > 4000 ? 0 : -1))); in ath5k_hw_rfregs_init()
956 return -EINVAL; in ath5k_hw_rfregs_init()
958 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], in ath5k_hw_rfregs_init()
961 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], in ath5k_hw_rfregs_init()
965 g_step = &go->go_step[ah->ah_gain.g_step_idx]; in ath5k_hw_rfregs_init()
968 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) && in ath5k_hw_rfregs_init()
969 (ah->ah_radio != AR5K_RF5413)) in ath5k_hw_rfregs_init()
970 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false); in ath5k_hw_rfregs_init()
972 /* Bank Modifications (chip-specific) */ in ath5k_hw_rfregs_init()
973 if (ah->ah_radio == AR5K_RF5111) { in ath5k_hw_rfregs_init()
976 if (channel->hw_value != AR5K_MODE_11B) { in ath5k_hw_rfregs_init()
978 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, in ath5k_hw_rfregs_init()
980 g_step->gos_param[0]); in ath5k_hw_rfregs_init()
982 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], in ath5k_hw_rfregs_init()
985 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], in ath5k_hw_rfregs_init()
988 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], in ath5k_hw_rfregs_init()
993 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_rfregs_init()
999 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], in ath5k_hw_rfregs_init()
1002 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], in ath5k_hw_rfregs_init()
1005 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], in ath5k_hw_rfregs_init()
1008 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], in ath5k_hw_rfregs_init()
1012 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || in ath5k_hw_rfregs_init()
1013 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { in ath5k_hw_rfregs_init()
1016 ath5k_hw_rfb_op(ah, rf_regs, 0x1f, in ath5k_hw_rfregs_init()
1019 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? in ath5k_hw_rfregs_init()
1022 ath5k_hw_rfb_op(ah, rf_regs, wait_i, in ath5k_hw_rfregs_init()
1024 ath5k_hw_rfb_op(ah, rf_regs, 3, in ath5k_hw_rfregs_init()
1030 if (ah->ah_radio == AR5K_RF5112) { in ath5k_hw_rfregs_init()
1033 if (channel->hw_value != AR5K_MODE_11B) { in ath5k_hw_rfregs_init()
1035 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], in ath5k_hw_rfregs_init()
1038 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], in ath5k_hw_rfregs_init()
1041 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], in ath5k_hw_rfregs_init()
1044 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], in ath5k_hw_rfregs_init()
1047 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], in ath5k_hw_rfregs_init()
1050 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], in ath5k_hw_rfregs_init()
1053 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], in ath5k_hw_rfregs_init()
1058 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_rfregs_init()
1063 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], in ath5k_hw_rfregs_init()
1066 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { in ath5k_hw_rfregs_init()
1068 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1069 ee->ee_x_gain[ee_mode], in ath5k_hw_rfregs_init()
1073 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; in ath5k_hw_rfregs_init()
1074 if (ee->ee_pd_gains[ee_mode] > 1) { in ath5k_hw_rfregs_init()
1075 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1078 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1082 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1085 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1091 if (ah->ah_radio == AR5K_RF5112 && in ath5k_hw_rfregs_init()
1092 (ah->ah_radio_5ghz_revision & AR5K_SREV_REV) > 0) { in ath5k_hw_rfregs_init()
1093 ath5k_hw_rfb_op(ah, rf_regs, 2, in ath5k_hw_rfregs_init()
1096 ath5k_hw_rfb_op(ah, rf_regs, 2, in ath5k_hw_rfregs_init()
1099 ath5k_hw_rfb_op(ah, rf_regs, 2, in ath5k_hw_rfregs_init()
1102 ath5k_hw_rfb_op(ah, rf_regs, 2, in ath5k_hw_rfregs_init()
1107 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { in ath5k_hw_rfregs_init()
1108 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1111 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1114 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1117 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1120 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1125 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], in ath5k_hw_rfregs_init()
1129 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || in ath5k_hw_rfregs_init()
1130 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { in ath5k_hw_rfregs_init()
1133 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? in ath5k_hw_rfregs_init()
1136 ath5k_hw_rfb_op(ah, rf_regs, pd_delay, in ath5k_hw_rfregs_init()
1138 ath5k_hw_rfb_op(ah, rf_regs, 0xf, in ath5k_hw_rfregs_init()
1144 if (ah->ah_radio == AR5K_RF5413 && in ath5k_hw_rfregs_init()
1145 channel->band == NL80211_BAND_2GHZ) { in ath5k_hw_rfregs_init()
1147 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, in ath5k_hw_rfregs_init()
1150 /* Set optimum value for early revisions (on pci-e chips) */ in ath5k_hw_rfregs_init()
1151 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && in ath5k_hw_rfregs_init()
1152 ah->ah_mac_srev < AR5K_SREV_AR5413) in ath5k_hw_rfregs_init()
1153 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), in ath5k_hw_rfregs_init()
1159 for (i = 0; i < ah->ah_rf_banks_size; i++) { in ath5k_hw_rfregs_init()
1161 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); in ath5k_hw_rfregs_init()
1173 * ath5k_hw_rf5110_chan2athchan() - Convert channel freq on RF5110
1186 channel->center_freq) - 24) / 2, 5) in ath5k_hw_rf5110_chan2athchan()
1192 * ath5k_hw_rf5110_channel() - Set channel frequency on RF5110
1193 * @ah: The &struct ath5k_hw
1197 ath5k_hw_rf5110_channel(struct ath5k_hw *ah, in ath5k_hw_rf5110_channel() argument
1206 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); in ath5k_hw_rf5110_channel()
1207 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); in ath5k_hw_rf5110_channel()
1214 * ath5k_hw_rf5111_chan2athchan() - Handle 2GHz channels on RF5111/2111
1229 /* Cast this value to catch negative channel numbers (>= -19) */ in ath5k_hw_rf5111_chan2athchan()
1233 * Map 2GHz IEEE channel to 5GHz Atheros channel in ath5k_hw_rf5111_chan2athchan()
1236 athchan->a2_athchan = 115 + channel; in ath5k_hw_rf5111_chan2athchan()
1237 athchan->a2_flags = 0x46; in ath5k_hw_rf5111_chan2athchan()
1239 athchan->a2_athchan = 124; in ath5k_hw_rf5111_chan2athchan()
1240 athchan->a2_flags = 0x44; in ath5k_hw_rf5111_chan2athchan()
1242 athchan->a2_athchan = ((channel - 14) * 4) + 132; in ath5k_hw_rf5111_chan2athchan()
1243 athchan->a2_flags = 0x46; in ath5k_hw_rf5111_chan2athchan()
1245 return -EINVAL; in ath5k_hw_rf5111_chan2athchan()
1251 * ath5k_hw_rf5111_channel() - Set channel frequency on RF5111/2111
1252 * @ah: The &struct ath5k_hw
1256 ath5k_hw_rf5111_channel(struct ath5k_hw *ah, in ath5k_hw_rf5111_channel() argument
1261 ieee80211_frequency_to_channel(channel->center_freq); in ath5k_hw_rf5111_channel()
1270 if (channel->band == NL80211_BAND_2GHZ) { in ath5k_hw_rf5111_channel()
1271 /* Map 2GHz channel to 5GHz Atheros channel ID */ in ath5k_hw_rf5111_channel()
1273 ieee80211_frequency_to_channel(channel->center_freq), in ath5k_hw_rf5111_channel()
1280 << 5) | (1 << 4); in ath5k_hw_rf5111_channel()
1285 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | in ath5k_hw_rf5111_channel()
1289 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) in ath5k_hw_rf5111_channel()
1293 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), in ath5k_hw_rf5111_channel()
1295 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), in ath5k_hw_rf5111_channel()
1302 * ath5k_hw_rf5112_channel() - Set channel frequency on 5112 and newer
1303 * @ah: The &struct ath5k_hw
1314 ath5k_hw_rf5112_channel(struct ath5k_hw *ah, in ath5k_hw_rf5112_channel() argument
1321 c = channel->center_freq; in ath5k_hw_rf5112_channel()
1330 * below/above (non-standard channels) */ in ath5k_hw_rf5112_channel()
1331 if (!((c - 2224) % 5)) { in ath5k_hw_rf5112_channel()
1332 /* Same as (c - 2224) / 5 */ in ath5k_hw_rf5112_channel()
1333 data0 = ((2 * (c - 704)) - 3040) / 10; in ath5k_hw_rf5112_channel()
1335 /* Channel 1 and all frequencies with 5Hz spacing in ath5k_hw_rf5112_channel()
1337 } else if (!((c - 2192) % 5)) { in ath5k_hw_rf5112_channel()
1338 /* Same as (c - 2192) / 5 */ in ath5k_hw_rf5112_channel()
1339 data0 = ((2 * (c - 672)) - 3040) / 10; in ath5k_hw_rf5112_channel()
1342 return -EINVAL; in ath5k_hw_rf5112_channel()
1354 } else if ((c % 5) != 2 || c > 5435) { in ath5k_hw_rf5112_channel()
1356 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); in ath5k_hw_rf5112_channel()
1359 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); in ath5k_hw_rf5112_channel()
1361 } else if (!(c % 5)) { in ath5k_hw_rf5112_channel()
1362 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); in ath5k_hw_rf5112_channel()
1365 return -EINVAL; in ath5k_hw_rf5112_channel()
1367 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); in ath5k_hw_rf5112_channel()
1373 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); in ath5k_hw_rf5112_channel()
1374 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); in ath5k_hw_rf5112_channel()
1380 * ath5k_hw_rf2425_channel() - Set channel frequency on RF2425
1381 * @ah: The &struct ath5k_hw
1388 ath5k_hw_rf2425_channel(struct ath5k_hw *ah, in ath5k_hw_rf2425_channel() argument
1395 c = channel->center_freq; in ath5k_hw_rf2425_channel()
1398 data0 = ath5k_hw_bitswap((c - 2272), 8); in ath5k_hw_rf2425_channel()
1400 /* ? 5GHz ? */ in ath5k_hw_rf2425_channel()
1401 } else if ((c % 5) != 2 || c > 5435) { in ath5k_hw_rf2425_channel()
1403 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); in ath5k_hw_rf2425_channel()
1405 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); in ath5k_hw_rf2425_channel()
1406 else if (!(c % 5)) in ath5k_hw_rf2425_channel()
1407 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); in ath5k_hw_rf2425_channel()
1409 return -EINVAL; in ath5k_hw_rf2425_channel()
1412 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); in ath5k_hw_rf2425_channel()
1418 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); in ath5k_hw_rf2425_channel()
1419 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); in ath5k_hw_rf2425_channel()
1425 * ath5k_hw_channel() - Set a channel on the radio chip
1426 * @ah: The &struct ath5k_hw
1433 ath5k_hw_channel(struct ath5k_hw *ah, in ath5k_hw_channel() argument
1441 if (!ath5k_channel_ok(ah, channel)) { in ath5k_hw_channel()
1442 ATH5K_ERR(ah, in ath5k_hw_channel()
1445 channel->center_freq); in ath5k_hw_channel()
1446 return -EINVAL; in ath5k_hw_channel()
1452 switch (ah->ah_radio) { in ath5k_hw_channel()
1454 ret = ath5k_hw_rf5110_channel(ah, channel); in ath5k_hw_channel()
1457 ret = ath5k_hw_rf5111_channel(ah, channel); in ath5k_hw_channel()
1461 ret = ath5k_hw_rf2425_channel(ah, channel); in ath5k_hw_channel()
1464 ret = ath5k_hw_rf5112_channel(ah, channel); in ath5k_hw_channel()
1472 if (channel->center_freq == 2484) { in ath5k_hw_channel()
1473 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, in ath5k_hw_channel()
1476 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, in ath5k_hw_channel()
1480 ah->ah_current_channel = channel; in ath5k_hw_channel()
1496 * sample-and-hold the minimum noise level seen at the antennas.
1520 * ath5k_hw_read_measured_noise_floor() - Read measured NF from hw
1521 * @ah: The &struct ath5k_hw
1524 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) in ath5k_hw_read_measured_noise_floor() argument
1528 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); in ath5k_hw_read_measured_noise_floor()
1533 * ath5k_hw_init_nfcal_hist() - Initialize NF calibration history buffer
1534 * @ah: The &struct ath5k_hw
1537 ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) in ath5k_hw_init_nfcal_hist() argument
1541 ah->ah_nfcal_hist.index = 0; in ath5k_hw_init_nfcal_hist()
1543 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; in ath5k_hw_init_nfcal_hist()
1547 * ath5k_hw_update_nfcal_hist() - Update NF calibration history buffer
1548 * @ah: The &struct ath5k_hw
1551 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) in ath5k_hw_update_nfcal_hist() argument
1553 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; in ath5k_hw_update_nfcal_hist()
1554 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX - 1); in ath5k_hw_update_nfcal_hist()
1555 hist->nfval[hist->index] = noise_floor; in ath5k_hw_update_nfcal_hist()
1560 return *(s16 *)a - *(s16 *)b; in cmps16()
1564 * ath5k_hw_get_median_noise_floor() - Get median NF from history buffer
1565 * @ah: The &struct ath5k_hw
1568 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) in ath5k_hw_get_median_noise_floor() argument
1573 memcpy(sorted_nfval, ah->ah_nfcal_hist.nfval, sizeof(sorted_nfval)); in ath5k_hw_get_median_noise_floor()
1576 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_get_median_noise_floor()
1579 return sorted_nfval[(ATH5K_NF_CAL_HIST_MAX - 1) / 2]; in ath5k_hw_get_median_noise_floor()
1583 * ath5k_hw_update_noise_floor() - Update NF on hardware
1584 * @ah: The &struct ath5k_hw
1591 ath5k_hw_update_noise_floor(struct ath5k_hw *ah) in ath5k_hw_update_noise_floor() argument
1593 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_update_noise_floor()
1599 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { in ath5k_hw_update_noise_floor()
1600 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_update_noise_floor()
1606 ah->ah_cal_mask |= AR5K_CALIBRATION_NF; in ath5k_hw_update_noise_floor()
1608 ee_mode = ath5k_eeprom_mode_from_channel(ah, ah->ah_current_channel); in ath5k_hw_update_noise_floor()
1611 nf = ath5k_hw_read_measured_noise_floor(ah); in ath5k_hw_update_noise_floor()
1612 threshold = ee->ee_noise_floor_thr[ee_mode]; in ath5k_hw_update_noise_floor()
1615 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_update_noise_floor()
1623 ath5k_hw_update_nfcal_hist(ah, nf); in ath5k_hw_update_noise_floor()
1624 nf = ath5k_hw_get_median_noise_floor(ah); in ath5k_hw_update_noise_floor()
1626 /* load noise floor (in .5 dBm) so the hardware will use it */ in ath5k_hw_update_noise_floor()
1627 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; in ath5k_hw_update_noise_floor()
1629 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); in ath5k_hw_update_noise_floor()
1631 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, in ath5k_hw_update_noise_floor()
1634 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, in ath5k_hw_update_noise_floor()
1638 * Load a high max CCA Power value (-50 dBm in .5 dBm units) in ath5k_hw_update_noise_floor()
1643 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M); in ath5k_hw_update_noise_floor()
1644 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); in ath5k_hw_update_noise_floor()
1645 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_update_noise_floor()
1650 ah->ah_noise_floor = nf; in ath5k_hw_update_noise_floor()
1652 ah->ah_cal_mask &= ~AR5K_CALIBRATION_NF; in ath5k_hw_update_noise_floor()
1654 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_update_noise_floor()
1659 * ath5k_hw_rf5110_calibrate() - Perform a PHY calibration on RF5110
1660 * @ah: The &struct ath5k_hw
1666 ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, in ath5k_hw_rf5110_calibrate() argument
1672 if (!(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) in ath5k_hw_rf5110_calibrate()
1678 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, in ath5k_hw_rf5110_calibrate()
1680 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); in ath5k_hw_rf5110_calibrate()
1681 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); in ath5k_hw_rf5110_calibrate()
1688 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); in ath5k_hw_rf5110_calibrate()
1690 ret = ath5k_hw_channel(ah, channel); in ath5k_hw_rf5110_calibrate()
1695 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); in ath5k_hw_rf5110_calibrate()
1698 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); in ath5k_hw_rf5110_calibrate()
1708 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); in ath5k_hw_rf5110_calibrate()
1709 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); in ath5k_hw_rf5110_calibrate()
1710 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); in ath5k_hw_rf5110_calibrate()
1713 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | in ath5k_hw_rf5110_calibrate()
1714 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); in ath5k_hw_rf5110_calibrate()
1716 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | in ath5k_hw_rf5110_calibrate()
1718 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | in ath5k_hw_rf5110_calibrate()
1719 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); in ath5k_hw_rf5110_calibrate()
1721 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | in ath5k_hw_rf5110_calibrate()
1728 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); in ath5k_hw_rf5110_calibrate()
1730 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); in ath5k_hw_rf5110_calibrate()
1731 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); in ath5k_hw_rf5110_calibrate()
1738 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); in ath5k_hw_rf5110_calibrate()
1740 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, in ath5k_hw_rf5110_calibrate()
1744 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); in ath5k_hw_rf5110_calibrate()
1745 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); in ath5k_hw_rf5110_calibrate()
1746 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); in ath5k_hw_rf5110_calibrate()
1749 ATH5K_ERR(ah, "calibration timeout (%uMHz)\n", in ath5k_hw_rf5110_calibrate()
1750 channel->center_freq); in ath5k_hw_rf5110_calibrate()
1755 * Re-enable RX/TX and beacons in ath5k_hw_rf5110_calibrate()
1757 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, in ath5k_hw_rf5110_calibrate()
1759 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); in ath5k_hw_rf5110_calibrate()
1765 * ath5k_hw_rf511x_iq_calibrate() - Perform I/Q calibration on RF5111 and newer
1766 * @ah: The &struct ath5k_hw
1769 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah) in ath5k_hw_rf511x_iq_calibrate() argument
1776 if (!ah->ah_iq_cal_needed) in ath5k_hw_rf511x_iq_calibrate()
1777 return -EINVAL; in ath5k_hw_rf511x_iq_calibrate()
1778 else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) { in ath5k_hw_rf511x_iq_calibrate()
1779 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_rf511x_iq_calibrate()
1781 return -EBUSY; in ath5k_hw_rf511x_iq_calibrate()
1784 /* Calibration has finished, get the results and re-run */ in ath5k_hw_rf511x_iq_calibrate()
1789 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); in ath5k_hw_rf511x_iq_calibrate()
1790 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); in ath5k_hw_rf511x_iq_calibrate()
1791 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); in ath5k_hw_rf511x_iq_calibrate()
1792 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_rf511x_iq_calibrate()
1800 if (ah->ah_version == AR5K_AR5211) in ath5k_hw_rf511x_iq_calibrate()
1809 return -ECANCELED; in ath5k_hw_rf511x_iq_calibrate()
1813 i_coff = (-iq_corr) / i_coffd; in ath5k_hw_rf511x_iq_calibrate()
1814 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */ in ath5k_hw_rf511x_iq_calibrate()
1816 if (ah->ah_version == AR5K_AR5211) in ath5k_hw_rf511x_iq_calibrate()
1817 q_coff = (i_pwr / q_coffd) - 64; in ath5k_hw_rf511x_iq_calibrate()
1819 q_coff = (i_pwr / q_coffd) - 128; in ath5k_hw_rf511x_iq_calibrate()
1820 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ in ath5k_hw_rf511x_iq_calibrate()
1822 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_rf511x_iq_calibrate()
1827 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); in ath5k_hw_rf511x_iq_calibrate()
1828 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); in ath5k_hw_rf511x_iq_calibrate()
1829 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); in ath5k_hw_rf511x_iq_calibrate()
1831 /* Re-enable calibration -if we don't we'll commit in ath5k_hw_rf511x_iq_calibrate()
1833 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_rf511x_iq_calibrate()
1835 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); in ath5k_hw_rf511x_iq_calibrate()
1841 * ath5k_hw_phy_calibrate() - Perform a PHY calibration
1842 * @ah: The &struct ath5k_hw
1850 ath5k_hw_phy_calibrate(struct ath5k_hw *ah, in ath5k_hw_phy_calibrate() argument
1855 if (ah->ah_radio == AR5K_RF5110) in ath5k_hw_phy_calibrate()
1856 return ath5k_hw_rf5110_calibrate(ah, channel); in ath5k_hw_phy_calibrate()
1858 ret = ath5k_hw_rf511x_iq_calibrate(ah); in ath5k_hw_phy_calibrate()
1860 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_phy_calibrate()
1862 channel->center_freq); in ath5k_hw_phy_calibrate()
1871 if ((ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && in ath5k_hw_phy_calibrate()
1872 (ah->ah_radio == AR5K_RF5111 || in ath5k_hw_phy_calibrate()
1873 ah->ah_radio == AR5K_RF5112) && in ath5k_hw_phy_calibrate()
1874 channel->hw_value != AR5K_MODE_11B) in ath5k_hw_phy_calibrate()
1875 ath5k_hw_request_rfgain_probe(ah); in ath5k_hw_phy_calibrate()
1878 if (!(ah->ah_cal_mask & AR5K_CALIBRATION_NF)) in ath5k_hw_phy_calibrate()
1879 ath5k_hw_update_noise_floor(ah); in ath5k_hw_phy_calibrate()
1890 * ath5k_hw_set_spur_mitigation_filter() - Configure SPUR filter
1891 * @ah: The &struct ath5k_hw
1900 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, in ath5k_hw_set_spur_mitigation_filter() argument
1903 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_set_spur_mitigation_filter()
1915 if (channel->band == NL80211_BAND_2GHZ) { in ath5k_hw_set_spur_mitigation_filter()
1916 chan_fbin = (channel->center_freq - 2300) * 10; in ath5k_hw_set_spur_mitigation_filter()
1919 chan_fbin = (channel->center_freq - 4900) * 10; in ath5k_hw_set_spur_mitigation_filter()
1928 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) in ath5k_hw_set_spur_mitigation_filter()
1932 spur_chan_fbin = ee->ee_spur_chans[i][freq_band]; in ath5k_hw_set_spur_mitigation_filter()
1941 if ((chan_fbin - spur_detection_window <= in ath5k_hw_set_spur_mitigation_filter()
1952 spur_offset = spur_chan_fbin - chan_fbin; in ath5k_hw_set_spur_mitigation_filter()
1955 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21 in ath5k_hw_set_spur_mitigation_filter()
1956 * spur_delta_phase -> spur_offset / chip_freq << 11 in ath5k_hw_set_spur_mitigation_filter()
1959 switch (ah->ah_bwmode) { in ath5k_hw_set_spur_mitigation_filter()
1979 if (channel->band == NL80211_BAND_5GHZ) { in ath5k_hw_set_spur_mitigation_filter()
1987 /* sample_freq -> 40MHz chip_freq -> 44MHz in ath5k_hw_set_spur_mitigation_filter()
2025 (i == 0 || i == (num_symbol_offsets - 1)) in ath5k_hw_set_spur_mitigation_filter()
2032 pilot_mask[0] |= 1 << (curr_sym_off - 1); in ath5k_hw_set_spur_mitigation_filter()
2034 pilot_mask[1] |= 1 << (curr_sym_off - 33); in ath5k_hw_set_spur_mitigation_filter()
2037 if (curr_sym_off >= -1 && curr_sym_off <= 14) in ath5k_hw_set_spur_mitigation_filter()
2042 plt_mag_map << (curr_sym_off - 15) * 2; in ath5k_hw_set_spur_mitigation_filter()
2045 plt_mag_map << (curr_sym_off - 31) * 2; in ath5k_hw_set_spur_mitigation_filter()
2048 plt_mag_map << (curr_sym_off - 47) * 2; in ath5k_hw_set_spur_mitigation_filter()
2053 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, in ath5k_hw_set_spur_mitigation_filter()
2056 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_set_spur_mitigation_filter()
2062 ath5k_hw_reg_write(ah, in ath5k_hw_set_spur_mitigation_filter()
2071 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); in ath5k_hw_set_spur_mitigation_filter()
2072 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, in ath5k_hw_set_spur_mitigation_filter()
2076 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); in ath5k_hw_set_spur_mitigation_filter()
2077 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, in ath5k_hw_set_spur_mitigation_filter()
2082 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); in ath5k_hw_set_spur_mitigation_filter()
2083 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); in ath5k_hw_set_spur_mitigation_filter()
2084 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); in ath5k_hw_set_spur_mitigation_filter()
2085 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, in ath5k_hw_set_spur_mitigation_filter()
2089 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); in ath5k_hw_set_spur_mitigation_filter()
2090 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); in ath5k_hw_set_spur_mitigation_filter()
2091 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); in ath5k_hw_set_spur_mitigation_filter()
2092 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, in ath5k_hw_set_spur_mitigation_filter()
2096 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & in ath5k_hw_set_spur_mitigation_filter()
2099 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, in ath5k_hw_set_spur_mitigation_filter()
2101 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_set_spur_mitigation_filter()
2105 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); in ath5k_hw_set_spur_mitigation_filter()
2108 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); in ath5k_hw_set_spur_mitigation_filter()
2109 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, in ath5k_hw_set_spur_mitigation_filter()
2113 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); in ath5k_hw_set_spur_mitigation_filter()
2114 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, in ath5k_hw_set_spur_mitigation_filter()
2119 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); in ath5k_hw_set_spur_mitigation_filter()
2120 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); in ath5k_hw_set_spur_mitigation_filter()
2121 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); in ath5k_hw_set_spur_mitigation_filter()
2122 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, in ath5k_hw_set_spur_mitigation_filter()
2126 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); in ath5k_hw_set_spur_mitigation_filter()
2127 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); in ath5k_hw_set_spur_mitigation_filter()
2128 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); in ath5k_hw_set_spur_mitigation_filter()
2129 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, in ath5k_hw_set_spur_mitigation_filter()
2145 * for 5GHz). Antenna 1 (MAIN) should be omnidirectional, 2 (AUX)
2146 * omnidirectional or sectorial and antennas 3-14 sectorial (or directional).
2151 * (0 for automatic selection, 1 - 14 antenna number).
2157 * AR5K_STA_ID1_DEFAULT_ANTENNA -> When 0 is set as the TX antenna on TX
2161 * AR5K_STA_ID1_DESC_ANTENNA -> Update default antenna after each TX frame to
2164 * AR5K_STA_ID1_RTS_DEF_ANTENNA -> Use default antenna for RTS or else use the
2167 * AR5K_STA_ID1_SELFGEN_DEF_ANT -> Use default antenna for self generated frames
2172 * AR5K_ANTMODE_DEFAULT -> Hw handles antenna diversity etc automatically
2174 * AR5K_ANTMODE_FIXED_A -> Only antenna A (MAIN) is present
2176 * AR5K_ANTMODE_FIXED_B -> Only antenna B (AUX) is present
2178 * AR5K_ANTMODE_SINGLE_AP -> Sta locked on a single ap
2180 * AR5K_ANTMODE_SECTOR_AP -> AP with tx antenna set on tx desc
2182 * AR5K_ANTMODE_SECTOR_STA -> STA with tx antenna set on tx desc
2184 * AR5K_ANTMODE_DEBUG Debug mode -A -> Rx, B-> Tx-
2191 * ath5k_hw_set_def_antenna() - Set default rx antenna on AR5211/5212 and newer
2192 * @ah: The &struct ath5k_hw
2196 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) in ath5k_hw_set_def_antenna() argument
2198 if (ah->ah_version != AR5K_AR5210) in ath5k_hw_set_def_antenna()
2199 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); in ath5k_hw_set_def_antenna()
2203 * ath5k_hw_set_fast_div() - Enable/disable fast rx antenna diversity
2204 * @ah: The &struct ath5k_hw
2209 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) in ath5k_hw_set_fast_div() argument
2217 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_set_fast_div()
2220 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_set_fast_div()
2224 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_set_fast_div()
2232 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, in ath5k_hw_set_fast_div()
2235 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, in ath5k_hw_set_fast_div()
2238 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, in ath5k_hw_set_fast_div()
2241 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, in ath5k_hw_set_fast_div()
2247 * ath5k_hw_set_antenna_switch() - Set up antenna switch table
2248 * @ah: The &struct ath5k_hw
2255 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode) in ath5k_hw_set_antenna_switch() argument
2263 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A) in ath5k_hw_set_antenna_switch()
2265 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B) in ath5k_hw_set_antenna_switch()
2273 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, in ath5k_hw_set_antenna_switch()
2275 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] | in ath5k_hw_set_antenna_switch()
2279 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0], in ath5k_hw_set_antenna_switch()
2281 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1], in ath5k_hw_set_antenna_switch()
2286 * ath5k_hw_set_antenna_mode() - Set antenna operating mode
2287 * @ah: The &struct ath5k_hw
2291 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) in ath5k_hw_set_antenna_mode() argument
2293 struct ieee80211_channel *channel = ah->ah_current_channel; in ath5k_hw_set_antenna_mode()
2303 ah->ah_ant_mode = ant_mode; in ath5k_hw_set_antenna_mode()
2307 def_ant = ah->ah_def_ant; in ath5k_hw_set_antenna_mode()
2309 ee_mode = ath5k_eeprom_mode_from_channel(ah, channel); in ath5k_hw_set_antenna_mode()
2376 ah->ah_tx_ant = tx_ant; in ath5k_hw_set_antenna_mode()
2377 ah->ah_ant_mode = ant_mode; in ath5k_hw_set_antenna_mode()
2378 ah->ah_def_ant = def_ant; in ath5k_hw_set_antenna_mode()
2385 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); in ath5k_hw_set_antenna_mode()
2388 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); in ath5k_hw_set_antenna_mode()
2390 ath5k_hw_set_antenna_switch(ah, ee_mode); in ath5k_hw_set_antenna_mode()
2393 ath5k_hw_set_fast_div(ah, ee_mode, fast_div); in ath5k_hw_set_antenna_mode()
2394 ath5k_hw_set_def_antenna(ah, def_ant); in ath5k_hw_set_antenna_mode()
2407 * ath5k_get_interpolated_value() - Get interpolated Y val between two points
2431 ratio = ((100 * y_right - 100 * y_left) / (x_right - x_left)); in ath5k_get_interpolated_value()
2434 result = y_left + (ratio * (target - x_left) / 100); in ath5k_get_interpolated_value()
2440 * ath5k_get_linear_pcdac_min() - Find vertical boundary (min pwr) for the
2469 pwr_i--; in ath5k_get_linear_pcdac_min()
2483 pwr_i--; in ath5k_get_linear_pcdac_min()
2497 * ath5k_create_power_curve() - Create a Power to PDADC or PCDAC curve
2542 for (i = 0; (i <= (u16) (pmax - pmin)) && in ath5k_create_power_curve()
2548 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { in ath5k_create_power_curve()
2564 * ath5k_get_chan_pcal_surrounding_piers() - Get surrounding calibration piers
2566 * @ah: The &struct ath5k_hw
2571 * Get the surrounding per-channel power calibration piers
2577 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, in ath5k_get_chan_pcal_surrounding_piers() argument
2582 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_get_chan_pcal_surrounding_piers()
2586 u32 target = channel->center_freq; in ath5k_get_chan_pcal_surrounding_piers()
2591 switch (channel->hw_value) { in ath5k_get_chan_pcal_surrounding_piers()
2593 pcinfo = ee->ee_pwr_cal_a; in ath5k_get_chan_pcal_surrounding_piers()
2597 pcinfo = ee->ee_pwr_cal_b; in ath5k_get_chan_pcal_surrounding_piers()
2602 pcinfo = ee->ee_pwr_cal_g; in ath5k_get_chan_pcal_surrounding_piers()
2606 max = ee->ee_n_piers[mode] - 1; in ath5k_get_chan_pcal_surrounding_piers()
2643 idx_l = idx_r - 1; in ath5k_get_chan_pcal_surrounding_piers()
2654 * ath5k_get_rate_pcal_data() - Get the interpolated per-rate power
2656 * @ah: The &struct ath5k_hw *ah,
2660 * Get the surrounding per-rate power calibration data
2666 ath5k_get_rate_pcal_data(struct ath5k_hw *ah, in ath5k_get_rate_pcal_data() argument
2670 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_get_rate_pcal_data()
2674 u32 target = channel->center_freq; in ath5k_get_rate_pcal_data()
2679 switch (channel->hw_value) { in ath5k_get_rate_pcal_data()
2681 rpinfo = ee->ee_rate_tpwr_a; in ath5k_get_rate_pcal_data()
2685 rpinfo = ee->ee_rate_tpwr_b; in ath5k_get_rate_pcal_data()
2690 rpinfo = ee->ee_rate_tpwr_g; in ath5k_get_rate_pcal_data()
2694 max = ee->ee_rate_target_pwr_num[mode] - 1; in ath5k_get_rate_pcal_data()
2697 * piers - same as above */ in ath5k_get_rate_pcal_data()
2717 idx_l = idx_r - 1; in ath5k_get_rate_pcal_data()
2724 rates->freq = target; in ath5k_get_rate_pcal_data()
2726 rates->target_power_6to24 = in ath5k_get_rate_pcal_data()
2732 rates->target_power_36 = in ath5k_get_rate_pcal_data()
2738 rates->target_power_48 = in ath5k_get_rate_pcal_data()
2744 rates->target_power_54 = in ath5k_get_rate_pcal_data()
2752 * ath5k_get_max_ctl_power() - Get max edge power for a given frequency
2753 * @ah: the &struct ath5k_hw
2761 ath5k_get_max_ctl_power(struct ath5k_hw *ah, in ath5k_get_max_ctl_power() argument
2764 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); in ath5k_get_max_ctl_power()
2765 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_get_max_ctl_power()
2766 struct ath5k_edge_power *rep = ee->ee_ctl_pwr; in ath5k_get_max_ctl_power()
2767 u8 *ctl_val = ee->ee_ctl; in ath5k_get_max_ctl_power()
2768 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; in ath5k_get_max_ctl_power()
2773 u32 target = channel->center_freq; in ath5k_get_max_ctl_power()
2775 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band); in ath5k_get_max_ctl_power()
2777 switch (channel->hw_value) { in ath5k_get_max_ctl_power()
2779 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) in ath5k_get_max_ctl_power()
2785 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) in ath5k_get_max_ctl_power()
2797 for (i = 0; i < ee->ee_ctls; i++) { in ath5k_get_max_ctl_power()
2827 ah->ah_txpower.txp_max_pwr = 4 * min(edge_pwr, max_chan_pwr); in ath5k_get_max_ctl_power()
2838 * For RF5111 we have an XPD -eXternal Power Detector- curve
2839 * for each calibrated channel. Each curve has 0,5dB Power steps
2844 * For RF5112 we have 4 XPD -eXternal Power Detector- curves
2845 * for each calibrated channel on 0, -6, -12 and -18dBm but we only
2849 * on hw, we get 4 points for xpd 0 (lower gain -> max power)
2850 * and 3 points for xpd 3 (higher gain -> lower power) from eeprom (eeprom.c)
2854 * -if we don't have calibration data for this specific channel- from the
2864 * ath5k_fill_pwr_to_pcdac_table() - Fill Power to PCDAC table on RF5111
2865 * @ah: The &struct ath5k_hw
2874 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, in ath5k_fill_pwr_to_pcdac_table() argument
2877 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; in ath5k_fill_pwr_to_pcdac_table()
2878 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; in ath5k_fill_pwr_to_pcdac_table()
2887 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; in ath5k_fill_pwr_to_pcdac_table()
2909 * ath5k_combine_linear_pcdac_curves() - Combine available PCDAC Curves
2910 * @ah: The &struct ath5k_hw
2924 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, in ath5k_combine_linear_pcdac_curves() argument
2927 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; in ath5k_combine_linear_pcdac_curves()
2949 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; in ath5k_combine_linear_pcdac_curves()
2950 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; in ath5k_combine_linear_pcdac_curves()
2951 mid_pwr_idx = table_max[1] - table_min[1] - 1; in ath5k_combine_linear_pcdac_curves()
2952 max_pwr_idx = (table_max[0] - table_min[0]) / 2; in ath5k_combine_linear_pcdac_curves()
2957 if (table_max[0] - table_min[1] > 126) in ath5k_combine_linear_pcdac_curves()
2958 min_pwr_idx = table_max[0] - 126; in ath5k_combine_linear_pcdac_curves()
2968 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ in ath5k_combine_linear_pcdac_curves()
2969 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; in ath5k_combine_linear_pcdac_curves()
2971 max_pwr_idx = (table_max[0] - table_min[0]) / 2; in ath5k_combine_linear_pcdac_curves()
2977 ah->ah_txpower.txp_min_idx = min_pwr_idx / 2; in ath5k_combine_linear_pcdac_curves()
2981 for (i = 63; i >= 0; i--) { in ath5k_combine_linear_pcdac_curves()
2986 (2 * pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { in ath5k_combine_linear_pcdac_curves()
2993 * already switched to the lower power curve -or in ath5k_combine_linear_pcdac_curves()
2999 i--; in ath5k_combine_linear_pcdac_curves()
3007 * 126 -this can happen because we OR pcdac_out in ath5k_combine_linear_pcdac_curves()
3013 pwr--; in ath5k_combine_linear_pcdac_curves()
3018 * ath5k_write_pcdac_table() - Write the PCDAC values on hw
3019 * @ah: The &struct ath5k_hw
3022 ath5k_write_pcdac_table(struct ath5k_hw *ah) in ath5k_write_pcdac_table() argument
3024 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; in ath5k_write_pcdac_table()
3031 ath5k_hw_reg_write(ah, in ath5k_write_pcdac_table()
3062 * ath5k_combine_pwr_to_pdadc_curves() - Combine the various PDADC curves
3063 * @ah: The &struct ath5k_hw
3074 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, in ath5k_combine_pwr_to_pdadc_curves() argument
3078 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; in ath5k_combine_pwr_to_pdadc_curves()
3087 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & in ath5k_combine_pwr_to_pdadc_curves()
3092 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; in ath5k_combine_pwr_to_pdadc_curves()
3094 if (pdg == pdcurves - 1) in ath5k_combine_pwr_to_pdadc_curves()
3115 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - in ath5k_combine_pwr_to_pdadc_curves()
3119 pwr_step = max(pdadc_tmp[1] - pdadc_tmp[0], 1); in ath5k_combine_pwr_to_pdadc_curves()
3130 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; in ath5k_combine_pwr_to_pdadc_curves()
3132 table_size = pwr_max[pdg] - pwr_min[pdg]; in ath5k_combine_pwr_to_pdadc_curves()
3144 pwr_step = max(pdadc_tmp[table_size - 1] - in ath5k_combine_pwr_to_pdadc_curves()
3145 pdadc_tmp[table_size - 2], 1); in ath5k_combine_pwr_to_pdadc_curves()
3150 s16 tmp = pdadc_tmp[table_size - 1] + in ath5k_combine_pwr_to_pdadc_curves()
3151 (pdadc_0 - max_idx) * pwr_step; in ath5k_combine_pwr_to_pdadc_curves()
3158 gain_boundaries[pdg] = gain_boundaries[pdg - 1]; in ath5k_combine_pwr_to_pdadc_curves()
3163 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; in ath5k_combine_pwr_to_pdadc_curves()
3168 ath5k_hw_reg_write(ah, in ath5k_combine_pwr_to_pdadc_curves()
3182 ah->ah_txpower.txp_min_idx = pwr_min[0]; in ath5k_combine_pwr_to_pdadc_curves()
3187 * ath5k_write_pwr_to_pdadc_table() - Write the PDADC values on hw
3188 * @ah: The &struct ath5k_hw
3192 ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode) in ath5k_write_pwr_to_pdadc_table() argument
3194 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_write_pwr_to_pdadc_table()
3195 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; in ath5k_write_pwr_to_pdadc_table()
3196 u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode]; in ath5k_write_pwr_to_pdadc_table()
3197 u8 pdcurves = ee->ee_pd_gains[ee_mode]; in ath5k_write_pwr_to_pdadc_table()
3198 u32 reg; in ath5k_write_pwr_to_pdadc_table() local
3204 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); in ath5k_write_pwr_to_pdadc_table()
3205 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | in ath5k_write_pwr_to_pdadc_table()
3216 * 5dB (1 * gain overlap ?) drop. in ath5k_write_pwr_to_pdadc_table()
3218 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); in ath5k_write_pwr_to_pdadc_table()
3222 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); in ath5k_write_pwr_to_pdadc_table()
3225 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); in ath5k_write_pwr_to_pdadc_table()
3228 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); in ath5k_write_pwr_to_pdadc_table()
3231 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); in ath5k_write_pwr_to_pdadc_table()
3238 ath5k_hw_reg_write(ah, val, AR5K_PHY_PDADC_TXPOWER(i)); in ath5k_write_pwr_to_pdadc_table()
3248 * ath5k_setup_channel_powertable() - Set up power table for this channel
3249 * @ah: The &struct ath5k_hw
3261 ath5k_setup_channel_powertable(struct ath5k_hw *ah, in ath5k_setup_channel_powertable() argument
3268 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_setup_channel_powertable()
3269 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; in ath5k_setup_channel_powertable()
3274 u32 target = channel->center_freq; in ath5k_setup_channel_powertable()
3278 ath5k_get_chan_pcal_surrounding_piers(ah, channel, in ath5k_setup_channel_powertable()
3284 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { in ath5k_setup_channel_powertable()
3288 * to higher power. Use curve -> idx in ath5k_setup_channel_powertable()
3293 pdg_L = &pcinfo_L->pd_curves[idx]; in ath5k_setup_channel_powertable()
3294 pdg_R = &pcinfo_R->pd_curves[idx]; in ath5k_setup_channel_powertable()
3297 tmpL = ah->ah_txpower.tmpL[pdg]; in ath5k_setup_channel_powertable()
3298 tmpR = ah->ah_txpower.tmpR[pdg]; in ath5k_setup_channel_powertable()
3306 table_min[pdg] = min(pdg_L->pd_pwr[0], in ath5k_setup_channel_powertable()
3307 pdg_R->pd_pwr[0]) / 2; in ath5k_setup_channel_powertable()
3309 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], in ath5k_setup_channel_powertable()
3310 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; in ath5k_setup_channel_powertable()
3319 table_min[pdg] = min(pdg_L->pd_pwr[0], in ath5k_setup_channel_powertable()
3320 pdg_R->pd_pwr[0]); in ath5k_setup_channel_powertable()
3323 max(pdg_L->pd_pwr[pdg_L->pd_points - 1], in ath5k_setup_channel_powertable()
3324 pdg_R->pd_pwr[pdg_R->pd_points - 1]); in ath5k_setup_channel_powertable()
3331 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { in ath5k_setup_channel_powertable()
3334 ath5k_get_linear_pcdac_min(pdg_L->pd_step, in ath5k_setup_channel_powertable()
3335 pdg_R->pd_step, in ath5k_setup_channel_powertable()
3336 pdg_L->pd_pwr, in ath5k_setup_channel_powertable()
3337 pdg_R->pd_pwr); in ath5k_setup_channel_powertable()
3343 if (table_max[pdg] - table_min[pdg] > 126) in ath5k_setup_channel_powertable()
3344 table_min[pdg] = table_max[pdg] - 126; in ath5k_setup_channel_powertable()
3353 pdg_L->pd_pwr, in ath5k_setup_channel_powertable()
3354 pdg_L->pd_step, in ath5k_setup_channel_powertable()
3355 pdg_L->pd_points, tmpL, type); in ath5k_setup_channel_powertable()
3365 pdg_R->pd_pwr, in ath5k_setup_channel_powertable()
3366 pdg_R->pd_step, in ath5k_setup_channel_powertable()
3367 pdg_R->pd_points, tmpR, type); in ath5k_setup_channel_powertable()
3370 return -EINVAL; in ath5k_setup_channel_powertable()
3376 * pd gain. Re-use tmpL for interpolation in ath5k_setup_channel_powertable()
3378 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && in ath5k_setup_channel_powertable()
3381 (s16) pcinfo_L->freq, in ath5k_setup_channel_powertable()
3382 (s16) pcinfo_R->freq, in ath5k_setup_channel_powertable()
3389 * channel on tmpL (x range is table_max - table_min in ath5k_setup_channel_powertable()
3399 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, in ath5k_setup_channel_powertable()
3400 (s16) pcinfo_L->freq, in ath5k_setup_channel_powertable()
3401 (s16) pcinfo_R->freq, in ath5k_setup_channel_powertable()
3402 pcinfo_L->min_pwr, pcinfo_R->min_pwr); in ath5k_setup_channel_powertable()
3404 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, in ath5k_setup_channel_powertable()
3405 (s16) pcinfo_L->freq, in ath5k_setup_channel_powertable()
3406 (s16) pcinfo_R->freq, in ath5k_setup_channel_powertable()
3407 pcinfo_L->max_pwr, pcinfo_R->max_pwr); in ath5k_setup_channel_powertable()
3415 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, in ath5k_setup_channel_powertable()
3416 ee->ee_pd_gains[ee_mode]); in ath5k_setup_channel_powertable()
3421 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); in ath5k_setup_channel_powertable()
3426 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); in ath5k_setup_channel_powertable()
3429 ah->ah_txpower.txp_min_idx = 0; in ath5k_setup_channel_powertable()
3430 ah->ah_txpower.txp_offset = 0; in ath5k_setup_channel_powertable()
3435 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, in ath5k_setup_channel_powertable()
3436 ee->ee_pd_gains[ee_mode]); in ath5k_setup_channel_powertable()
3440 ah->ah_txpower.txp_offset = table_min[0]; in ath5k_setup_channel_powertable()
3443 return -EINVAL; in ath5k_setup_channel_powertable()
3446 ah->ah_txpower.txp_setup = true; in ath5k_setup_channel_powertable()
3452 * ath5k_write_channel_powertable() - Set power table for current channel on hw
3453 * @ah: The &struct ath5k_hw
3458 ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type) in ath5k_write_channel_powertable() argument
3461 ath5k_write_pwr_to_pdadc_table(ah, ee_mode); in ath5k_write_channel_powertable()
3463 ath5k_write_pcdac_table(ah); in ath5k_write_channel_powertable()
3468 * DOC: Per-rate tx power setting
3482 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps -
3484 * rates[0] - rates[7] -> OFDM rates
3485 * rates[8] - rates[14] -> CCK rates
3486 * rates[15] -> XR rates (they all have the same power)
3490 * ath5k_setup_rate_powertable() - Set up rate power table for a given tx power
3491 * @ah: The &struct ath5k_hw
3497 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, in ath5k_setup_rate_powertable() argument
3508 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; in ath5k_setup_rate_powertable()
3511 rates = ah->ah_txpower.txp_rates_power_table; in ath5k_setup_rate_powertable()
3514 for (i = 0; i < 5; i++) in ath5k_setup_rate_powertable()
3515 rates[i] = min(max_pwr, rate_info->target_power_6to24); in ath5k_setup_rate_powertable()
3518 rates[5] = min(rates[0], rate_info->target_power_36); in ath5k_setup_rate_powertable()
3519 rates[6] = min(rates[0], rate_info->target_power_48); in ath5k_setup_rate_powertable()
3520 rates[7] = min(rates[0], rate_info->target_power_54); in ath5k_setup_rate_powertable()
3524 rates[8] = min(rates[0], rate_info->target_power_6to24); in ath5k_setup_rate_powertable()
3526 rates[9] = min(rates[0], rate_info->target_power_36); in ath5k_setup_rate_powertable()
3528 rates[10] = min(rates[0], rate_info->target_power_36); in ath5k_setup_rate_powertable()
3529 /* 5L */ in ath5k_setup_rate_powertable()
3530 rates[11] = min(rates[0], rate_info->target_power_48); in ath5k_setup_rate_powertable()
3531 /* 5S */ in ath5k_setup_rate_powertable()
3532 rates[12] = min(rates[0], rate_info->target_power_48); in ath5k_setup_rate_powertable()
3534 rates[13] = min(rates[0], rate_info->target_power_54); in ath5k_setup_rate_powertable()
3536 rates[14] = min(rates[0], rate_info->target_power_54); in ath5k_setup_rate_powertable()
3539 rates[15] = min(rates[0], rate_info->target_power_6to24); in ath5k_setup_rate_powertable()
3546 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) in ath5k_setup_rate_powertable()
3548 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; in ath5k_setup_rate_powertable()
3556 ah->ah_txpower.txp_min_pwr = 2 * rates[7]; in ath5k_setup_rate_powertable()
3557 ah->ah_txpower.txp_cur_pwr = 2 * rates[0]; in ath5k_setup_rate_powertable()
3560 * -that is the txpower for 54Mbit-, it's used for the PAPD in ath5k_setup_rate_powertable()
3562 ah->ah_txpower.txp_ofdm = rates[7]; in ath5k_setup_rate_powertable()
3568 rate_idx_scaled = rates[i] + ah->ah_txpower.txp_offset; in ath5k_setup_rate_powertable()
3580 * ath5k_hw_txpower() - Set transmission power limit for a given channel
3581 * @ah: The &struct ath5k_hw
3589 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, in ath5k_hw_txpower() argument
3593 struct ieee80211_channel *curr_channel = ah->ah_current_channel; in ath5k_hw_txpower()
3599 ATH5K_ERR(ah, "invalid tx power: %u\n", txpower); in ath5k_hw_txpower()
3600 return -EINVAL; in ath5k_hw_txpower()
3603 ee_mode = ath5k_eeprom_mode_from_channel(ah, channel); in ath5k_hw_txpower()
3606 switch (ah->ah_radio) { in ath5k_hw_txpower()
3624 return -EINVAL; in ath5k_hw_txpower()
3631 if (!ah->ah_txpower.txp_setup || in ath5k_hw_txpower()
3632 (channel->hw_value != curr_channel->hw_value) || in ath5k_hw_txpower()
3633 (channel->center_freq != curr_channel->center_freq)) { in ath5k_hw_txpower()
3636 int requested_txpower = ah->ah_txpower.txp_requested; in ath5k_hw_txpower()
3638 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); in ath5k_hw_txpower()
3641 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; in ath5k_hw_txpower()
3643 ah->ah_txpower.txp_requested = requested_txpower; in ath5k_hw_txpower()
3646 ret = ath5k_setup_channel_powertable(ah, channel, in ath5k_hw_txpower()
3653 ath5k_write_channel_powertable(ah, ee_mode, type); in ath5k_hw_txpower()
3656 ath5k_get_max_ctl_power(ah, channel); in ath5k_hw_txpower()
3664 /* Get surrounding channels for per-rate power table in ath5k_hw_txpower()
3666 ath5k_get_rate_pcal_data(ah, channel, &rate_info); in ath5k_hw_txpower()
3669 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); in ath5k_hw_txpower()
3672 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | in ath5k_hw_txpower()
3676 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | in ath5k_hw_txpower()
3677 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | in ath5k_hw_txpower()
3680 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | in ath5k_hw_txpower()
3684 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | in ath5k_hw_txpower()
3689 if (ah->ah_txpower.txp_tpc) { in ath5k_hw_txpower()
3690 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | in ath5k_hw_txpower()
3693 ath5k_hw_reg_write(ah, in ath5k_hw_txpower()
3699 ath5k_hw_reg_write(ah, AR5K_TUNE_MAX_TXPOWER, in ath5k_hw_txpower()
3707 * ath5k_hw_set_txpower_limit() - Set txpower limit for the current channel
3708 * @ah: The &struct ath5k_hw
3715 ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) in ath5k_hw_set_txpower_limit() argument
3717 ATH5K_DBG(ah, ATH5K_DEBUG_TXPOWER, in ath5k_hw_set_txpower_limit()
3720 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower); in ath5k_hw_set_txpower_limit()
3729 * ath5k_hw_phy_init() - Initialize PHY
3730 * @ah: The &struct ath5k_hw
3742 ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, in ath5k_hw_phy_init() argument
3756 curr_channel = ah->ah_current_channel; in ath5k_hw_phy_init()
3757 if (fast && (channel->hw_value != curr_channel->hw_value)) in ath5k_hw_phy_init()
3758 return -EINVAL; in ath5k_hw_phy_init()
3765 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, in ath5k_hw_phy_init()
3768 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT)) in ath5k_hw_phy_init()
3770 udelay(5); in ath5k_hw_phy_init()
3774 return -EIO; in ath5k_hw_phy_init()
3777 ret = ath5k_hw_channel(ah, channel); in ath5k_hw_phy_init()
3781 ath5k_hw_wait_for_synth(ah, channel); in ath5k_hw_phy_init()
3791 ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_requested ? in ath5k_hw_phy_init()
3792 ah->ah_txpower.txp_requested * 2 : in ath5k_hw_phy_init()
3798 if (ah->ah_version == AR5K_AR5212 && in ath5k_hw_phy_init()
3799 channel->hw_value != AR5K_MODE_11B) { in ath5k_hw_phy_init()
3801 ret = ath5k_hw_write_ofdm_timings(ah, channel); in ath5k_hw_phy_init()
3808 if (ah->ah_mac_srev >= AR5K_SREV_AR5424) in ath5k_hw_phy_init()
3809 ath5k_hw_set_spur_mitigation_filter(ah, in ath5k_hw_phy_init()
3825 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, in ath5k_hw_phy_init()
3831 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_phy_init()
3843 if (ah->ah_version != AR5K_AR5210) { in ath5k_hw_phy_init()
3849 ret = ath5k_hw_rfgain_init(ah, channel->band); in ath5k_hw_phy_init()
3858 ret = ath5k_hw_rfregs_init(ah, channel, mode); in ath5k_hw_phy_init()
3864 if (ah->ah_radio == AR5K_RF5111) { in ath5k_hw_phy_init()
3866 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, in ath5k_hw_phy_init()
3869 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, in ath5k_hw_phy_init()
3873 } else if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_phy_init()
3876 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); in ath5k_hw_phy_init()
3881 ret = ath5k_hw_channel(ah, channel); in ath5k_hw_phy_init()
3890 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); in ath5k_hw_phy_init()
3892 ath5k_hw_wait_for_synth(ah, channel); in ath5k_hw_phy_init()
3898 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); in ath5k_hw_phy_init()
3899 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); in ath5k_hw_phy_init()
3901 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) in ath5k_hw_phy_init()
3905 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); in ath5k_hw_phy_init()
3910 * During AGC calibration RX path is re-routed to in ath5k_hw_phy_init()
3914 * used together with on-the fly I/Q calibration (the in ath5k_hw_phy_init()
3918 * While rx path is re-routed to the power detector we also in ath5k_hw_phy_init()
3926 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_phy_init()
3930 * -no need for CCK- */ in ath5k_hw_phy_init()
3931 ah->ah_iq_cal_needed = false; in ath5k_hw_phy_init()
3933 ah->ah_iq_cal_needed = true; in ath5k_hw_phy_init()
3934 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_phy_init()
3936 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_phy_init()
3942 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, in ath5k_hw_phy_init()
3944 ATH5K_ERR(ah, "gain calibration timeout (%uMHz)\n", in ath5k_hw_phy_init()
3945 channel->center_freq); in ath5k_hw_phy_init()
3949 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); in ath5k_hw_phy_init()