Lines Matching +full:reg +full:- +full:5 +full:ah
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
38 /* level: 0 1 2 3 4 5 6 7 8 */
39 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
42 /* level: 0 1 2 3 4 5 6 7 8 */
43 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
125 * ar9003_hw_set_channel - set channel on single-chip device
126 * @ah: atheros hardware structure
129 * This is the function to change channel on single-chip devices, that is
141 * For 5GHz channel,
145 * For 5GHz channels which are 5MHz spaced,
149 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar9003_hw_set_channel() argument
156 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar9003_hw_set_channel()
160 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || in ar9003_hw_set_channel()
161 AR_SREV_9531(ah) || AR_SREV_9550(ah) || in ar9003_hw_set_channel()
162 AR_SREV_9561(ah) || AR_SREV_9565(ah)) { in ar9003_hw_set_channel()
163 if (ah->is_clk_25mhz) in ar9003_hw_set_channel()
171 } else if (AR_SREV_9340(ah)) { in ar9003_hw_set_channel()
172 if (ah->is_clk_25mhz) { in ar9003_hw_set_channel()
185 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) || in ar9003_hw_set_channel()
186 AR_SREV_9531(ah) || AR_SREV_9561(ah)) && in ar9003_hw_set_channel()
187 ah->is_clk_25mhz) { in ar9003_hw_set_channel()
196 /* Set to 5G mode */ in ar9003_hw_set_channel()
206 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9003_hw_set_channel()
209 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, in ar9003_hw_set_channel()
215 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
221 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
223 ah->curchan = chan; in ar9003_hw_set_channel()
229 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
230 * @ah: atheros hardware structure
233 * For single-chip solutions. Converts to baseband spur frequency given the
238 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, in ar9003_hw_spur_mitigate_mrc_cck() argument
245 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan)); in ar9003_hw_spur_mitigate_mrc_cck()
248 * Need to verify range +/- 10 MHz in control channel, otherwise spur in ar9003_hw_spur_mitigate_mrc_cck()
249 * is out-of-band and can be ignored. in ar9003_hw_spur_mitigate_mrc_cck()
252 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ar9003_hw_spur_mitigate_mrc_cck()
253 AR_SREV_9550(ah) || AR_SREV_9561(ah)) { in ar9003_hw_spur_mitigate_mrc_cck()
256 max_spur_cnts = 5; in ar9003_hw_spur_mitigate_mrc_cck()
259 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_mitigate_mrc_cck()
261 synth_freq = chan->channel + 10; in ar9003_hw_spur_mitigate_mrc_cck()
263 synth_freq = chan->channel - 10; in ar9003_hw_spur_mitigate_mrc_cck()
266 synth_freq = chan->channel; in ar9003_hw_spur_mitigate_mrc_cck()
269 range = AR_SREV_9462(ah) ? 5 : 10; in ar9003_hw_spur_mitigate_mrc_cck()
271 synth_freq = chan->channel; in ar9003_hw_spur_mitigate_mrc_cck()
275 if (AR_SREV_9462(ah) && (i == 0 || i == 3)) in ar9003_hw_spur_mitigate_mrc_cck()
279 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ar9003_hw_spur_mitigate_mrc_cck()
280 AR_SREV_9550(ah) || AR_SREV_9561(ah)) in ar9003_hw_spur_mitigate_mrc_cck()
286 cur_bb_spur -= synth_freq; in ar9003_hw_spur_mitigate_mrc_cck()
289 cur_bb_spur = -cur_bb_spur; in ar9003_hw_spur_mitigate_mrc_cck()
295 cck_spur_freq = -cck_spur_freq; in ar9003_hw_spur_mitigate_mrc_cck()
299 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_spur_mitigate_mrc_cck()
301 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
303 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
306 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
309 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
317 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_spur_mitigate_mrc_cck()
319 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
321 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
326 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah) in ar9003_hw_spur_ofdm_clear() argument
328 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
330 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
332 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
334 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_spur_ofdm_clear()
336 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
338 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
340 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
342 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
344 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
347 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
349 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
351 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
353 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
355 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah), in ar9003_hw_spur_ofdm_clear()
357 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
359 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
361 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
363 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah), in ar9003_hw_spur_ofdm_clear()
365 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
369 static void ar9003_hw_spur_ofdm(struct ath_hw *ah, in ar9003_hw_spur_ofdm() argument
380 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
382 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
384 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
386 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_spur_ofdm()
388 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
391 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437)) in ar9003_hw_spur_ofdm()
392 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
395 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
397 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
399 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
402 if (!AR_SREV_9340(ah) && in ar9003_hw_spur_ofdm()
403 REG_READ_FIELD(ah, AR_PHY_MODE, in ar9003_hw_spur_ofdm()
405 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
408 mask_index = (freq_offset << 4) / 5; in ar9003_hw_spur_ofdm()
410 mask_index = mask_index - 1; in ar9003_hw_spur_ofdm()
414 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
416 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
418 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
420 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm()
422 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah), in ar9003_hw_spur_ofdm()
424 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm()
426 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm()
428 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm()
430 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah), in ar9003_hw_spur_ofdm()
432 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
436 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah, in ar9003_hw_spur_ofdm_9565() argument
441 mask_index = (freq_offset << 4) / 5; in ar9003_hw_spur_ofdm_9565()
443 mask_index = mask_index - 1; in ar9003_hw_spur_ofdm_9565()
447 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
452 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B(ah), in ar9003_hw_spur_ofdm_9565()
456 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
459 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
461 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
465 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B(ah), in ar9003_hw_spur_ofdm_9565()
469 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, in ar9003_hw_spur_ofdm_work() argument
481 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_ofdm_work()
490 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_ofdm_work()
496 spur_freq_sd = ((freq_offset - 10) << 9) / 11; in ar9003_hw_spur_ofdm_work()
500 spur_delta_phase = (freq_offset << 17) / 5; in ar9003_hw_spur_ofdm_work()
505 spur_delta_phase = (freq_offset << 18) / 5; in ar9003_hw_spur_ofdm_work()
511 ar9003_hw_spur_ofdm(ah, in ar9003_hw_spur_ofdm_work()
520 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, in ar9003_hw_spur_mitigate_ofdm() argument
526 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan)); in ar9003_hw_spur_mitigate_ofdm()
534 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_mitigate_ofdm()
536 synth_freq = chan->channel - 10; in ar9003_hw_spur_mitigate_ofdm()
538 synth_freq = chan->channel + 10; in ar9003_hw_spur_mitigate_ofdm()
541 synth_freq = chan->channel; in ar9003_hw_spur_mitigate_ofdm()
544 ar9003_hw_spur_ofdm_clear(ah); in ar9003_hw_spur_mitigate_ofdm()
549 freq_offset -= synth_freq; in ar9003_hw_spur_mitigate_ofdm()
551 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset, in ar9003_hw_spur_mitigate_ofdm()
554 if (AR_SREV_9565(ah) && (i < 4)) { in ar9003_hw_spur_mitigate_ofdm()
558 freq_offset -= synth_freq; in ar9003_hw_spur_mitigate_ofdm()
560 ar9003_hw_spur_ofdm_9565(ah, freq_offset); in ar9003_hw_spur_mitigate_ofdm()
568 static void ar9003_hw_spur_mitigate(struct ath_hw *ah, in ar9003_hw_spur_mitigate() argument
571 if (!AR_SREV_9565(ah)) in ar9003_hw_spur_mitigate()
572 ar9003_hw_spur_mitigate_mrc_cck(ah, chan); in ar9003_hw_spur_mitigate()
573 ar9003_hw_spur_mitigate_ofdm(ah, chan); in ar9003_hw_spur_mitigate()
576 static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah, in ar9003_hw_compute_pll_control_soc() argument
593 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, in ar9003_hw_compute_pll_control() argument
610 static void ar9003_hw_set_channel_regs(struct ath_hw *ah, in ar9003_hw_set_channel_regs() argument
617 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); in ar9003_hw_set_channel_regs()
622 if (!AR_SREV_9561(ah)) in ar9003_hw_set_channel_regs()
628 /* Configure control (primary) channel at +-10MHz */ in ar9003_hw_set_channel_regs()
635 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); in ar9003_hw_set_channel_regs()
639 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); in ar9003_hw_set_channel_regs()
642 ath9k_hw_set11nmac2040(ah, chan); in ar9003_hw_set_channel_regs()
645 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
647 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
650 static void ar9003_hw_init_bb(struct ath_hw *ah, in ar9003_hw_init_bb() argument
660 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_init_bb()
663 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_init_bb()
664 ath9k_hw_synth_delay(ah, chan, synthDelay); in ar9003_hw_init_bb()
667 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) in ar9003_hw_set_chain_masks() argument
669 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5) in ar9003_hw_set_chain_masks()
670 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar9003_hw_set_chain_masks()
673 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); in ar9003_hw_set_chain_masks()
674 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); in ar9003_hw_set_chain_masks()
676 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) in ar9003_hw_set_chain_masks()
679 REG_WRITE(ah, AR_SELFGEN_MASK, tx); in ar9003_hw_set_chain_masks()
685 static void ar9003_hw_override_ini(struct ath_hw *ah) in ar9003_hw_override_ini() argument
694 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar9003_hw_override_ini()
703 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); in ar9003_hw_override_ini()
707 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); in ar9003_hw_override_ini()
709 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ar9003_hw_override_ini()
710 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE, in ar9003_hw_override_ini()
713 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah), in ar9003_hw_override_ini()
715 ah->enabled_cals |= TX_IQ_CAL; in ar9003_hw_override_ini()
717 ah->enabled_cals &= ~TX_IQ_CAL; in ar9003_hw_override_ini()
721 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) in ar9003_hw_override_ini()
722 ah->enabled_cals |= TX_CL_CAL; in ar9003_hw_override_ini()
724 ah->enabled_cals &= ~TX_CL_CAL; in ar9003_hw_override_ini()
726 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah) || in ar9003_hw_override_ini()
727 AR_SREV_9561(ah)) { in ar9003_hw_override_ini()
728 if (ah->is_clk_25mhz) { in ar9003_hw_override_ini()
729 REG_WRITE(ah, AR_RTC_DERIVED_CLK(ah), 0x17c << 1); in ar9003_hw_override_ini()
730 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); in ar9003_hw_override_ini()
731 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); in ar9003_hw_override_ini()
733 REG_WRITE(ah, AR_RTC_DERIVED_CLK(ah), 0x261 << 1); in ar9003_hw_override_ini()
734 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); in ar9003_hw_override_ini()
735 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); in ar9003_hw_override_ini()
741 static void ar9003_hw_prog_ini(struct ath_hw *ah, in ar9003_hw_prog_ini() argument
748 if (!iniArr->ia_array) in ar9003_hw_prog_ini()
753 * may be modal (> 2 columns) or non-modal (2 columns). Determine if in ar9003_hw_prog_ini()
754 * the array is non-modal and force the column to 1. in ar9003_hw_prog_ini()
756 if (column >= iniArr->ia_columns) in ar9003_hw_prog_ini()
759 for (i = 0; i < iniArr->ia_rows; i++) { in ar9003_hw_prog_ini()
760 u32 reg = INI_RA(iniArr, i, 0); in ar9003_hw_prog_ini() local
763 REG_WRITE(ah, reg, val); in ar9003_hw_prog_ini()
769 static u32 ar9550_hw_get_modes_txgain_index(struct ath_hw *ah, in ar9550_hw_get_modes_txgain_index() argument
781 if (chan->channel <= 5350) in ar9550_hw_get_modes_txgain_index()
783 else if ((chan->channel > 5350) && (chan->channel <= 5600)) in ar9550_hw_get_modes_txgain_index()
786 ret = 5; in ar9550_hw_get_modes_txgain_index()
794 static u32 ar9561_hw_get_modes_txgain_index(struct ath_hw *ah, in ar9561_hw_get_modes_txgain_index() argument
807 static void ar9003_doubler_fix(struct ath_hw *ah) in ar9003_doubler_fix() argument
809 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) { in ar9003_doubler_fix()
810 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
813 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
816 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
822 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
824 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
826 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
831 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
833 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
835 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
840 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12, in ar9003_doubler_fix()
843 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0, in ar9003_doubler_fix()
846 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0, in ar9003_doubler_fix()
849 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0, in ar9003_doubler_fix()
855 static int ar9003_hw_process_ini(struct ath_hw *ah, in ar9003_hw_process_ini() argument
870 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); in ar9003_hw_process_ini()
871 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); in ar9003_hw_process_ini()
872 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); in ar9003_hw_process_ini()
873 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); in ar9003_hw_process_ini()
874 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah)) in ar9003_hw_process_ini()
875 ar9003_hw_prog_ini(ah, in ar9003_hw_process_ini()
876 &ah->ini_radio_post_sys2ant, in ar9003_hw_process_ini()
880 ar9003_doubler_fix(ah); in ar9003_hw_process_ini()
885 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); in ar9003_hw_process_ini()
887 if (AR_SREV_9462_20_OR_LATER(ah)) { in ar9003_hw_process_ini()
891 if (ar9003_hw_get_rx_gain_idx(ah) == 2) { in ar9003_hw_process_ini()
892 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, in ar9003_hw_process_ini()
894 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, in ar9003_hw_process_ini()
899 * 5G-XLNA in ar9003_hw_process_ini()
901 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) || in ar9003_hw_process_ini()
902 (ar9003_hw_get_rx_gain_idx(ah) == 3)) { in ar9003_hw_process_ini()
903 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna, in ar9003_hw_process_ini()
908 if (AR_SREV_9550(ah) || AR_SREV_9561(ah)) in ar9003_hw_process_ini()
909 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex, in ar9003_hw_process_ini()
912 if (AR_SREV_9561(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0)) in ar9003_hw_process_ini()
913 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna, in ar9003_hw_process_ini()
918 if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ar9003_hw_process_ini()
921 if (AR_SREV_9550(ah)) in ar9003_hw_process_ini()
922 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan); in ar9003_hw_process_ini()
924 if (AR_SREV_9561(ah)) in ar9003_hw_process_ini()
926 ar9561_hw_get_modes_txgain_index(ah, chan); in ar9003_hw_process_ini()
928 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index, in ar9003_hw_process_ini()
931 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); in ar9003_hw_process_ini()
935 * For 5GHz channels requiring Fast Clock, apply in ar9003_hw_process_ini()
938 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar9003_hw_process_ini()
939 REG_WRITE_ARRAY(&ah->iniModesFastClock, in ar9003_hw_process_ini()
945 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites); in ar9003_hw_process_ini()
950 if (chan->channel == 2484) { in ar9003_hw_process_ini()
951 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); in ar9003_hw_process_ini()
953 if (AR_SREV_9531(ah)) in ar9003_hw_process_ini()
954 REG_RMW_FIELD(ah, AR_PHY_FCAL_2_0, in ar9003_hw_process_ini()
958 ah->modes_index = modesIndex; in ar9003_hw_process_ini()
959 ar9003_hw_override_ini(ah); in ar9003_hw_process_ini()
960 ar9003_hw_set_channel_regs(ah, chan); in ar9003_hw_process_ini()
961 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); in ar9003_hw_process_ini()
962 ath9k_hw_apply_txpower(ah, chan, false); in ar9003_hw_process_ini()
967 static void ar9003_hw_set_rfmode(struct ath_hw *ah, in ar9003_hw_set_rfmode() argument
980 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar9003_hw_set_rfmode()
984 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, in ar9003_hw_set_rfmode()
987 REG_WRITE(ah, AR_PHY_MODE, rfMode); in ar9003_hw_set_rfmode()
990 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) in ar9003_hw_mark_phy_inactive() argument
992 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); in ar9003_hw_mark_phy_inactive()
995 static void ar9003_hw_set_delta_slope(struct ath_hw *ah, in ar9003_hw_set_delta_slope() argument
1012 * ALGO -> coef = 1e8/fcarrier*fclock/40; in ar9003_hw_set_delta_slope()
1015 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar9003_hw_set_delta_slope()
1018 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar9003_hw_set_delta_slope()
1021 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar9003_hw_set_delta_slope()
1023 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar9003_hw_set_delta_slope()
1032 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar9003_hw_set_delta_slope()
1036 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, in ar9003_hw_set_delta_slope()
1038 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, in ar9003_hw_set_delta_slope()
1042 static bool ar9003_hw_rfbus_req(struct ath_hw *ah) in ar9003_hw_rfbus_req() argument
1044 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); in ar9003_hw_rfbus_req()
1045 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, in ar9003_hw_rfbus_req()
1053 static void ar9003_hw_rfbus_done(struct ath_hw *ah) in ar9003_hw_rfbus_done() argument
1055 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_rfbus_done()
1057 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); in ar9003_hw_rfbus_done()
1059 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); in ar9003_hw_rfbus_done()
1062 static bool ar9003_hw_ani_control(struct ath_hw *ah, in ar9003_hw_ani_control() argument
1065 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_ani_control()
1066 struct ath9k_channel *chan = ah->curchan; in ar9003_hw_ani_control()
1067 struct ar5416AniState *aniState = &ah->ani; in ar9003_hw_ani_control()
1075 switch (cmd & ah->ani_function) { in ar9003_hw_ani_control()
1086 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ar9003_hw_ani_control()
1090 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; in ar9003_hw_ani_control()
1092 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; in ar9003_hw_ani_control()
1094 aniState->iniDef.m1Thresh : m1Thresh_off; in ar9003_hw_ani_control()
1096 aniState->iniDef.m2Thresh : m2Thresh_off; in ar9003_hw_ani_control()
1098 aniState->iniDef.m2CountThr : m2CountThr_off; in ar9003_hw_ani_control()
1100 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; in ar9003_hw_ani_control()
1102 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; in ar9003_hw_ani_control()
1104 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; in ar9003_hw_ani_control()
1106 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; in ar9003_hw_ani_control()
1108 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; in ar9003_hw_ani_control()
1110 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1113 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1116 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar9003_hw_ani_control()
1119 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar9003_hw_ani_control()
1122 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar9003_hw_ani_control()
1125 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1128 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1131 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1134 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1137 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1142 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1145 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1148 if (on != aniState->ofdmWeakSigDetect) { in ar9003_hw_ani_control()
1151 chan->channel, in ar9003_hw_ani_control()
1152 aniState->ofdmWeakSigDetect ? in ar9003_hw_ani_control()
1156 ah->stats.ast_ani_ofdmon++; in ar9003_hw_ani_control()
1158 ah->stats.ast_ani_ofdmoff++; in ar9003_hw_ani_control()
1159 aniState->ofdmWeakSigDetect = on; in ar9003_hw_ani_control()
1177 value = firstep_table[level] - in ar9003_hw_ani_control()
1179 aniState->iniDef.firstep; in ar9003_hw_ani_control()
1184 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, in ar9003_hw_ani_control()
1192 value2 = firstep_table[level] - in ar9003_hw_ani_control()
1194 aniState->iniDef.firstepLow; in ar9003_hw_ani_control()
1200 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, in ar9003_hw_ani_control()
1203 if (level != aniState->firstepLevel) { in ar9003_hw_ani_control()
1206 chan->channel, in ar9003_hw_ani_control()
1207 aniState->firstepLevel, in ar9003_hw_ani_control()
1211 aniState->iniDef.firstep); in ar9003_hw_ani_control()
1214 chan->channel, in ar9003_hw_ani_control()
1215 aniState->firstepLevel, in ar9003_hw_ani_control()
1219 aniState->iniDef.firstepLow); in ar9003_hw_ani_control()
1220 if (level > aniState->firstepLevel) in ar9003_hw_ani_control()
1221 ah->stats.ast_ani_stepup++; in ar9003_hw_ani_control()
1222 else if (level < aniState->firstepLevel) in ar9003_hw_ani_control()
1223 ah->stats.ast_ani_stepdown++; in ar9003_hw_ani_control()
1224 aniState->firstepLevel = level; in ar9003_hw_ani_control()
1241 value = cycpwrThr1_table[level] - in ar9003_hw_ani_control()
1243 aniState->iniDef.cycpwrThr1; in ar9003_hw_ani_control()
1248 REG_RMW_FIELD(ah, AR_PHY_TIMING5, in ar9003_hw_ani_control()
1257 value2 = cycpwrThr1_table[level] - in ar9003_hw_ani_control()
1259 aniState->iniDef.cycpwrThr1Ext; in ar9003_hw_ani_control()
1264 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, in ar9003_hw_ani_control()
1267 if (level != aniState->spurImmunityLevel) { in ar9003_hw_ani_control()
1270 chan->channel, in ar9003_hw_ani_control()
1271 aniState->spurImmunityLevel, in ar9003_hw_ani_control()
1275 aniState->iniDef.cycpwrThr1); in ar9003_hw_ani_control()
1278 chan->channel, in ar9003_hw_ani_control()
1279 aniState->spurImmunityLevel, in ar9003_hw_ani_control()
1283 aniState->iniDef.cycpwrThr1Ext); in ar9003_hw_ani_control()
1284 if (level > aniState->spurImmunityLevel) in ar9003_hw_ani_control()
1285 ah->stats.ast_ani_spurup++; in ar9003_hw_ani_control()
1286 else if (level < aniState->spurImmunityLevel) in ar9003_hw_ani_control()
1287 ah->stats.ast_ani_spurdown++; in ar9003_hw_ani_control()
1288 aniState->spurImmunityLevel = level; in ar9003_hw_ani_control()
1299 if (ah->caps.rx_chainmask == 1) in ar9003_hw_ani_control()
1302 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, in ar9003_hw_ani_control()
1304 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, in ar9003_hw_ani_control()
1306 if (is_on != aniState->mrcCCK) { in ar9003_hw_ani_control()
1308 chan->channel, in ar9003_hw_ani_control()
1309 aniState->mrcCCK ? "on" : "off", in ar9003_hw_ani_control()
1312 ah->stats.ast_ani_ccklow++; in ar9003_hw_ani_control()
1314 ah->stats.ast_ani_cckhigh++; in ar9003_hw_ani_control()
1315 aniState->mrcCCK = is_on; in ar9003_hw_ani_control()
1326 aniState->spurImmunityLevel, in ar9003_hw_ani_control()
1327 aniState->ofdmWeakSigDetect ? "on" : "off", in ar9003_hw_ani_control()
1328 aniState->firstepLevel, in ar9003_hw_ani_control()
1329 aniState->mrcCCK ? "on" : "off", in ar9003_hw_ani_control()
1330 aniState->listenTime, in ar9003_hw_ani_control()
1331 aniState->ofdmPhyErrCount, in ar9003_hw_ani_control()
1332 aniState->cckPhyErrCount); in ar9003_hw_ani_control()
1336 static void ar9003_hw_do_getnf(struct ath_hw *ah, in ar9003_hw_do_getnf() argument
1348 if (ah->rxchainmask & BIT(i)) { in ar9003_hw_do_getnf()
1349 nf = MS(REG_READ(ah, ah->nf_regs[i]), in ar9003_hw_do_getnf()
1353 if (IS_CHAN_HT40(ah->curchan)) { in ar9003_hw_do_getnf()
1356 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), in ar9003_hw_do_getnf()
1364 static void ar9003_hw_set_nf_limits(struct ath_hw *ah) in ar9003_hw_set_nf_limits() argument
1366 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1367 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1368 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1369 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1370 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1371 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1373 if (AR_SREV_9330(ah)) in ar9003_hw_set_nf_limits()
1374 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; in ar9003_hw_set_nf_limits()
1376 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ar9003_hw_set_nf_limits()
1377 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ; in ar9003_hw_set_nf_limits()
1378 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ; in ar9003_hw_set_nf_limits()
1379 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ; in ar9003_hw_set_nf_limits()
1380 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ; in ar9003_hw_set_nf_limits()
1389 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) in ar9003_hw_ani_cache_ini_regs() argument
1392 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_ani_cache_ini_regs()
1393 struct ath9k_channel *chan = ah->curchan; in ar9003_hw_ani_cache_ini_regs()
1397 aniState = &ah->ani; in ar9003_hw_ani_cache_ini_regs()
1398 iniDef = &aniState->iniDef; in ar9003_hw_ani_cache_ini_regs()
1401 ah->hw_version.macVersion, in ar9003_hw_ani_cache_ini_regs()
1402 ah->hw_version.macRev, in ar9003_hw_ani_cache_ini_regs()
1403 ah->opmode, in ar9003_hw_ani_cache_ini_regs()
1404 chan->channel); in ar9003_hw_ani_cache_ini_regs()
1406 val = REG_READ(ah, AR_PHY_SFCORR); in ar9003_hw_ani_cache_ini_regs()
1407 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); in ar9003_hw_ani_cache_ini_regs()
1408 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); in ar9003_hw_ani_cache_ini_regs()
1409 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); in ar9003_hw_ani_cache_ini_regs()
1411 val = REG_READ(ah, AR_PHY_SFCORR_LOW); in ar9003_hw_ani_cache_ini_regs()
1412 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); in ar9003_hw_ani_cache_ini_regs()
1413 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); in ar9003_hw_ani_cache_ini_regs()
1414 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); in ar9003_hw_ani_cache_ini_regs()
1416 val = REG_READ(ah, AR_PHY_SFCORR_EXT); in ar9003_hw_ani_cache_ini_regs()
1417 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); in ar9003_hw_ani_cache_ini_regs()
1418 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); in ar9003_hw_ani_cache_ini_regs()
1419 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); in ar9003_hw_ani_cache_ini_regs()
1420 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); in ar9003_hw_ani_cache_ini_regs()
1421 iniDef->firstep = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1424 iniDef->firstepLow = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1427 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1430 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1435 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; in ar9003_hw_ani_cache_ini_regs()
1436 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; in ar9003_hw_ani_cache_ini_regs()
1437 aniState->ofdmWeakSigDetect = true; in ar9003_hw_ani_cache_ini_regs()
1438 aniState->mrcCCK = true; in ar9003_hw_ani_cache_ini_regs()
1441 static void ar9003_hw_set_radar_params(struct ath_hw *ah, in ar9003_hw_set_radar_params() argument
1448 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); in ar9003_hw_set_radar_params()
1453 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); in ar9003_hw_set_radar_params()
1454 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); in ar9003_hw_set_radar_params()
1455 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); in ar9003_hw_set_radar_params()
1456 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); in ar9003_hw_set_radar_params()
1457 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); in ar9003_hw_set_radar_params()
1459 radar_1 = REG_READ(ah, AR_PHY_RADAR_1); in ar9003_hw_set_radar_params()
1464 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); in ar9003_hw_set_radar_params()
1465 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); in ar9003_hw_set_radar_params()
1466 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); in ar9003_hw_set_radar_params()
1468 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); in ar9003_hw_set_radar_params()
1469 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); in ar9003_hw_set_radar_params()
1470 if (conf->ext_channel) in ar9003_hw_set_radar_params()
1471 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params()
1473 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params()
1475 if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) { in ar9003_hw_set_radar_params()
1476 REG_WRITE_ARRAY(&ah->ini_dfs, in ar9003_hw_set_radar_params()
1477 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites); in ar9003_hw_set_radar_params()
1481 static void ar9003_hw_set_radar_conf(struct ath_hw *ah) in ar9003_hw_set_radar_conf() argument
1483 struct ath_hw_radar_conf *conf = &ah->radar_conf; in ar9003_hw_set_radar_conf()
1485 conf->fir_power = -28; in ar9003_hw_set_radar_conf()
1486 conf->radar_rssi = 0; in ar9003_hw_set_radar_conf()
1487 conf->pulse_height = 10; in ar9003_hw_set_radar_conf()
1488 conf->pulse_rssi = 15; in ar9003_hw_set_radar_conf()
1489 conf->pulse_inband = 8; in ar9003_hw_set_radar_conf()
1490 conf->pulse_maxlen = 255; in ar9003_hw_set_radar_conf()
1491 conf->pulse_inband_step = 12; in ar9003_hw_set_radar_conf()
1492 conf->radar_inband = 8; in ar9003_hw_set_radar_conf()
1495 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, in ar9003_hw_antdiv_comb_conf_get() argument
1500 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_antdiv_comb_conf_get()
1501 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >> in ar9003_hw_antdiv_comb_conf_get()
1503 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >> in ar9003_hw_antdiv_comb_conf_get()
1505 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >> in ar9003_hw_antdiv_comb_conf_get()
1508 if (AR_SREV_9330_11(ah)) { in ar9003_hw_antdiv_comb_conf_get()
1509 antconf->lna1_lna2_switch_delta = -1; in ar9003_hw_antdiv_comb_conf_get()
1510 antconf->lna1_lna2_delta = -9; in ar9003_hw_antdiv_comb_conf_get()
1511 antconf->div_group = 1; in ar9003_hw_antdiv_comb_conf_get()
1512 } else if (AR_SREV_9485(ah)) { in ar9003_hw_antdiv_comb_conf_get()
1513 antconf->lna1_lna2_switch_delta = -1; in ar9003_hw_antdiv_comb_conf_get()
1514 antconf->lna1_lna2_delta = -9; in ar9003_hw_antdiv_comb_conf_get()
1515 antconf->div_group = 2; in ar9003_hw_antdiv_comb_conf_get()
1516 } else if (AR_SREV_9565(ah)) { in ar9003_hw_antdiv_comb_conf_get()
1517 antconf->lna1_lna2_switch_delta = 3; in ar9003_hw_antdiv_comb_conf_get()
1518 antconf->lna1_lna2_delta = -9; in ar9003_hw_antdiv_comb_conf_get()
1519 antconf->div_group = 3; in ar9003_hw_antdiv_comb_conf_get()
1521 antconf->lna1_lna2_switch_delta = -1; in ar9003_hw_antdiv_comb_conf_get()
1522 antconf->lna1_lna2_delta = -3; in ar9003_hw_antdiv_comb_conf_get()
1523 antconf->div_group = 0; in ar9003_hw_antdiv_comb_conf_get()
1527 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, in ar9003_hw_antdiv_comb_conf_set() argument
1532 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_antdiv_comb_conf_set()
1538 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S) in ar9003_hw_antdiv_comb_conf_set()
1540 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S) in ar9003_hw_antdiv_comb_conf_set()
1542 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S) in ar9003_hw_antdiv_comb_conf_set()
1544 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S) in ar9003_hw_antdiv_comb_conf_set()
1546 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S) in ar9003_hw_antdiv_comb_conf_set()
1549 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_antdiv_comb_conf_set()
1554 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable) in ar9003_hw_set_bt_ant_diversity() argument
1556 struct ath9k_hw_capabilities *pCap = &ah->caps; in ar9003_hw_set_bt_ant_diversity()
1560 if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah)) in ar9003_hw_set_bt_ant_diversity()
1563 if (AR_SREV_9485(ah)) { in ar9003_hw_set_bt_ant_diversity()
1564 regval = ar9003_hw_ant_ctrl_common_2_get(ah, in ar9003_hw_set_bt_ant_diversity()
1565 IS_CHAN_2GHZ(ah->curchan)); in ar9003_hw_set_bt_ant_diversity()
1568 regval |= ah->config.ant_ctrl_comm2g_switch_enable; in ar9003_hw_set_bt_ant_diversity()
1570 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, in ar9003_hw_set_bt_ant_diversity()
1574 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ar9003_hw_set_bt_ant_diversity()
1580 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1583 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1585 if (AR_SREV_9485_11_OR_LATER(ah)) { in ar9003_hw_set_bt_ant_diversity()
1589 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1595 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1600 regval = REG_READ(ah, AR_PHY_CCK_DETECT); in ar9003_hw_set_bt_ant_diversity()
1606 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); in ar9003_hw_set_bt_ant_diversity()
1608 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { in ar9003_hw_set_bt_ant_diversity()
1609 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1622 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1624 } else if (AR_SREV_9565(ah)) { in ar9003_hw_set_bt_ant_diversity()
1626 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1628 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1630 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, in ar9003_hw_set_bt_ant_diversity()
1632 REG_SET_BIT(ah, AR_PHY_RESTART, in ar9003_hw_set_bt_ant_diversity()
1634 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_set_bt_ant_diversity()
1637 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1639 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1641 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, in ar9003_hw_set_bt_ant_diversity()
1643 REG_CLR_BIT(ah, AR_PHY_RESTART, in ar9003_hw_set_bt_ant_diversity()
1645 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_set_bt_ant_diversity()
1648 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1657 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1664 static int ar9003_hw_fast_chan_change(struct ath_hw *ah, in ar9003_hw_fast_chan_change() argument
1676 txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex; in ar9003_hw_fast_chan_change()
1678 if (modesIndex == ah->modes_index) { in ar9003_hw_fast_chan_change()
1683 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1684 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1685 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1686 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1688 if (AR_SREV_9462_20_OR_LATER(ah)) in ar9003_hw_fast_chan_change()
1689 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant, in ar9003_hw_fast_chan_change()
1692 REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites); in ar9003_hw_fast_chan_change()
1694 if (AR_SREV_9462_20_OR_LATER(ah)) { in ar9003_hw_fast_chan_change()
1698 if (ar9003_hw_get_rx_gain_idx(ah) == 2) { in ar9003_hw_fast_chan_change()
1699 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, in ar9003_hw_fast_chan_change()
1701 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, in ar9003_hw_fast_chan_change()
1707 * For 5GHz channels requiring Fast Clock, apply in ar9003_hw_fast_chan_change()
1710 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar9003_hw_fast_chan_change()
1711 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites); in ar9003_hw_fast_chan_change()
1713 if (AR_SREV_9565(ah)) in ar9003_hw_fast_chan_change()
1714 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites); in ar9003_hw_fast_chan_change()
1719 if (chan->channel == 2484) in ar9003_hw_fast_chan_change()
1720 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); in ar9003_hw_fast_chan_change()
1722 ah->modes_index = modesIndex; in ar9003_hw_fast_chan_change()
1726 ar9003_hw_set_rfmode(ah, chan); in ar9003_hw_fast_chan_change()
1730 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah, in ar9003_hw_spectral_scan_config() argument
1735 if (!param->enabled) { in ar9003_hw_spectral_scan_config()
1736 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1741 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); in ar9003_hw_spectral_scan_config()
1742 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); in ar9003_hw_spectral_scan_config()
1748 count = param->count; in ar9003_hw_spectral_scan_config()
1749 if (param->endless) in ar9003_hw_spectral_scan_config()
1751 else if (param->count == 0) in ar9003_hw_spectral_scan_config()
1754 if (param->short_repeat) in ar9003_hw_spectral_scan_config()
1755 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1758 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1761 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1763 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1764 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period); in ar9003_hw_spectral_scan_config()
1765 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1766 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period); in ar9003_hw_spectral_scan_config()
1771 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah) in ar9003_hw_spectral_scan_trigger() argument
1773 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_trigger()
1776 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_trigger()
1780 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah) in ar9003_hw_spectral_scan_wait() argument
1782 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_spectral_scan_wait()
1785 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_wait()
1793 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum) in ar9003_hw_tx99_start() argument
1795 REG_SET_BIT(ah, AR_PHY_TEST(ah), PHY_AGC_CLR); in ar9003_hw_tx99_start()
1796 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9003_hw_tx99_start()
1797 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ar9003_hw_tx99_start()
1798 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); in ar9003_hw_tx99_start()
1799 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ in ar9003_hw_tx99_start()
1800 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); in ar9003_hw_tx99_start()
1801 REG_WRITE(ah, AR_TIME_OUT, 0x00000400); in ar9003_hw_tx99_start()
1802 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); in ar9003_hw_tx99_start()
1803 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ); in ar9003_hw_tx99_start()
1806 static void ar9003_hw_tx99_stop(struct ath_hw *ah) in ar9003_hw_tx99_stop() argument
1808 REG_CLR_BIT(ah, AR_PHY_TEST(ah), PHY_AGC_CLR); in ar9003_hw_tx99_stop()
1809 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9003_hw_tx99_stop()
1812 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower) in ar9003_hw_tx99_set_txpower() argument
1821 ar9003_hw_tx_power_regwrite(ah, p_pwr_array); in ar9003_hw_tx99_set_txpower()
1824 static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array) in ar9003_hw_init_txpower_cck() argument
1826 ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L]; in ar9003_hw_init_txpower_cck()
1827 ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L]; in ar9003_hw_init_txpower_cck()
1828 ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L], in ar9003_hw_init_txpower_cck()
1830 ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L], in ar9003_hw_init_txpower_cck()
1834 static void ar9003_hw_init_txpower_ofdm(struct ath_hw *ah, u8 *rate_array, in ar9003_hw_init_txpower_ofdm() argument
1841 j = ofdm2pwr[i - offset]; in ar9003_hw_init_txpower_ofdm()
1842 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ofdm()
1846 static void ar9003_hw_init_txpower_ht(struct ath_hw *ah, u8 *rate_array, in ar9003_hw_init_txpower_ht() argument
1855 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1861 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1867 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1872 static void ar9003_hw_init_txpower_stbc(struct ath_hw *ah, int ss_offset, in ar9003_hw_init_txpower_stbc() argument
1875 memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset], in ar9003_hw_init_txpower_stbc()
1877 memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset], in ar9003_hw_init_txpower_stbc()
1879 memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset], in ar9003_hw_init_txpower_stbc()
1883 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array, in ar9003_hw_init_rate_txpower() argument
1887 ar9003_hw_init_txpower_ofdm(ah, rate_array, in ar9003_hw_init_rate_txpower()
1890 ar9003_hw_init_txpower_ht(ah, rate_array, in ar9003_hw_init_rate_txpower()
1895 ar9003_hw_init_txpower_stbc(ah, in ar9003_hw_init_rate_txpower()
1901 ar9003_hw_init_txpower_cck(ah, rate_array); in ar9003_hw_init_rate_txpower()
1902 ar9003_hw_init_txpower_ofdm(ah, rate_array, in ar9003_hw_init_rate_txpower()
1905 ar9003_hw_init_txpower_ht(ah, rate_array, in ar9003_hw_init_rate_txpower()
1910 ar9003_hw_init_txpower_stbc(ah, in ar9003_hw_init_rate_txpower()
1918 void ar9003_hw_attach_phy_ops(struct ath_hw *ah) in ar9003_hw_attach_phy_ops() argument
1920 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar9003_hw_attach_phy_ops()
1921 struct ath_hw_ops *ops = ath9k_hw_ops(ah); in ar9003_hw_attach_phy_ops()
1931 priv_ops->rf_set_freq = ar9003_hw_set_channel; in ar9003_hw_attach_phy_ops()
1932 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; in ar9003_hw_attach_phy_ops()
1934 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ar9003_hw_attach_phy_ops()
1935 AR_SREV_9561(ah)) in ar9003_hw_attach_phy_ops()
1936 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc; in ar9003_hw_attach_phy_ops()
1938 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; in ar9003_hw_attach_phy_ops()
1940 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs; in ar9003_hw_attach_phy_ops()
1941 priv_ops->init_bb = ar9003_hw_init_bb; in ar9003_hw_attach_phy_ops()
1942 priv_ops->process_ini = ar9003_hw_process_ini; in ar9003_hw_attach_phy_ops()
1943 priv_ops->set_rfmode = ar9003_hw_set_rfmode; in ar9003_hw_attach_phy_ops()
1944 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive; in ar9003_hw_attach_phy_ops()
1945 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope; in ar9003_hw_attach_phy_ops()
1946 priv_ops->rfbus_req = ar9003_hw_rfbus_req; in ar9003_hw_attach_phy_ops()
1947 priv_ops->rfbus_done = ar9003_hw_rfbus_done; in ar9003_hw_attach_phy_ops()
1948 priv_ops->ani_control = ar9003_hw_ani_control; in ar9003_hw_attach_phy_ops()
1949 priv_ops->do_getnf = ar9003_hw_do_getnf; in ar9003_hw_attach_phy_ops()
1950 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs; in ar9003_hw_attach_phy_ops()
1951 priv_ops->set_radar_params = ar9003_hw_set_radar_params; in ar9003_hw_attach_phy_ops()
1952 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change; in ar9003_hw_attach_phy_ops()
1954 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get; in ar9003_hw_attach_phy_ops()
1955 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set; in ar9003_hw_attach_phy_ops()
1956 ops->spectral_scan_config = ar9003_hw_spectral_scan_config; in ar9003_hw_attach_phy_ops()
1957 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger; in ar9003_hw_attach_phy_ops()
1958 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait; in ar9003_hw_attach_phy_ops()
1961 ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity; in ar9003_hw_attach_phy_ops()
1963 ops->tx99_start = ar9003_hw_tx99_start; in ar9003_hw_attach_phy_ops()
1964 ops->tx99_stop = ar9003_hw_tx99_stop; in ar9003_hw_attach_phy_ops()
1965 ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower; in ar9003_hw_attach_phy_ops()
1967 ar9003_hw_set_nf_limits(ah); in ar9003_hw_attach_phy_ops()
1968 ar9003_hw_set_radar_conf(ah); in ar9003_hw_attach_phy_ops()
1969 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs)); in ar9003_hw_attach_phy_ops()
1998 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah) in ar9003_hw_bb_watchdog_check() argument
2002 switch(ah->bb_watchdog_last_status) { in ar9003_hw_bb_watchdog_check()
2004 val = REG_READ(ah, AR_PHY_RADAR_0); in ar9003_hw_bb_watchdog_check()
2007 REG_WRITE(ah, AR_PHY_RADAR_0, val); in ar9003_hw_bb_watchdog_check()
2009 val = REG_READ(ah, AR_PHY_RADAR_0); in ar9003_hw_bb_watchdog_check()
2012 REG_WRITE(ah, AR_PHY_RADAR_0, val); in ar9003_hw_bb_watchdog_check()
2021 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) in ar9003_hw_bb_watchdog_check()
2035 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) in ar9003_hw_bb_watchdog_config() argument
2037 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_bb_watchdog_config()
2038 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms; in ar9003_hw_bb_watchdog_config()
2042 /* disable IRQ, disable chip-reset for BB panic */ in ar9003_hw_bb_watchdog_config()
2043 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, in ar9003_hw_bb_watchdog_config()
2044 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & in ar9003_hw_bb_watchdog_config()
2048 /* disable watchdog in non-IDLE mode, disable in IDLE mode */ in ar9003_hw_bb_watchdog_config()
2049 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, in ar9003_hw_bb_watchdog_config()
2050 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) & in ar9003_hw_bb_watchdog_config()
2058 /* enable IRQ, disable chip-reset for BB watchdog */ in ar9003_hw_bb_watchdog_config()
2059 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK; in ar9003_hw_bb_watchdog_config()
2060 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, in ar9003_hw_bb_watchdog_config()
2074 * Given we use fast clock now in 5 GHz, these time units should in ar9003_hw_bb_watchdog_config()
2075 * be common for both 2 GHz and 5 GHz. in ar9003_hw_bb_watchdog_config()
2078 if (ah->curchan && IS_CHAN_HT40(ah->curchan)) in ar9003_hw_bb_watchdog_config()
2082 * enable watchdog in non-IDLE mode, disable in IDLE mode, in ar9003_hw_bb_watchdog_config()
2083 * set idle time-out. in ar9003_hw_bb_watchdog_config()
2085 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, in ar9003_hw_bb_watchdog_config()
2094 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) in ar9003_hw_bb_watchdog_read() argument
2100 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); in ar9003_hw_bb_watchdog_read()
2106 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS, in ar9003_hw_bb_watchdog_read()
2107 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR); in ar9003_hw_bb_watchdog_read()
2110 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) in ar9003_hw_bb_watchdog_dbg_info() argument
2112 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_bb_watchdog_dbg_info()
2115 if (likely(!(common->debug_mask & ATH_DBG_RESET))) in ar9003_hw_bb_watchdog_dbg_info()
2118 status = ah->bb_watchdog_last_status; in ar9003_hw_bb_watchdog_dbg_info()
2134 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), in ar9003_hw_bb_watchdog_dbg_info()
2135 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); in ar9003_hw_bb_watchdog_dbg_info()
2137 REG_READ(ah, AR_PHY_GEN_CTRL)); in ar9003_hw_bb_watchdog_dbg_info()
2139 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles) in ar9003_hw_bb_watchdog_dbg_info()
2140 if (common->cc_survey.cycles) in ar9003_hw_bb_watchdog_dbg_info()
2149 void ar9003_hw_disable_phy_restart(struct ath_hw *ah) in ar9003_hw_disable_phy_restart() argument
2159 result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM); in ar9003_hw_disable_phy_restart()
2161 if ((result == 0xb) || ah->bb_hang_rx_ofdm) { in ar9003_hw_disable_phy_restart()
2162 ah->bb_hang_rx_ofdm = true; in ar9003_hw_disable_phy_restart()
2163 val = REG_READ(ah, AR_PHY_RESTART); in ar9003_hw_disable_phy_restart()
2165 REG_WRITE(ah, AR_PHY_RESTART, val); in ar9003_hw_disable_phy_restart()