Lines Matching +full:reg +full:- +full:5 +full:ah
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
36 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
37 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
49 .macAddr = {0, 2, 3, 4, 5, 6},
62 .deviceType = 5, /* takes lower byte in eeprom location */
67 * bit0 - enable tx temp comp - disabled
68 * bit1 - enable tx volt comp - disabled
69 * bit2 - enable fastClock - enabled
70 * bit3 - enable doubling - enabled
71 * bit4 - enable internal regulator - disabled
72 * bit5 - enable pa predistortion - disabled
74 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
97 * for ar9280 (0xa20c/b20c 5:0)
119 .noiseFloorThreshCh = {-1, 0, 0},
128 .adcDesiredSize = -30,
177 /* 1L-5L,5S,11L,11S */
182 /* 6-24,36,48,54 */
236 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
237 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
238 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
309 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
322 .noiseFloorThreshCh = {-1, 0, 0},
331 .adcDesiredSize = -30,
426 /* 6-24,36,48,54 */
438 * 0_8_16,1-3_9-11_17-19,
439 * 4,5,6,7,12,13,14,15,20,21,22,23
452 * 0_8_16,1-3_9-11_17-19,
453 * 4,5,6,7,12,13,14,15,20,21,22,23
475 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
485 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
496 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
507 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
518 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
524 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
525 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
526 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
527 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
528 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
529 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
530 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
531 /* Data[5].ctlEdges[7].bChannel */ 0xFF
540 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
551 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
562 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
629 .custData = {"x113-023-f0000"},
640 .deviceType = 5, /* takes lower byte in eeprom location */
645 * bit0 - enable tx temp comp - disabled
646 * bit1 - enable tx volt comp - disabled
647 * bit2 - enable fastClock - enabled
648 * bit3 - enable doubling - enabled
649 * bit4 - enable internal regulator - disabled
650 * bit5 - enable pa predistortion - disabled
652 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
675 * for ar9280 (0xa20c/b20c 5:0)
697 .noiseFloorThreshCh = {-1, 0, 0},
706 .adcDesiredSize = -30,
755 /* 1L-5L,5S,11L,11S */
760 /* 6-24,36,48,54 */
814 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
815 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
816 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
887 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
900 .noiseFloorThreshCh = {-1, 0, 0},
909 .adcDesiredSize = -30,
1004 /* 6-24,36,48,54 */
1016 * 0_8_16,1-3_9-11_17-19,
1017 * 4,5,6,7,12,13,14,15,20,21,22,23
1030 * 0_8_16,1-3_9-11_17-19,
1031 * 4,5,6,7,12,13,14,15,20,21,22,23
1053 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1063 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1074 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1085 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1096 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1102 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1103 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1104 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1105 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1106 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1107 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1108 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1109 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1118 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1129 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1140 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1208 .custData = {"h112-241-f0000"},
1219 .deviceType = 5, /* takes lower byte in eeprom location */
1224 * bit0 - enable tx temp comp - disabled
1225 * bit1 - enable tx volt comp - disabled
1226 * bit2 - enable fastClock - enabled
1227 * bit3 - enable doubling - enabled
1228 * bit4 - enable internal regulator - disabled
1229 * bit5 - enable pa predistortion - disabled
1231 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1254 * for ar9280 (0xa20c/b20c 5:0)
1276 .noiseFloorThreshCh = {-1, 0, 0},
1285 .adcDesiredSize = -30,
1334 /* 1L-5L,5S,11L,11S */
1339 /* 6-24,36,48,54 */
1393 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1394 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1395 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1466 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1479 .noiseFloorThreshCh = {-1, 0, 0},
1488 .adcDesiredSize = -30,
1583 /* 6-24,36,48,54 */
1595 * 0_8_16,1-3_9-11_17-19,
1596 * 4,5,6,7,12,13,14,15,20,21,22,23
1609 * 0_8_16,1-3_9-11_17-19,
1610 * 4,5,6,7,12,13,14,15,20,21,22,23
1632 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1642 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1653 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1664 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1675 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1681 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1682 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1683 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1684 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1685 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1686 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1687 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1688 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1697 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1708 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1719 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1785 .templateVersion = 5,
1787 .custData = {"x112-041-f0000"},
1798 .deviceType = 5, /* takes lower byte in eeprom location */
1803 * bit0 - enable tx temp comp - disabled
1804 * bit1 - enable tx volt comp - disabled
1805 * bit2 - enable fastclock - enabled
1806 * bit3 - enable doubling - enabled
1807 * bit4 - enable internal regulator - disabled
1808 * bit5 - enable pa predistortion - disabled
1810 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1833 * for ar9280 (0xa20c/b20c 5:0)
1855 .noiseFloorThreshCh = {-1, 0, 0},
1864 .adcDesiredSize = -30,
1913 /* 1L-5L,5S,11L,11s */
1918 /* 6-24,36,48,54 */
1972 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1973 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1974 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2045 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2058 .noiseFloorThreshCh = {-1, 0, 0},
2067 .adcDesiredSize = -30,
2162 /* 6-24,36,48,54 */
2174 * 0_8_16,1-3_9-11_17-19,
2175 * 4,5,6,7,12,13,14,15,20,21,22,23
2188 * 0_8_16,1-3_9-11_17-19,
2189 * 4,5,6,7,12,13,14,15,20,21,22,23
2211 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2221 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2232 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2243 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2254 /* Data[4].ctledges[5].bchannel */ 0xFF,
2260 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2261 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2262 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2263 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2264 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2265 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2266 /* Data[5].ctledges[6].bchannel */ 0xFF,
2267 /* Data[5].ctledges[7].bchannel */ 0xFF
2276 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2287 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2298 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2365 .custData = {"h116-041-f0000"},
2376 .deviceType = 5, /* takes lower byte in eeprom location */
2381 * bit0 - enable tx temp comp - disabled
2382 * bit1 - enable tx volt comp - disabled
2383 * bit2 - enable fastClock - enabled
2384 * bit3 - enable doubling - enabled
2385 * bit4 - enable internal regulator - disabled
2386 * bit5 - enable pa predistortion - disabled
2388 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2411 * for ar9280 (0xa20c/b20c 5:0)
2433 .noiseFloorThreshCh = {-1, 0, 0},
2442 .adcDesiredSize = -30,
2491 /* 1L-5L,5S,11L,11S */
2496 /* 6-24,36,48,54 */
2550 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2551 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2552 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2623 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2636 .noiseFloorThreshCh = {-1, 0, 0},
2645 .adcDesiredSize = -30,
2740 /* 6-24,36,48,54 */
2752 * 0_8_16,1-3_9-11_17-19,
2753 * 4,5,6,7,12,13,14,15,20,21,22,23
2766 * 0_8_16,1-3_9-11_17-19,
2767 * 4,5,6,7,12,13,14,15,20,21,22,23
2789 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2799 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2810 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2821 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2832 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2838 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2839 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2840 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2841 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2842 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2843 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2844 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2845 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2854 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2865 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2876 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2953 if (ar9300_eep_templates[it]->templateVersion == id) in ar9003_eeprom_struct_find_by_id()
2958 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah) in ath9k_hw_ar9300_check_eeprom() argument
2967 bf = 2 * (yb - ya) * (x - xa) / (xb - xa); in interpolate()
2973 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, in ath9k_hw_ar9300_get_eeprom() argument
2976 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ath9k_hw_ar9300_get_eeprom()
2977 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; in ath9k_hw_ar9300_get_eeprom()
2981 return get_unaligned_be16(eep->macAddr); in ath9k_hw_ar9300_get_eeprom()
2983 return get_unaligned_be16(eep->macAddr + 2); in ath9k_hw_ar9300_get_eeprom()
2985 return get_unaligned_be16(eep->macAddr + 4); in ath9k_hw_ar9300_get_eeprom()
2987 return le16_to_cpu(pBase->regDmn[0]); in ath9k_hw_ar9300_get_eeprom()
2989 return pBase->deviceCap; in ath9k_hw_ar9300_get_eeprom()
2991 return pBase->opCapFlags.opFlags; in ath9k_hw_ar9300_get_eeprom()
2993 return pBase->rfSilent; in ath9k_hw_ar9300_get_eeprom()
2995 return (pBase->txrxMask >> 4) & 0xf; in ath9k_hw_ar9300_get_eeprom()
2997 return pBase->txrxMask & 0xf; in ath9k_hw_ar9300_get_eeprom()
2999 return !!(pBase->featureEnable & BIT(5)); in ath9k_hw_ar9300_get_eeprom()
3001 return (pBase->miscConfiguration >> 0x3) & 0x1; in ath9k_hw_ar9300_get_eeprom()
3003 if (AR_SREV_9565(ah)) in ath9k_hw_ar9300_get_eeprom()
3006 return eep->base_ext1.ant_div_control; in ath9k_hw_ar9300_get_eeprom()
3008 return eep->modalHeader5G.antennaGain; in ath9k_hw_ar9300_get_eeprom()
3010 return eep->modalHeader2G.antennaGain; in ath9k_hw_ar9300_get_eeprom()
3016 static bool ar9300_eeprom_read_byte(struct ath_hw *ah, int address, in ar9300_eeprom_read_byte() argument
3021 if (unlikely(!ath9k_hw_nvram_read(ah, address / 2, &val))) in ar9300_eeprom_read_byte()
3028 static bool ar9300_eeprom_read_word(struct ath_hw *ah, int address, in ar9300_eeprom_read_word() argument
3033 if (unlikely(!ath9k_hw_nvram_read(ah, address / 2, &val))) in ar9300_eeprom_read_word()
3042 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer, in ar9300_read_eeprom() argument
3045 struct ath_common *common = ath9k_hw_common(ah); in ar9300_read_eeprom()
3048 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) { in ar9300_read_eeprom()
3054 * Since we're reading the bytes in reverse order from a little-endian in ar9300_read_eeprom()
3056 * the 16-bit word at that address in ar9300_read_eeprom()
3059 if (!ar9300_eeprom_read_byte(ah, address--, buffer++)) in ar9300_read_eeprom()
3062 count--; in ar9300_read_eeprom()
3066 if (!ar9300_eeprom_read_word(ah, address, buffer)) in ar9300_read_eeprom()
3069 address -= 2; in ar9300_read_eeprom()
3074 if (!ar9300_eeprom_read_byte(ah, address, buffer)) in ar9300_read_eeprom()
3085 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data) in ar9300_otp_read_word() argument
3087 REG_READ(ah, AR9300_OTP_BASE(ah) + (4 * addr)); in ar9300_otp_read_word()
3089 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS(ah), AR9300_OTP_STATUS_TYPE, in ar9300_otp_read_word()
3093 *data = REG_READ(ah, AR9300_OTP_READ_DATA(ah)); in ar9300_otp_read_word()
3097 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer, in ar9300_read_otp() argument
3104 int offset = 8 * ((address - i) % 4); in ar9300_read_otp()
3105 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data)) in ar9300_read_otp()
3124 *code = ((value[0] >> 5) & 0x0007); in ar9300_comp_hdr_unpack()
3143 static bool ar9300_uncompress_block(struct ath_hw *ah, in ar9300_uncompress_block() argument
3153 struct ath_common *common = ath9k_hw_common(ah); in ar9300_uncompress_block()
3180 static int ar9300_compress_decision(struct ath_hw *ah, in ar9300_compress_decision() argument
3187 struct ath_common *common = ath9k_hw_common(ah); in ar9300_compress_decision()
3196 return -1; in ar9300_compress_decision()
3210 return -1; in ar9300_compress_decision()
3217 ar9300_uncompress_block(ah, mptr, mdata_size, in ar9300_compress_decision()
3222 return -1; in ar9300_compress_decision()
3227 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3236 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read, in ar9300_check_eeprom_header() argument
3241 if (!read(ah, base_addr, header, 4)) in ar9300_check_eeprom_header()
3247 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr, in ar9300_eeprom_restore_flash() argument
3254 if (!ath9k_hw_nvram_read(ah, i, data)) in ar9300_eeprom_restore_flash()
3255 return -EIO; in ar9300_eeprom_restore_flash()
3263 * Returns -1 on error.
3266 static int ar9300_eeprom_restore_internal(struct ath_hw *ah, in ar9300_eeprom_restore_internal() argument
3278 struct ath_common *common = ath9k_hw_common(ah); in ar9300_eeprom_restore_internal()
3282 if (ath9k_hw_use_flash(ah)) { in ar9300_eeprom_restore_internal()
3285 if (ar9300_eeprom_restore_flash(ah, mptr, mdata_size)) in ar9300_eeprom_restore_internal()
3286 return -EIO; in ar9300_eeprom_restore_internal()
3290 txrx = eep->baseEepHeader.txrxMask; in ar9300_eeprom_restore_internal()
3297 return -ENOMEM; in ar9300_eeprom_restore_internal()
3302 if (AR_SREV_9485(ah)) in ar9300_eeprom_restore_internal()
3304 else if (AR_SREV_9330(ah)) in ar9300_eeprom_restore_internal()
3310 if (ar9300_check_eeprom_header(ah, read, cptr)) in ar9300_eeprom_restore_internal()
3316 if (ar9300_check_eeprom_header(ah, read, cptr)) in ar9300_eeprom_restore_internal()
3322 if (ar9300_check_eeprom_header(ah, read, cptr)) in ar9300_eeprom_restore_internal()
3328 if (ar9300_check_eeprom_header(ah, read, cptr)) in ar9300_eeprom_restore_internal()
3333 if (ar9300_check_eeprom_header(ah, read, cptr)) in ar9300_eeprom_restore_internal()
3342 if (!read(ah, cptr, word, COMP_HDR_LEN)) in ar9300_eeprom_restore_internal()
3353 if ((!AR_SREV_9485(ah) && length >= 1024) || in ar9300_eeprom_restore_internal()
3354 (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485) || in ar9300_eeprom_restore_internal()
3357 cptr -= COMP_HDR_LEN; in ar9300_eeprom_restore_internal()
3362 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN); in ar9300_eeprom_restore_internal()
3368 ar9300_compress_decision(ah, it, code, reference, mptr, in ar9300_eeprom_restore_internal()
3374 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN); in ar9300_eeprom_restore_internal()
3382 return -1; in ar9300_eeprom_restore_internal()
3387 * This function destroys any existing in-memory structure
3390 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah) in ath9k_hw_ar9300_fill_eeprom() argument
3392 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep; in ath9k_hw_ar9300_fill_eeprom()
3394 if (ar9300_eeprom_restore_internal(ah, mptr, in ath9k_hw_ar9300_fill_eeprom()
3405 PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0])); in ar9003_dump_modal_eeprom()
3406 PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1])); in ar9003_dump_modal_eeprom()
3407 PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2])); in ar9003_dump_modal_eeprom()
3408 PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon)); in ar9003_dump_modal_eeprom()
3409 PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2)); in ar9003_dump_modal_eeprom()
3410 PR_EEP("Ant. Gain", modal_hdr->antennaGain); in ar9003_dump_modal_eeprom()
3411 PR_EEP("Switch Settle", modal_hdr->switchSettling); in ar9003_dump_modal_eeprom()
3412 PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]); in ar9003_dump_modal_eeprom()
3413 PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]); in ar9003_dump_modal_eeprom()
3414 PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]); in ar9003_dump_modal_eeprom()
3415 PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]); in ar9003_dump_modal_eeprom()
3416 PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]); in ar9003_dump_modal_eeprom()
3417 PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]); in ar9003_dump_modal_eeprom()
3418 PR_EEP("Temp Slope", modal_hdr->tempSlope); in ar9003_dump_modal_eeprom()
3419 PR_EEP("Volt Slope", modal_hdr->voltSlope); in ar9003_dump_modal_eeprom()
3420 PR_EEP("spur Channels0", modal_hdr->spurChans[0]); in ar9003_dump_modal_eeprom()
3421 PR_EEP("spur Channels1", modal_hdr->spurChans[1]); in ar9003_dump_modal_eeprom()
3422 PR_EEP("spur Channels2", modal_hdr->spurChans[2]); in ar9003_dump_modal_eeprom()
3423 PR_EEP("spur Channels3", modal_hdr->spurChans[3]); in ar9003_dump_modal_eeprom()
3424 PR_EEP("spur Channels4", modal_hdr->spurChans[4]); in ar9003_dump_modal_eeprom()
3425 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]); in ar9003_dump_modal_eeprom()
3426 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]); in ar9003_dump_modal_eeprom()
3427 PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]); in ar9003_dump_modal_eeprom()
3428 PR_EEP("Quick Drop", modal_hdr->quick_drop); in ar9003_dump_modal_eeprom()
3429 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff); in ar9003_dump_modal_eeprom()
3430 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl); in ar9003_dump_modal_eeprom()
3431 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart); in ar9003_dump_modal_eeprom()
3432 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn); in ar9003_dump_modal_eeprom()
3433 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn); in ar9003_dump_modal_eeprom()
3434 PR_EEP("txClip", modal_hdr->txClip); in ar9003_dump_modal_eeprom()
3435 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize); in ar9003_dump_modal_eeprom()
3440 static u32 ar9003_dump_cal_data(struct ath_hw *ah, char *buf, u32 len, u32 size, in ar9003_dump_cal_data() argument
3443 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_dump_cal_data()
3450 pBase = &eep->baseEepHeader; in ar9003_dump_cal_data()
3458 if (!((pBase->txrxMask >> i) & 1)) in ar9003_dump_cal_data()
3461 len += scnprintf(buf + len, size - len, "Chain %d\n", i); in ar9003_dump_cal_data()
3463 len += scnprintf(buf + len, size - len, in ar9003_dump_cal_data()
3468 cal_pier = &eep->calPierData2G[i][j]; in ar9003_dump_cal_data()
3469 freq = 2300 + eep->calFreqPier2G[j]; in ar9003_dump_cal_data()
3471 cal_pier = &eep->calPierData5G[i][j]; in ar9003_dump_cal_data()
3472 freq = 4800 + eep->calFreqPier5G[j] * 5; in ar9003_dump_cal_data()
3475 len += scnprintf(buf + len, size - len, in ar9003_dump_cal_data()
3478 len += scnprintf(buf + len, size - len, in ar9003_dump_cal_data()
3480 cal_pier->refPower, in ar9003_dump_cal_data()
3481 cal_pier->voltMeas, in ar9003_dump_cal_data()
3482 cal_pier->tempMeas, in ar9003_dump_cal_data()
3483 cal_pier->rxTempMeas ? in ar9003_dump_cal_data()
3484 N2DBM(cal_pier->rxNoisefloorCal) : 0, in ar9003_dump_cal_data()
3485 cal_pier->rxTempMeas ? in ar9003_dump_cal_data()
3486 N2DBM(cal_pier->rxNoisefloorPower) : 0, in ar9003_dump_cal_data()
3487 cal_pier->rxTempMeas); in ar9003_dump_cal_data()
3494 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, in ath9k_hw_ar9003_dump_eeprom() argument
3497 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ath9k_hw_ar9003_dump_eeprom()
3501 len += scnprintf(buf + len, size - len, in ath9k_hw_ar9003_dump_eeprom()
3504 &eep->modalHeader2G); in ath9k_hw_ar9003_dump_eeprom()
3506 len += scnprintf(buf + len, size - len, "Calibration data\n"); in ath9k_hw_ar9003_dump_eeprom()
3507 len = ar9003_dump_cal_data(ah, buf, len, size, true); in ath9k_hw_ar9003_dump_eeprom()
3509 len += scnprintf(buf + len, size - len, in ath9k_hw_ar9003_dump_eeprom()
3510 "%20s :\n", "5GHz modal Header"); in ath9k_hw_ar9003_dump_eeprom()
3512 &eep->modalHeader5G); in ath9k_hw_ar9003_dump_eeprom()
3514 len += scnprintf(buf + len, size - len, "Calibration data\n"); in ath9k_hw_ar9003_dump_eeprom()
3515 len = ar9003_dump_cal_data(ah, buf, len, size, false); in ath9k_hw_ar9003_dump_eeprom()
3520 pBase = &eep->baseEepHeader; in ath9k_hw_ar9003_dump_eeprom()
3522 PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion); in ath9k_hw_ar9003_dump_eeprom()
3523 PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0])); in ath9k_hw_ar9003_dump_eeprom()
3524 PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1])); in ath9k_hw_ar9003_dump_eeprom()
3525 PR_EEP("TX Mask", (pBase->txrxMask >> 4)); in ath9k_hw_ar9003_dump_eeprom()
3526 PR_EEP("RX Mask", (pBase->txrxMask & 0x0f)); in ath9k_hw_ar9003_dump_eeprom()
3527 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags & in ath9k_hw_ar9003_dump_eeprom()
3529 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags & in ath9k_hw_ar9003_dump_eeprom()
3531 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags & in ath9k_hw_ar9003_dump_eeprom()
3533 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags & in ath9k_hw_ar9003_dump_eeprom()
3535 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags & in ath9k_hw_ar9003_dump_eeprom()
3537 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags & in ath9k_hw_ar9003_dump_eeprom()
3539 PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & in ath9k_hw_ar9003_dump_eeprom()
3541 PR_EEP("RF Silent", pBase->rfSilent); in ath9k_hw_ar9003_dump_eeprom()
3542 PR_EEP("BT option", pBase->blueToothOptions); in ath9k_hw_ar9003_dump_eeprom()
3543 PR_EEP("Device Cap", pBase->deviceCap); in ath9k_hw_ar9003_dump_eeprom()
3544 PR_EEP("Device Type", pBase->deviceType); in ath9k_hw_ar9003_dump_eeprom()
3545 PR_EEP("Power Table Offset", pBase->pwrTableOffset); in ath9k_hw_ar9003_dump_eeprom()
3546 PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]); in ath9k_hw_ar9003_dump_eeprom()
3547 PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]); in ath9k_hw_ar9003_dump_eeprom()
3548 PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0))); in ath9k_hw_ar9003_dump_eeprom()
3549 PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1))); in ath9k_hw_ar9003_dump_eeprom()
3550 PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2))); in ath9k_hw_ar9003_dump_eeprom()
3551 PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3))); in ath9k_hw_ar9003_dump_eeprom()
3552 PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4))); in ath9k_hw_ar9003_dump_eeprom()
3553 PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5))); in ath9k_hw_ar9003_dump_eeprom()
3554 PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0))); in ath9k_hw_ar9003_dump_eeprom()
3555 PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1))); in ath9k_hw_ar9003_dump_eeprom()
3556 PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1); in ath9k_hw_ar9003_dump_eeprom()
3557 PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio); in ath9k_hw_ar9003_dump_eeprom()
3558 PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio); in ath9k_hw_ar9003_dump_eeprom()
3559 PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio); in ath9k_hw_ar9003_dump_eeprom()
3560 PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio); in ath9k_hw_ar9003_dump_eeprom()
3561 PR_EEP("Tx Gain", pBase->txrxgain >> 4); in ath9k_hw_ar9003_dump_eeprom()
3562 PR_EEP("Rx Gain", pBase->txrxgain & 0xf); in ath9k_hw_ar9003_dump_eeprom()
3563 PR_EEP("SW Reg", le32_to_cpu(pBase->swreg)); in ath9k_hw_ar9003_dump_eeprom()
3565 len += scnprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress", in ath9k_hw_ar9003_dump_eeprom()
3566 ah->eeprom.ar9300_eep.macAddr); in ath9k_hw_ar9003_dump_eeprom()
3574 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, in ath9k_hw_ar9003_dump_eeprom() argument
3582 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah) in ath9k_hw_ar9300_get_eeprom_ver() argument
3584 return ah->eeprom.ar9300_eep.eepromVersion; in ath9k_hw_ar9300_get_eeprom_ver()
3588 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah) in ath9k_hw_ar9300_get_eeprom_rev() argument
3593 static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah, in ar9003_modal_header() argument
3596 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_modal_header()
3599 return &eep->modalHeader2G; in ar9003_modal_header()
3601 return &eep->modalHeader5G; in ar9003_modal_header()
3604 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) in ar9003_hw_xpa_bias_level_apply() argument
3606 int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl; in ar9003_hw_xpa_bias_level_apply()
3608 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah) || in ar9003_hw_xpa_bias_level_apply()
3609 AR_SREV_9531(ah) || AR_SREV_9561(ah)) in ar9003_hw_xpa_bias_level_apply()
3610 REG_RMW_FIELD(ah, AR_CH0_TOP2(ah), AR_CH0_TOP2_XPABIASLVL, bias); in ar9003_hw_xpa_bias_level_apply()
3611 else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9565(ah)) in ar9003_hw_xpa_bias_level_apply()
3612 REG_RMW_FIELD(ah, AR_CH0_TOP(ah), AR_CH0_TOP_XPABIASLVL, bias); in ar9003_hw_xpa_bias_level_apply()
3614 REG_RMW_FIELD(ah, AR_CH0_TOP(ah), AR_CH0_TOP_XPABIASLVL, bias); in ar9003_hw_xpa_bias_level_apply()
3615 REG_RMW_FIELD(ah, AR_CH0_THERM(ah), in ar9003_hw_xpa_bias_level_apply()
3618 REG_RMW_FIELD(ah, AR_CH0_THERM(ah), in ar9003_hw_xpa_bias_level_apply()
3623 static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz) in ar9003_switch_com_spdt_get() argument
3625 return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt); in ar9003_switch_com_spdt_get()
3628 u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz) in ar9003_hw_ant_ctrl_common_get() argument
3630 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon); in ar9003_hw_ant_ctrl_common_get()
3633 u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz) in ar9003_hw_ant_ctrl_common_2_get() argument
3635 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2); in ar9003_hw_ant_ctrl_common_2_get()
3638 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain, in ar9003_hw_ant_ctrl_chain_get() argument
3641 __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain]; in ar9003_hw_ant_ctrl_chain_get()
3645 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) in ar9003_hw_ant_ctrl_apply() argument
3647 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_ant_ctrl_apply()
3648 struct ath9k_hw_capabilities *pCap = &ah->caps; in ar9003_hw_ant_ctrl_apply()
3657 if (AR_SREV_9485(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0)) { in ar9003_hw_ant_ctrl_apply()
3658 if (ah->config.xlna_gpio) in ar9003_hw_ant_ctrl_apply()
3659 gpio = ah->config.xlna_gpio; in ar9003_hw_ant_ctrl_apply()
3663 ath9k_hw_gpio_request_out(ah, gpio, NULL, in ar9003_hw_ant_ctrl_apply()
3667 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz); in ar9003_hw_ant_ctrl_apply()
3669 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ar9003_hw_ant_ctrl_apply()
3670 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, in ar9003_hw_ant_ctrl_apply()
3672 } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ar9003_hw_ant_ctrl_apply()
3673 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, in ar9003_hw_ant_ctrl_apply()
3676 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, in ar9003_hw_ant_ctrl_apply()
3682 * here's new field name in XXX.ref for both 2G and 5G. in ar9003_hw_ant_ctrl_apply()
3693 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565(ah)) { in ar9003_hw_ant_ctrl_apply()
3694 value = ar9003_switch_com_spdt_get(ah, is2ghz); in ar9003_hw_ant_ctrl_apply()
3695 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, in ar9003_hw_ant_ctrl_apply()
3697 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE); in ar9003_hw_ant_ctrl_apply()
3700 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz); in ar9003_hw_ant_ctrl_apply()
3701 if (AR_SREV_9485(ah) && common->bt_ant_diversity) { in ar9003_hw_ant_ctrl_apply()
3703 value |= ah->config.ant_ctrl_comm2g_switch_enable; in ar9003_hw_ant_ctrl_apply()
3706 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value); in ar9003_hw_ant_ctrl_apply()
3708 if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) { in ar9003_hw_ant_ctrl_apply()
3709 value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz); in ar9003_hw_ant_ctrl_apply()
3710 REG_RMW_FIELD(ah, switch_chain_reg[0], in ar9003_hw_ant_ctrl_apply()
3715 if ((ah->rxchainmask & BIT(chain)) || in ar9003_hw_ant_ctrl_apply()
3716 (ah->txchainmask & BIT(chain))) { in ar9003_hw_ant_ctrl_apply()
3717 value = ar9003_hw_ant_ctrl_chain_get(ah, chain, in ar9003_hw_ant_ctrl_apply()
3719 REG_RMW_FIELD(ah, switch_chain_reg[chain], in ar9003_hw_ant_ctrl_apply()
3724 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { in ar9003_hw_ant_ctrl_apply()
3725 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1); in ar9003_hw_ant_ctrl_apply()
3730 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_ant_ctrl_apply()
3737 if (AR_SREV_9485(ah) && common->bt_ant_diversity) in ar9003_hw_ant_ctrl_apply()
3740 if (AR_SREV_9565(ah)) { in ar9003_hw_ant_ctrl_apply()
3741 if (common->bt_ant_diversity) { in ar9003_hw_ant_ctrl_apply()
3744 REG_SET_BIT(ah, AR_PHY_RESTART, in ar9003_hw_ant_ctrl_apply()
3748 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_ant_ctrl_apply()
3754 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_ant_ctrl_apply()
3758 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_ant_ctrl_apply()
3763 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_ant_ctrl_apply()
3766 regval = REG_READ(ah, AR_PHY_CCK_DETECT); in ar9003_hw_ant_ctrl_apply()
3770 if ((AR_SREV_9485(ah) || AR_SREV_9565(ah)) in ar9003_hw_ant_ctrl_apply()
3771 && common->bt_ant_diversity) in ar9003_hw_ant_ctrl_apply()
3774 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); in ar9003_hw_ant_ctrl_apply()
3776 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { in ar9003_hw_ant_ctrl_apply()
3777 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_ant_ctrl_apply()
3779 * clear bits 25-30 main_lnaconf, alt_lnaconf, in ar9003_hw_ant_ctrl_apply()
3791 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_ant_ctrl_apply()
3796 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah) in ar9003_hw_drive_strength_apply() argument
3798 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_drive_strength_apply()
3799 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; in ar9003_hw_drive_strength_apply()
3801 unsigned long reg; in ar9003_hw_drive_strength_apply() local
3803 drive_strength = pBase->miscConfiguration & BIT(0); in ar9003_hw_drive_strength_apply()
3807 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1); in ar9003_hw_drive_strength_apply()
3808 reg &= ~0x00ffffc0; in ar9003_hw_drive_strength_apply()
3809 reg |= 0x5 << 21; in ar9003_hw_drive_strength_apply()
3810 reg |= 0x5 << 18; in ar9003_hw_drive_strength_apply()
3811 reg |= 0x5 << 15; in ar9003_hw_drive_strength_apply()
3812 reg |= 0x5 << 12; in ar9003_hw_drive_strength_apply()
3813 reg |= 0x5 << 9; in ar9003_hw_drive_strength_apply()
3814 reg |= 0x5 << 6; in ar9003_hw_drive_strength_apply()
3815 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg); in ar9003_hw_drive_strength_apply()
3817 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2); in ar9003_hw_drive_strength_apply()
3818 reg &= ~0xffffffe0; in ar9003_hw_drive_strength_apply()
3819 reg |= 0x5 << 29; in ar9003_hw_drive_strength_apply()
3820 reg |= 0x5 << 26; in ar9003_hw_drive_strength_apply()
3821 reg |= 0x5 << 23; in ar9003_hw_drive_strength_apply()
3822 reg |= 0x5 << 20; in ar9003_hw_drive_strength_apply()
3823 reg |= 0x5 << 17; in ar9003_hw_drive_strength_apply()
3824 reg |= 0x5 << 14; in ar9003_hw_drive_strength_apply()
3825 reg |= 0x5 << 11; in ar9003_hw_drive_strength_apply()
3826 reg |= 0x5 << 8; in ar9003_hw_drive_strength_apply()
3827 reg |= 0x5 << 5; in ar9003_hw_drive_strength_apply()
3828 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg); in ar9003_hw_drive_strength_apply()
3830 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4); in ar9003_hw_drive_strength_apply()
3831 reg &= ~0xff800000; in ar9003_hw_drive_strength_apply()
3832 reg |= 0x5 << 29; in ar9003_hw_drive_strength_apply()
3833 reg |= 0x5 << 26; in ar9003_hw_drive_strength_apply()
3834 reg |= 0x5 << 23; in ar9003_hw_drive_strength_apply()
3835 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg); in ar9003_hw_drive_strength_apply()
3838 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain, in ar9003_hw_atten_chain_get() argument
3843 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_atten_chain_get()
3847 return eep->modalHeader2G.xatten1DB[chain]; in ar9003_hw_atten_chain_get()
3848 else if (eep->base_ext2.xatten1DBLow[chain] != 0) { in ar9003_hw_atten_chain_get()
3849 t[0] = eep->base_ext2.xatten1DBLow[chain]; in ar9003_hw_atten_chain_get()
3851 t[1] = eep->modalHeader5G.xatten1DB[chain]; in ar9003_hw_atten_chain_get()
3853 t[2] = eep->base_ext2.xatten1DBHigh[chain]; in ar9003_hw_atten_chain_get()
3855 value = ar9003_hw_power_interpolate((s32) chan->channel, in ar9003_hw_atten_chain_get()
3859 return eep->modalHeader5G.xatten1DB[chain]; in ar9003_hw_atten_chain_get()
3866 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain, in ar9003_hw_atten_chain_get_margin() argument
3871 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_atten_chain_get_margin()
3875 return eep->modalHeader2G.xatten1Margin[chain]; in ar9003_hw_atten_chain_get_margin()
3876 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) { in ar9003_hw_atten_chain_get_margin()
3877 t[0] = eep->base_ext2.xatten1MarginLow[chain]; in ar9003_hw_atten_chain_get_margin()
3879 t[1] = eep->modalHeader5G.xatten1Margin[chain]; in ar9003_hw_atten_chain_get_margin()
3881 t[2] = eep->base_ext2.xatten1MarginHigh[chain]; in ar9003_hw_atten_chain_get_margin()
3883 value = ar9003_hw_power_interpolate((s32) chan->channel, in ar9003_hw_atten_chain_get_margin()
3887 return eep->modalHeader5G.xatten1Margin[chain]; in ar9003_hw_atten_chain_get_margin()
3893 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan) in ar9003_hw_atten_apply() argument
3902 if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) { in ar9003_hw_atten_apply()
3903 value = ar9003_hw_atten_chain_get(ah, 1, chan); in ar9003_hw_atten_apply()
3904 REG_RMW_FIELD(ah, ext_atten_reg[0], in ar9003_hw_atten_apply()
3907 value = ar9003_hw_atten_chain_get_margin(ah, 1, chan); in ar9003_hw_atten_apply()
3908 REG_RMW_FIELD(ah, ext_atten_reg[0], in ar9003_hw_atten_apply()
3915 if (ah->txchainmask & BIT(i)) { in ar9003_hw_atten_apply()
3916 value = ar9003_hw_atten_chain_get(ah, i, chan); in ar9003_hw_atten_apply()
3917 REG_RMW_FIELD(ah, ext_atten_reg[i], in ar9003_hw_atten_apply()
3920 if (AR_SREV_9485(ah) && in ar9003_hw_atten_apply()
3921 (ar9003_hw_get_rx_gain_idx(ah) == 0) && in ar9003_hw_atten_apply()
3922 ah->config.xatten_margin_cfg) in ar9003_hw_atten_apply()
3923 value = 5; in ar9003_hw_atten_apply()
3925 value = ar9003_hw_atten_chain_get_margin(ah, i, chan); in ar9003_hw_atten_apply()
3927 if (ah->config.alt_mingainidx) in ar9003_hw_atten_apply()
3928 REG_RMW_FIELD(ah, AR_PHY_EXT_ATTEN_CTL_0, in ar9003_hw_atten_apply()
3932 REG_RMW_FIELD(ah, ext_atten_reg[i], in ar9003_hw_atten_apply()
3939 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set) in is_pmu_set() argument
3943 while (pmu_set != REG_READ(ah, pmu_reg)) { in is_pmu_set()
3944 if (timeout-- == 0) in is_pmu_set()
3946 REG_WRITE(ah, pmu_reg, pmu_set); in is_pmu_set()
3953 void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) in ar9003_hw_internal_regulator_apply() argument
3955 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_internal_regulator_apply()
3956 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; in ar9003_hw_internal_regulator_apply()
3959 if (pBase->featureEnable & BIT(4)) { in ar9003_hw_internal_regulator_apply()
3960 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { in ar9003_hw_internal_regulator_apply()
3963 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2(ah)) & ~AR_PHY_PMU2_PGM; in ar9003_hw_internal_regulator_apply()
3964 REG_WRITE(ah, AR_PHY_PMU2(ah), reg_pmu_set); in ar9003_hw_internal_regulator_apply()
3965 if (!is_pmu_set(ah, AR_PHY_PMU2(ah), reg_pmu_set)) in ar9003_hw_internal_regulator_apply()
3968 if (AR_SREV_9330(ah)) { in ar9003_hw_internal_regulator_apply()
3969 if (ah->is_clk_25mhz) { in ar9003_hw_internal_regulator_apply()
3981 reg_pmu_set = (5 << 1) | (7 << 4) | in ar9003_hw_internal_regulator_apply()
3987 REG_WRITE(ah, AR_PHY_PMU1(ah), reg_pmu_set); in ar9003_hw_internal_regulator_apply()
3988 if (!is_pmu_set(ah, AR_PHY_PMU1(ah), reg_pmu_set)) in ar9003_hw_internal_regulator_apply()
3991 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2(ah)) & ~0xFFC00000) in ar9003_hw_internal_regulator_apply()
3993 REG_WRITE(ah, AR_PHY_PMU2(ah), reg_pmu_set); in ar9003_hw_internal_regulator_apply()
3994 if (!is_pmu_set(ah, AR_PHY_PMU2(ah), reg_pmu_set)) in ar9003_hw_internal_regulator_apply()
3997 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2(ah)) & ~0x00200000) in ar9003_hw_internal_regulator_apply()
3999 REG_WRITE(ah, AR_PHY_PMU2(ah), reg_pmu_set); in ar9003_hw_internal_regulator_apply()
4000 if (!is_pmu_set(ah, AR_PHY_PMU2(ah), reg_pmu_set)) in ar9003_hw_internal_regulator_apply()
4002 } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah) || in ar9003_hw_internal_regulator_apply()
4003 AR_SREV_9561(ah)) { in ar9003_hw_internal_regulator_apply()
4004 reg_val = le32_to_cpu(pBase->swreg); in ar9003_hw_internal_regulator_apply()
4005 REG_WRITE(ah, AR_PHY_PMU1(ah), reg_val); in ar9003_hw_internal_regulator_apply()
4007 if (AR_SREV_9561(ah)) in ar9003_hw_internal_regulator_apply()
4008 REG_WRITE(ah, AR_PHY_PMU2(ah), 0x10200000); in ar9003_hw_internal_regulator_apply()
4011 reg_val = le32_to_cpu(pBase->swreg); in ar9003_hw_internal_regulator_apply()
4012 REG_WRITE(ah, AR_RTC_REG_CONTROL1, in ar9003_hw_internal_regulator_apply()
4013 REG_READ(ah, AR_RTC_REG_CONTROL1) & in ar9003_hw_internal_regulator_apply()
4015 REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val); in ar9003_hw_internal_regulator_apply()
4017 REG_WRITE(ah, AR_RTC_REG_CONTROL1, in ar9003_hw_internal_regulator_apply()
4018 REG_READ(ah, in ar9003_hw_internal_regulator_apply()
4023 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { in ar9003_hw_internal_regulator_apply()
4024 REG_RMW_FIELD(ah, AR_PHY_PMU2(ah), AR_PHY_PMU2_PGM, 0); in ar9003_hw_internal_regulator_apply()
4025 while (REG_READ_FIELD(ah, AR_PHY_PMU2(ah), in ar9003_hw_internal_regulator_apply()
4029 REG_RMW_FIELD(ah, AR_PHY_PMU1(ah), AR_PHY_PMU1_PWD, 0x1); in ar9003_hw_internal_regulator_apply()
4030 while (!REG_READ_FIELD(ah, AR_PHY_PMU1(ah), in ar9003_hw_internal_regulator_apply()
4033 REG_RMW_FIELD(ah, AR_PHY_PMU2(ah), AR_PHY_PMU2_PGM, 0x1); in ar9003_hw_internal_regulator_apply()
4034 while (!REG_READ_FIELD(ah, AR_PHY_PMU2(ah), in ar9003_hw_internal_regulator_apply()
4037 } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ar9003_hw_internal_regulator_apply()
4038 REG_RMW_FIELD(ah, AR_PHY_PMU1(ah), AR_PHY_PMU1_PWD, 0x1); in ar9003_hw_internal_regulator_apply()
4040 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK(ah)) | in ar9003_hw_internal_regulator_apply()
4042 REG_WRITE(ah, AR_RTC_SLEEP_CLK(ah), reg_val); in ar9003_hw_internal_regulator_apply()
4048 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah) in ar9003_hw_apply_tuning_caps() argument
4050 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_apply_tuning_caps()
4051 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0]; in ar9003_hw_apply_tuning_caps()
4053 if (AR_SREV_9340(ah) || AR_SREV_9531(ah)) in ar9003_hw_apply_tuning_caps()
4056 if (eep->baseEepHeader.featureEnable & 0x40) { in ar9003_hw_apply_tuning_caps()
4058 REG_RMW_FIELD(ah, AR_CH0_XTAL(ah), AR_CH0_XTAL_CAPINDAC, in ar9003_hw_apply_tuning_caps()
4060 REG_RMW_FIELD(ah, AR_CH0_XTAL(ah), AR_CH0_XTAL_CAPOUTDAC, in ar9003_hw_apply_tuning_caps()
4065 static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq) in ar9003_hw_quick_drop_apply() argument
4067 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_quick_drop_apply()
4068 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; in ar9003_hw_quick_drop_apply()
4072 if (!(pBase->miscConfiguration & BIT(4))) in ar9003_hw_quick_drop_apply()
4075 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9340(ah)) { in ar9003_hw_quick_drop_apply()
4077 quick_drop = eep->modalHeader2G.quick_drop; in ar9003_hw_quick_drop_apply()
4079 t[0] = eep->base_ext1.quick_drop_low; in ar9003_hw_quick_drop_apply()
4080 t[1] = eep->modalHeader5G.quick_drop; in ar9003_hw_quick_drop_apply()
4081 t[2] = eep->base_ext1.quick_drop_high; in ar9003_hw_quick_drop_apply()
4084 REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop); in ar9003_hw_quick_drop_apply()
4088 static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz) in ar9003_hw_txend_to_xpa_off_apply() argument
4092 value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff; in ar9003_hw_txend_to_xpa_off_apply()
4094 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, in ar9003_hw_txend_to_xpa_off_apply()
4096 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, in ar9003_hw_txend_to_xpa_off_apply()
4100 static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz) in ar9003_hw_xpa_timing_control_apply() argument
4102 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_xpa_timing_control_apply()
4105 if (!(eep->baseEepHeader.featureEnable & 0x80)) in ar9003_hw_xpa_timing_control_apply()
4108 if (!AR_SREV_9300(ah) && in ar9003_hw_xpa_timing_control_apply()
4109 !AR_SREV_9340(ah) && in ar9003_hw_xpa_timing_control_apply()
4110 !AR_SREV_9580(ah) && in ar9003_hw_xpa_timing_control_apply()
4111 !AR_SREV_9531(ah) && in ar9003_hw_xpa_timing_control_apply()
4112 !AR_SREV_9561(ah)) in ar9003_hw_xpa_timing_control_apply()
4115 xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn; in ar9003_hw_xpa_timing_control_apply()
4117 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, in ar9003_hw_xpa_timing_control_apply()
4120 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, in ar9003_hw_xpa_timing_control_apply()
4124 static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz) in ar9003_hw_xlna_bias_strength_apply() argument
4126 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_xlna_bias_strength_apply()
4129 if (!(eep->baseEepHeader.miscConfiguration & 0x40)) in ar9003_hw_xlna_bias_strength_apply()
4132 if (!AR_SREV_9300(ah)) in ar9003_hw_xlna_bias_strength_apply()
4135 bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength; in ar9003_hw_xlna_bias_strength_apply()
4136 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS, in ar9003_hw_xlna_bias_strength_apply()
4139 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS, in ar9003_hw_xlna_bias_strength_apply()
4142 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS, in ar9003_hw_xlna_bias_strength_apply()
4146 static int ar9003_hw_get_thermometer(struct ath_hw *ah) in ar9003_hw_get_thermometer() argument
4148 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_get_thermometer()
4149 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; in ar9003_hw_get_thermometer()
4150 int thermometer = (pBase->miscConfiguration >> 1) & 0x3; in ar9003_hw_get_thermometer()
4152 return --thermometer; in ar9003_hw_get_thermometer()
4155 static void ar9003_hw_thermometer_apply(struct ath_hw *ah) in ar9003_hw_thermometer_apply() argument
4157 struct ath9k_hw_capabilities *pCap = &ah->caps; in ar9003_hw_thermometer_apply()
4158 int thermometer = ar9003_hw_get_thermometer(ah); in ar9003_hw_thermometer_apply()
4161 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, in ar9003_hw_thermometer_apply()
4163 if (pCap->chip_chainmask & BIT(1)) in ar9003_hw_thermometer_apply()
4164 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, in ar9003_hw_thermometer_apply()
4166 if (pCap->chip_chainmask & BIT(2)) in ar9003_hw_thermometer_apply()
4167 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, in ar9003_hw_thermometer_apply()
4171 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, in ar9003_hw_thermometer_apply()
4173 if (pCap->chip_chainmask & BIT(1)) { in ar9003_hw_thermometer_apply()
4175 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, in ar9003_hw_thermometer_apply()
4178 if (pCap->chip_chainmask & BIT(2)) { in ar9003_hw_thermometer_apply()
4180 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, in ar9003_hw_thermometer_apply()
4185 static void ar9003_hw_thermo_cal_apply(struct ath_hw *ah) in ar9003_hw_thermo_cal_apply() argument
4189 if (!AR_SREV_9462_20_OR_LATER(ah)) in ar9003_hw_thermo_cal_apply()
4192 ar9300_otp_read_word(ah, 1, &data); in ar9003_hw_thermo_cal_apply()
4196 REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3, in ar9003_hw_thermo_cal_apply()
4198 REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3, in ar9003_hw_thermo_cal_apply()
4204 static void ar9003_hw_apply_minccapwr_thresh(struct ath_hw *ah, in ar9003_hw_apply_minccapwr_thresh() argument
4207 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_apply_minccapwr_thresh()
4217 if (!(eep->base_ext1.misc_enable & BIT(2))) in ar9003_hw_apply_minccapwr_thresh()
4220 if (!(eep->base_ext1.misc_enable & BIT(3))) in ar9003_hw_apply_minccapwr_thresh()
4225 if (!(ah->caps.tx_chainmask & BIT(chain))) in ar9003_hw_apply_minccapwr_thresh()
4228 val = ar9003_modal_header(ah, is2ghz)->noiseFloorThreshCh[chain]; in ar9003_hw_apply_minccapwr_thresh()
4229 REG_RMW_FIELD(ah, cca_ctrl[chain], in ar9003_hw_apply_minccapwr_thresh()
4235 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, in ath9k_hw_ar9300_set_board_values() argument
4239 ar9003_hw_xpa_timing_control_apply(ah, is2ghz); in ath9k_hw_ar9300_set_board_values()
4240 ar9003_hw_xpa_bias_level_apply(ah, is2ghz); in ath9k_hw_ar9300_set_board_values()
4241 ar9003_hw_ant_ctrl_apply(ah, is2ghz); in ath9k_hw_ar9300_set_board_values()
4242 ar9003_hw_drive_strength_apply(ah); in ath9k_hw_ar9300_set_board_values()
4243 ar9003_hw_xlna_bias_strength_apply(ah, is2ghz); in ath9k_hw_ar9300_set_board_values()
4244 ar9003_hw_atten_apply(ah, chan); in ath9k_hw_ar9300_set_board_values()
4245 ar9003_hw_quick_drop_apply(ah, chan->channel); in ath9k_hw_ar9300_set_board_values()
4246 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9531(ah)) in ath9k_hw_ar9300_set_board_values()
4247 ar9003_hw_internal_regulator_apply(ah); in ath9k_hw_ar9300_set_board_values()
4248 ar9003_hw_apply_tuning_caps(ah); in ath9k_hw_ar9300_set_board_values()
4249 ar9003_hw_apply_minccapwr_thresh(ah, is2ghz); in ath9k_hw_ar9300_set_board_values()
4250 ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz); in ath9k_hw_ar9300_set_board_values()
4251 ar9003_hw_thermometer_apply(ah); in ath9k_hw_ar9300_set_board_values()
4252 ar9003_hw_thermo_cal_apply(ah); in ath9k_hw_ar9300_set_board_values()
4255 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah, in ath9k_hw_ar9300_set_addac() argument
4283 dx = x - px[ip]; in ar9003_hw_power_interpolate()
4287 if (!hhave || dx > (x - hx)) { in ar9003_hw_power_interpolate()
4296 if (!lhave || dx < (x - lx)) { in ar9003_hw_power_interpolate()
4319 y = -(1 << 30); in ar9003_hw_power_interpolate()
4323 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah, in ar9003_hw_eeprom_get_tgt_pwr() argument
4329 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_eeprom_get_tgt_pwr()
4335 pEepromTargetPwr = eep->calTargetPower2G; in ar9003_hw_eeprom_get_tgt_pwr()
4336 pFreqBin = eep->calTarget_freqbin_2G; in ar9003_hw_eeprom_get_tgt_pwr()
4339 pEepromTargetPwr = eep->calTargetPower5G; in ar9003_hw_eeprom_get_tgt_pwr()
4340 pFreqBin = eep->calTarget_freqbin_5G; in ar9003_hw_eeprom_get_tgt_pwr()
4358 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah, in ar9003_hw_eeprom_get_ht20_tgt_pwr() argument
4365 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_eeprom_get_ht20_tgt_pwr()
4371 pEepromTargetPwr = eep->calTargetPower2GHT20; in ar9003_hw_eeprom_get_ht20_tgt_pwr()
4372 pFreqBin = eep->calTarget_freqbin_2GHT20; in ar9003_hw_eeprom_get_ht20_tgt_pwr()
4375 pEepromTargetPwr = eep->calTargetPower5GHT20; in ar9003_hw_eeprom_get_ht20_tgt_pwr()
4376 pFreqBin = eep->calTarget_freqbin_5GHT20; in ar9003_hw_eeprom_get_ht20_tgt_pwr()
4394 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah, in ar9003_hw_eeprom_get_ht40_tgt_pwr() argument
4401 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_eeprom_get_ht40_tgt_pwr()
4407 pEepromTargetPwr = eep->calTargetPower2GHT40; in ar9003_hw_eeprom_get_ht40_tgt_pwr()
4408 pFreqBin = eep->calTarget_freqbin_2GHT40; in ar9003_hw_eeprom_get_ht40_tgt_pwr()
4411 pEepromTargetPwr = eep->calTargetPower5GHT40; in ar9003_hw_eeprom_get_ht40_tgt_pwr()
4412 pFreqBin = eep->calTarget_freqbin_5GHT40; in ar9003_hw_eeprom_get_ht40_tgt_pwr()
4430 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah, in ar9003_hw_eeprom_get_cck_tgt_pwr() argument
4436 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_eeprom_get_cck_tgt_pwr()
4437 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck; in ar9003_hw_eeprom_get_cck_tgt_pwr()
4438 u8 *pFreqBin = eep->calTarget_freqbin_Cck; in ar9003_hw_eeprom_get_cck_tgt_pwr()
4455 static void ar9003_hw_selfgen_tpc_txpower(struct ath_hw *ah, in ar9003_hw_selfgen_tpc_txpower() argument
4471 REG_WRITE(ah, AR_TPC, val); in ar9003_hw_selfgen_tpc_txpower()
4475 int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray) in ar9003_hw_tx_power_regwrite() argument
4479 REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0); in ar9003_hw_tx_power_regwrite()
4484 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0), in ar9003_hw_tx_power_regwrite()
4491 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1), in ar9003_hw_tx_power_regwrite()
4500 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2), in ar9003_hw_tx_power_regwrite()
4507 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3), in ar9003_hw_tx_power_regwrite()
4514 /* Write the power for duplicated frames - HT40 */ in ar9003_hw_tx_power_regwrite()
4517 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8), in ar9003_hw_tx_power_regwrite()
4526 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ in ar9003_hw_tx_power_regwrite()
4527 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4), in ar9003_hw_tx_power_regwrite()
4535 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5), in ar9003_hw_tx_power_regwrite()
4543 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9), in ar9003_hw_tx_power_regwrite()
4553 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10), in ar9003_hw_tx_power_regwrite()
4563 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) in ar9003_hw_tx_power_regwrite()
4565 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6), in ar9003_hw_tx_power_regwrite()
4573 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7), in ar9003_hw_tx_power_regwrite()
4581 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11), in ar9003_hw_tx_power_regwrite()
4592 static void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq, in ar9003_hw_get_legacy_target_powers() argument
4597 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq, in ar9003_hw_get_legacy_target_powers()
4600 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq, in ar9003_hw_get_legacy_target_powers()
4603 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq, in ar9003_hw_get_legacy_target_powers()
4606 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq, in ar9003_hw_get_legacy_target_powers()
4610 static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq, in ar9003_hw_get_cck_target_powers() argument
4614 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L, in ar9003_hw_get_cck_target_powers()
4617 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq); in ar9003_hw_get_cck_target_powers()
4619 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq); in ar9003_hw_get_cck_target_powers()
4621 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq); in ar9003_hw_get_cck_target_powers()
4624 static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq, in ar9003_hw_get_ht20_target_powers() argument
4628 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq, in ar9003_hw_get_ht20_target_powers()
4631 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19, in ar9003_hw_get_ht20_target_powers()
4634 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq, in ar9003_hw_get_ht20_target_powers()
4637 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq, in ar9003_hw_get_ht20_target_powers()
4640 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq, in ar9003_hw_get_ht20_target_powers()
4643 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq, in ar9003_hw_get_ht20_target_powers()
4646 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq, in ar9003_hw_get_ht20_target_powers()
4649 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq, in ar9003_hw_get_ht20_target_powers()
4652 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq, in ar9003_hw_get_ht20_target_powers()
4655 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq, in ar9003_hw_get_ht20_target_powers()
4658 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq, in ar9003_hw_get_ht20_target_powers()
4661 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq, in ar9003_hw_get_ht20_target_powers()
4664 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq, in ar9003_hw_get_ht20_target_powers()
4667 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq, in ar9003_hw_get_ht20_target_powers()
4671 static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah, in ar9003_hw_get_ht40_target_powers() argument
4680 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq, in ar9003_hw_get_ht40_target_powers()
4683 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19, in ar9003_hw_get_ht40_target_powers()
4687 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq, in ar9003_hw_get_ht40_target_powers()
4690 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq, in ar9003_hw_get_ht40_target_powers()
4693 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq, in ar9003_hw_get_ht40_target_powers()
4696 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq, in ar9003_hw_get_ht40_target_powers()
4699 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq, in ar9003_hw_get_ht40_target_powers()
4702 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq, in ar9003_hw_get_ht40_target_powers()
4705 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq, in ar9003_hw_get_ht40_target_powers()
4708 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq, in ar9003_hw_get_ht40_target_powers()
4711 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq, in ar9003_hw_get_ht40_target_powers()
4714 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq, in ar9003_hw_get_ht40_target_powers()
4717 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq, in ar9003_hw_get_ht40_target_powers()
4720 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq, in ar9003_hw_get_ht40_target_powers()
4724 static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah, in ar9003_hw_get_target_power_eeprom() argument
4730 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_get_target_power_eeprom()
4731 u16 freq = chan->channel; in ar9003_hw_get_target_power_eeprom()
4734 ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2); in ar9003_hw_get_target_power_eeprom()
4736 ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz); in ar9003_hw_get_target_power_eeprom()
4737 ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz); in ar9003_hw_get_target_power_eeprom()
4740 ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2, in ar9003_hw_get_target_power_eeprom()
4749 static int ar9003_hw_cal_pier_get(struct ath_hw *ah, in ar9003_hw_cal_pier_get() argument
4760 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_cal_pier_get()
4761 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_cal_pier_get()
4767 return -1; in ar9003_hw_cal_pier_get()
4775 return -1; in ar9003_hw_cal_pier_get()
4778 pCalPier = &(eep->calFreqPier2G[ipier]); in ar9003_hw_cal_pier_get()
4779 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]); in ar9003_hw_cal_pier_get()
4783 "Invalid 5GHz cal pier index, must be less than %d\n", in ar9003_hw_cal_pier_get()
4785 return -1; in ar9003_hw_cal_pier_get()
4787 pCalPier = &(eep->calFreqPier5G[ipier]); in ar9003_hw_cal_pier_get()
4788 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]); in ar9003_hw_cal_pier_get()
4792 *pcorrection = pCalPierStruct->refPower; in ar9003_hw_cal_pier_get()
4793 *ptemperature = pCalPierStruct->tempMeas; in ar9003_hw_cal_pier_get()
4794 *pvoltage = pCalPierStruct->voltMeas; in ar9003_hw_cal_pier_get()
4795 *pnf_cal = pCalPierStruct->rxTempMeas ? in ar9003_hw_cal_pier_get()
4796 N2DBM(pCalPierStruct->rxNoisefloorCal) : 0; in ar9003_hw_cal_pier_get()
4797 *pnf_power = pCalPierStruct->rxTempMeas ? in ar9003_hw_cal_pier_get()
4798 N2DBM(pCalPierStruct->rxNoisefloorPower) : 0; in ar9003_hw_cal_pier_get()
4803 static void ar9003_hw_power_control_override(struct ath_hw *ah, in ar9003_hw_power_control_override() argument
4809 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_power_control_override()
4812 REG_RMW(ah, AR_PHY_TPC_11_B0, in ar9003_hw_power_control_override()
4815 if (ah->caps.tx_chainmask & BIT(1)) in ar9003_hw_power_control_override()
4816 REG_RMW(ah, AR_PHY_TPC_11_B1, in ar9003_hw_power_control_override()
4819 if (ah->caps.tx_chainmask & BIT(2)) in ar9003_hw_power_control_override()
4820 REG_RMW(ah, AR_PHY_TPC_11_B2, in ar9003_hw_power_control_override()
4825 REG_RMW(ah, AR_PHY_TPC_6_B0, in ar9003_hw_power_control_override()
4828 if (ah->caps.tx_chainmask & BIT(1)) in ar9003_hw_power_control_override()
4829 REG_RMW(ah, AR_PHY_TPC_6_B1, in ar9003_hw_power_control_override()
4832 if (ah->caps.tx_chainmask & BIT(2)) in ar9003_hw_power_control_override()
4833 REG_RMW(ah, AR_PHY_TPC_6_B2, in ar9003_hw_power_control_override()
4842 temp_slope = eep->modalHeader2G.tempSlope; in ar9003_hw_power_control_override()
4844 if (AR_SREV_9550(ah)) { in ar9003_hw_power_control_override()
4845 t[0] = eep->base_ext1.tempslopextension[2]; in ar9003_hw_power_control_override()
4846 t1[0] = eep->base_ext1.tempslopextension[3]; in ar9003_hw_power_control_override()
4847 t2[0] = eep->base_ext1.tempslopextension[4]; in ar9003_hw_power_control_override()
4850 t[1] = eep->modalHeader5G.tempSlope; in ar9003_hw_power_control_override()
4851 t1[1] = eep->base_ext1.tempslopextension[0]; in ar9003_hw_power_control_override()
4852 t2[1] = eep->base_ext1.tempslopextension[1]; in ar9003_hw_power_control_override()
4855 t[2] = eep->base_ext1.tempslopextension[5]; in ar9003_hw_power_control_override()
4856 t1[2] = eep->base_ext1.tempslopextension[6]; in ar9003_hw_power_control_override()
4857 t2[2] = eep->base_ext1.tempslopextension[7]; in ar9003_hw_power_control_override()
4870 if ((eep->baseEepHeader.miscConfiguration & 0x20) != 0) { in ar9003_hw_power_control_override()
4872 t[i] = eep->base_ext1.tempslopextension[i]; in ar9003_hw_power_control_override()
4873 f[i] = FBIN2FREQ(eep->calFreqPier5G[i], 0); in ar9003_hw_power_control_override()
4877 } else if (eep->base_ext2.tempSlopeLow != 0) { in ar9003_hw_power_control_override()
4878 t[0] = eep->base_ext2.tempSlopeLow; in ar9003_hw_power_control_override()
4880 t[1] = eep->modalHeader5G.tempSlope; in ar9003_hw_power_control_override()
4882 t[2] = eep->base_ext2.tempSlopeHigh; in ar9003_hw_power_control_override()
4887 temp_slope = eep->modalHeader5G.tempSlope; in ar9003_hw_power_control_override()
4892 if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ar9003_hw_power_control_override()
4893 u8 txmask = (eep->baseEepHeader.txrxMask & 0xf0) >> 4; in ar9003_hw_power_control_override()
4899 if (eep->baseEepHeader.featureEnable & 0x1) { in ar9003_hw_power_control_override()
4902 REG_RMW_FIELD(ah, AR_PHY_TPC_19, in ar9003_hw_power_control_override()
4904 eep->base_ext2.tempSlopeLow); in ar9003_hw_power_control_override()
4906 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, in ar9003_hw_power_control_override()
4910 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, in ar9003_hw_power_control_override()
4912 eep->base_ext2.tempSlopeHigh); in ar9003_hw_power_control_override()
4915 REG_RMW_FIELD(ah, AR_PHY_TPC_19, in ar9003_hw_power_control_override()
4919 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, in ar9003_hw_power_control_override()
4923 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, in ar9003_hw_power_control_override()
4933 REG_RMW_FIELD(ah, AR_PHY_TPC_19, in ar9003_hw_power_control_override()
4936 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, in ar9003_hw_power_control_override()
4939 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, in ar9003_hw_power_control_override()
4943 REG_RMW_FIELD(ah, AR_PHY_TPC_19, in ar9003_hw_power_control_override()
4947 if (AR_SREV_9462_20_OR_LATER(ah)) in ar9003_hw_power_control_override()
4948 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, in ar9003_hw_power_control_override()
4952 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE, in ar9003_hw_power_control_override()
4957 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency) in ar9003_hw_calibration_apply() argument
4974 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_calibration_apply()
4989 if (!ar9003_hw_cal_pier_get(ah, is2ghz, ipier, ichain, in ar9003_hw_calibration_apply()
4993 fdiff = frequency - pfrequency; in ar9003_hw_calibration_apply()
5003 (frequency - hfrequency[ichain])) { in ar9003_hw_calibration_apply()
5021 (frequency - lfrequency[ichain])) { in ar9003_hw_calibration_apply()
5058 else if (frequency - lfrequency[ichain] < 1000) { in ar9003_hw_calibration_apply()
5060 if (hfrequency[ichain] - frequency < 1000) { in ar9003_hw_calibration_apply()
5102 else if (hfrequency[ichain] - frequency < 1000) { in ar9003_hw_calibration_apply()
5117 ar9003_hw_power_control_override(ah, frequency, correction, voltage, in ar9003_hw_calibration_apply()
5127 ah->nf_2g.cal[ichain] = nf_cal[ichain]; in ar9003_hw_calibration_apply()
5128 ah->nf_2g.pwr[ichain] = nf_pwr[ichain]; in ar9003_hw_calibration_apply()
5130 ah->nf_5g.cal[ichain] = nf_cal[ichain]; in ar9003_hw_calibration_apply()
5131 ah->nf_5g.pwr[ichain] = nf_pwr[ichain]; in ar9003_hw_calibration_apply()
5142 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G; in ar9003_hw_get_direct_edge_power()
5143 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; in ar9003_hw_get_direct_edge_power()
5157 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G; in ar9003_hw_get_indirect_edge_power()
5158 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; in ar9003_hw_get_indirect_edge_power()
5161 &eep->ctl_freqbin_2G[idx][0] : in ar9003_hw_get_indirect_edge_power()
5162 &eep->ctl_freqbin_5G[idx][0]; in ar9003_hw_get_indirect_edge_power()
5165 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq && in ar9003_hw_get_indirect_edge_power()
5166 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1])) in ar9003_hw_get_indirect_edge_power()
5167 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]); in ar9003_hw_get_indirect_edge_power()
5169 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq && in ar9003_hw_get_indirect_edge_power()
5170 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1])) in ar9003_hw_get_indirect_edge_power()
5171 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]); in ar9003_hw_get_indirect_edge_power()
5185 &eep->ctl_freqbin_2G[idx][0] : in ar9003_hw_get_max_edge_power()
5186 &eep->ctl_freqbin_5G[idx][0]; in ar9003_hw_get_max_edge_power()
5212 * Leave loop - no more affecting edges possible in in ar9003_hw_get_max_edge_power()
5225 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, in ar9003_hw_set_power_per_rate_table() argument
5231 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_set_power_per_rate_table()
5232 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep; in ar9003_hw_set_power_per_rate_table()
5252 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar9003_hw_set_power_per_rate_table()
5253 scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit, in ar9003_hw_set_power_per_rate_table()
5260 ARRAY_SIZE(ctlModesFor11g) - in ar9003_hw_set_power_per_rate_table()
5269 numCtlModes = ARRAY_SIZE(ctlModesFor11a) - in ar9003_hw_set_power_per_rate_table()
5273 /* All 5G CTL's */ in ar9003_hw_set_power_per_rate_table()
5296 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n", in ar9003_hw_set_power_per_rate_table()
5302 ctlIndex = pEepData->ctlIndex_2G; in ar9003_hw_set_power_per_rate_table()
5305 ctlIndex = pEepData->ctlIndex_5G; in ar9003_hw_set_power_per_rate_table()
5312 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n", in ar9003_hw_set_power_per_rate_table()
5314 chan->channel); in ar9003_hw_set_power_per_rate_table()
5353 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n", in ar9003_hw_set_power_per_rate_table()
5378 if (ath9k_hw_mci_is_enabled(ah)) in ar9003_hw_set_power_per_rate_table()
5381 ar9003_mci_get_max_txpower(ah, in ar9003_hw_set_power_per_rate_table()
5391 if (ath9k_hw_mci_is_enabled(ah)) in ar9003_hw_set_power_per_rate_table()
5394 ar9003_mci_get_max_txpower(ah, in ar9003_hw_set_power_per_rate_table()
5411 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2; in mcsidx_to_tgtpwridx()
5414 static void ar9003_paprd_set_txpower(struct ath_hw *ah, in ar9003_paprd_set_txpower() argument
5420 if (!ar9003_is_paprd_enabled(ah)) in ar9003_paprd_set_txpower()
5429 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && in ar9003_paprd_set_txpower()
5430 !AR_SREV_9462(ah) && !AR_SREV_9565(ah)) { in ar9003_paprd_set_txpower()
5438 ah->paprd_target_power = targetPowerValT2[i]; in ar9003_paprd_set_txpower()
5441 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, in ath9k_hw_ar9300_set_txpower() argument
5446 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); in ath9k_hw_ar9300_set_txpower()
5447 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_ar9300_set_txpower()
5457 * Get target powers from EEPROM - our baseline for TX Power in ath9k_hw_ar9300_set_txpower()
5459 ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2); in ath9k_hw_ar9300_set_txpower()
5461 if (ar9003_is_paprd_enabled(ah)) { in ath9k_hw_ar9300_set_txpower()
5462 ah->paprd_ratemask = in ath9k_hw_ar9300_set_txpower()
5463 ar9003_get_paprd_rate_mask_ht20(ah, IS_CHAN_2GHZ(chan)) & in ath9k_hw_ar9300_set_txpower()
5466 ah->paprd_ratemask_ht40 = in ath9k_hw_ar9300_set_txpower()
5467 ar9003_get_paprd_rate_mask_ht40(ah, IS_CHAN_2GHZ(chan)) & in ath9k_hw_ar9300_set_txpower()
5470 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan); in ath9k_hw_ar9300_set_txpower()
5474 if (!ah->paprd_table_write_done) { in ath9k_hw_ar9300_set_txpower()
5479 if (ah->paprd_ratemask & (1 << i)) { in ath9k_hw_ar9300_set_txpower()
5483 targetPowerValT2[pwr_idx] -= in ath9k_hw_ar9300_set_txpower()
5492 ar9003_hw_set_power_per_rate_table(ah, chan, in ath9k_hw_ar9300_set_txpower()
5500 if (ar9003_is_paprd_enabled(ah)) { in ath9k_hw_ar9300_set_txpower()
5502 if ((ah->paprd_ratemask & (1 << i)) && in ath9k_hw_ar9300_set_txpower()
5503 (abs(targetPowerValT2[i] - in ath9k_hw_ar9300_set_txpower()
5506 ah->paprd_ratemask &= ~(1 << i); in ath9k_hw_ar9300_set_txpower()
5513 regulatory->max_power_level = 0; in ath9k_hw_ar9300_set_txpower()
5515 if (targetPowerValT2[i] > regulatory->max_power_level) in ath9k_hw_ar9300_set_txpower()
5516 regulatory->max_power_level = targetPowerValT2[i]; in ath9k_hw_ar9300_set_txpower()
5519 ath9k_hw_update_regulatory_maxpower(ah); in ath9k_hw_ar9300_set_txpower()
5530 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2); in ath9k_hw_ar9300_set_txpower()
5531 ar9003_hw_calibration_apply(ah, chan->channel); in ath9k_hw_ar9300_set_txpower()
5532 ar9003_paprd_set_txpower(ah, chan, targetPowerValT2); in ath9k_hw_ar9300_set_txpower()
5534 ar9003_hw_selfgen_tpc_txpower(ah, chan, targetPowerValT2); in ath9k_hw_ar9300_set_txpower()
5537 if (ah->tpc_enabled) { in ath9k_hw_ar9300_set_txpower()
5540 ar9003_hw_init_rate_txpower(ah, targetPowerValT2_tpc, chan); in ath9k_hw_ar9300_set_txpower()
5543 REG_WRITE(ah, AR_PHY_PWRTX_MAX, in ath9k_hw_ar9300_set_txpower()
5546 val = REG_READ(ah, AR_PHY_POWER_TX_SUB); in ath9k_hw_ar9300_set_txpower()
5547 if (AR_SREV_9340(ah)) in ath9k_hw_ar9300_set_txpower()
5548 REG_WRITE(ah, AR_PHY_POWER_TX_SUB, in ath9k_hw_ar9300_set_txpower()
5551 REG_WRITE(ah, AR_PHY_POWER_TX_SUB, in ath9k_hw_ar9300_set_txpower()
5555 REG_WRITE(ah, AR_PHY_PWRTX_MAX, 0); in ath9k_hw_ar9300_set_txpower()
5559 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah, in ath9k_hw_ar9300_get_spur_channel() argument
5565 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah) in ar9003_hw_get_tx_gain_idx() argument
5567 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_get_tx_gain_idx()
5569 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */ in ar9003_hw_get_tx_gain_idx()
5572 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah) in ar9003_hw_get_rx_gain_idx() argument
5574 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_get_rx_gain_idx()
5576 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */ in ar9003_hw_get_rx_gain_idx()
5579 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz) in ar9003_get_spur_chan_ptr() argument
5581 return ar9003_modal_header(ah, is2ghz)->spurChans; in ar9003_get_spur_chan_ptr()
5584 u32 ar9003_get_paprd_rate_mask_ht20(struct ath_hw *ah, bool is2ghz) in ar9003_get_paprd_rate_mask_ht20() argument
5586 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->papdRateMaskHt20); in ar9003_get_paprd_rate_mask_ht20()
5589 u32 ar9003_get_paprd_rate_mask_ht40(struct ath_hw *ah, bool is2ghz) in ar9003_get_paprd_rate_mask_ht40() argument
5591 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->papdRateMaskHt40); in ar9003_get_paprd_rate_mask_ht40()
5594 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah, in ar9003_get_paprd_scale_factor() argument
5600 return MS(ar9003_get_paprd_rate_mask_ht20(ah, is2ghz), in ar9003_get_paprd_scale_factor()
5603 if (chan->channel >= 5700) in ar9003_get_paprd_scale_factor()
5604 return MS(ar9003_get_paprd_rate_mask_ht20(ah, is2ghz), in ar9003_get_paprd_scale_factor()
5606 else if (chan->channel >= 5400) in ar9003_get_paprd_scale_factor()
5607 return MS(ar9003_get_paprd_rate_mask_ht40(ah, is2ghz), in ar9003_get_paprd_scale_factor()
5610 return MS(ar9003_get_paprd_rate_mask_ht40(ah, is2ghz), in ar9003_get_paprd_scale_factor()
5615 static u8 ar9003_get_eepmisc(struct ath_hw *ah) in ar9003_get_eepmisc() argument
5617 return ah->eeprom.ar9300_eep.baseEepHeader.opCapFlags.eepMisc; in ar9003_get_eepmisc()