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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dstarfive,jh7110-mmc.yaml65 reg = <0x16010000 0x10000>;
74 data-addr = <0>;
/freebsd/contrib/opencsd/decoder/source/i_dec/
H A Dtrc_idec_arminst.cpp48 if ((inst & 0xf0000000) == 0xf0000000) { in inst_ARM_is_direct_branch()
50 if ((inst & 0xfe000000) == 0xfa000000){ in inst_ARM_is_direct_branch()
53 is_direct_branch = 0; in inst_ARM_is_direct_branch()
55 } else if ((inst & 0x0e000000) == 0x0a000000) { in inst_ARM_is_direct_branch()
58 is_direct_branch = 0; in inst_ARM_is_direct_branch()
65 if ( ((inst & 0xf0000000) != 0xf0000000) && in inst_ARM_wfiwfe()
66 ((inst & 0x0ffffffe) == 0x0320f002) in inst_ARM_wfiwfe()
70 return 0; in inst_ARM_wfiwfe()
76 if ((inst & 0xf0000000) == 0xf0000000) { in inst_ARM_is_indirect_branch()
78 if ((inst & 0xfe500000) == 0xf8100000) { in inst_ARM_is_indirect_branch()
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/
H A Dr92c_tx_desc.h28 #define R92C_FLAGS0_BMCAST 0x01
29 #define R92C_FLAGS0_LSG 0x04
30 #define R92C_FLAGS0_FSG 0x08
31 #define R92C_FLAGS0_OWN 0x80
34 #define R92C_TXDW1_MACID_M 0x0000001f
35 #define R92C_TXDW1_MACID_S 0
36 #define R92C_TXDW1_AGGEN 0x00000020
37 #define R92C_TXDW1_AGGBK 0x00000040
39 #define R92C_TXDW1_QSEL_M 0x00001f00
42 #define R92C_TXDW1_QSEL_BE 0x00 /* or 0x03 */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/edac/
H A Dapm-xgene-edac.txt53 reg = <0x0 0x7e200000 0x0 0x1000>;
58 reg = <0x0 0x7e700000 0x0 0x1000>;
63 reg = <0x0 0x7e720000 0x0 0x1000>;
68 reg = <0x0 0x1054a000 0x0 0x20>;
73 reg = <0x0 0x7e000000 0x0 0x10>;
86 reg = <0x0 0x78800000 0x0 0x100>;
87 interrupts = <0x0 0x20 0x4>,
88 <0x0 0x21 0x4>,
89 <0x0 0x27 0x4>;
93 reg = <0x0 0x7e800000 0x0 0x1000>;
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7921/
H A Dpci.c20 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
22 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
24 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
26 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
65 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ in __mt7921_reg_addr()
66 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ in __mt7921_reg_addr()
67 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ in __mt7921_reg_addr()
68 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ in __mt7921_reg_addr()
69 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ in __mt7921_reg_addr()
70 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ in __mt7921_reg_addr()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm2711.dtsi21 #clock-cells = <0>;
28 #clock-cells = <0>;
41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
42 <0x7c000000 0x0 0xfc00000
[all...]
/freebsd/contrib/llvm-project/lld/ELF/
H A DAArch64ErrataFix.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
54 // | 1 | immlo (2) | 1 | 0 0 0 0 | immhi (19) | Rd (5) |
56 return (instr & 0x9f000000) == 0x90000000; in isADRP()
63 // All loads and stores have 1 (at bit position 27), (0 at bit position 25).
64 // | op0 x op1 (2) | 1 op2 0 op3 (2) | x | op4 (5) | xxxx | op5 (2) | x (10) |
66 return (instr & 0x0a000000) == 0x08000000; in isLoadStoreClass()
70 // | 0 Q 00 | 1100 | 0 L 00 | 0000 | opcode (4) | size (2) | Rn (5) | Rt (5) |
72 // | 0 Q 00 | 1100 | 1 L 0 | Rm (5)| opcode (4) | size (2) | Rn (5) | Rt (5) |
73 // L == 0 for stores.
82 return (instr & 0x0000f000) == 0x00002000 || in isST1MultipleOpcode()
[all …]
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DHexagon.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
56 defaultMaxPageSize = 0x10000; in Hexagon()
71 return ret.value_or(/* Default Arch Rev: */ 0x60); in calcEFlags()
75 uint32_t result = 0; in applyMask()
76 size_t off = 0; in applyMask()
78 for (size_t bit = 0; bit != 32; ++bit) { in applyMask()
170 {0x38000000, 0x0000201f}, {0x39000000, 0x0000201f},
171 {0x3e000000, 0x00001f80}, {0x3f000000, 0x00001f80},
172 {0x40000000, 0x000020f8}, {0x41000000, 0x000007e0},
173 {0x42000000, 0x000020f8}, {0x43000000, 0x000007e0},
[all …]
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Ddfmul.S3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
10 #define A r1:0
70 ATMP = combine(##0x40000000,#0)
93 BTMP = combine(##BIAS+BIAS-4,#0)
98 p1 = cmp.eq(PP_LL_L,#0) // 64 lsb's 0?
99 p1 = cmp.eq(PP_ODD_L,#0) // 64 lsb's 0?
102 // PP_HH can have a maximum of 0x3FFF_FFFF_FFFF_FFFF or thereabouts
103 // PP_HH can have a minimum of 0x1000_0000_0000_0000 or so
143 // Fortunately, this is pretty easy to detect, we must have +/- 0x0010_0000_0000_0000
147 // Note: BTMPL should have 0x7FEFFFFF
[all …]
H A Ddffma.S3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
15 #define A r1:0
80 // Next, unpack mantissa into 0x1000_0000_0000_0000 + mant<<8
88 // PP_HH can have a maximum of 0x03FF_FFFF_FFFF_FFFF or thereabouts
89 // PP_HH can have a minimum of 0x0100_0000_0000_0000
91 // 0x0100_0000_0000_0000 has EXP of EXPA+EXPB-BIAS
115 ATMP = #0
116 BTMP = #0
121 PP_ODD_H = ##0x10000000
133 CTMP = combine(PP_ODD_H,#0)
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Dmmio.c15 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
16 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
17 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
18 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
19 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
20 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
21 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
22 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
23 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
24 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
[all …]
H A Dregs.h42 #define MT_MCU_INT_EVENT 0x2108
43 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
48 #define MT_PLE_BASE 0x820c0000
51 #define MT_FL_Q_EMPTY MT_PLE(0x360)
52 #define MT_FL_Q0_CTRL MT_PLE(0x3e0)
53 #define MT_FL_Q2_CTRL MT_PLE(0x3e8)
54 #define MT_FL_Q3_CTRL MT_PLE(0x3ec)
56 #define MT_PLE_FREEPG_CNT MT_PLE(0x380)
57 #define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(0x384)
58 #define MT_PLE_PG_HIF_GROUP MT_PLE(0x00c)
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dregs.h37 #define MT_HW_REV MT_HW_INFO(0x000)
38 #define MT_HW_CHIPID MT_HW_INFO(0x008)
39 #define MT_TOP_STRAP_STA MT_HW_INFO(0x010)
42 #define MT_TOP_OFF_RSV 0x1128
45 #define MT_TOP_MISC2 ((dev)->reg_map[MT_TOP_CFG_BASE] + 0x134)
46 #define MT_TOP_MISC2_FW_STATE GENMASK(2, 0)
51 #define MT_MCU_BASE 0x2000
54 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)
55 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
57 #define MT_PCIE_REMAP_BASE_1 0x40000
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apm/
H A Dapm-shadowcat.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
26 clocks = <&pmd0clk 0>;
31 reg = <0x0 0x001>;
33 cpu-release-addr = <0x
[all...]
H A Dapm-storm.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
29 reg = <0x0 0x001>;
31 cpu-release-addr = <0x1 0x0000fff
[all...]
/freebsd/sys/dev/usb/controller/
H A Ddwc_otgreg.h32 #define DOTG_GOTGCTL 0x0000
33 #define DOTG_GOTGINT 0x0004
34 #define DOTG_GAHBCFG 0x0008
35 #define DOTG_GUSBCFG 0x000C
36 #define DOTG_GRSTCTL 0x0010
37 #define DOTG_GINTSTS 0x0014
38 #define DOTG_GINTMSK 0x0018
39 #define DOTG_GRXSTSRD 0x001C
40 #define DOTG_GRXSTSRH 0x001C
41 #define DOTG_GRXSTSPD 0x0020
[all …]
/freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/aes/
H A Daestab2.h49 0x00000001, 0x00000002, 0x00000004, 0x00000008,
50 0x00000010, 0x00000020, 0x00000040, 0x00000080,
51 0x0000001b, 0x00000036
57 0x00000063, 0x0000007c, 0x00000077, 0x0000007b,
58 0x000000f2, 0x0000006b, 0x0000006f, 0x000000c5,
59 0x00000030, 0x00000001, 0x00000067, 0x0000002b,
60 0x000000fe, 0x000000d7, 0x000000ab, 0x00000076,
61 0x000000ca, 0x00000082, 0x000000c9, 0x0000007d,
62 0x000000fa, 0x00000059, 0x00000047, 0x000000f0,
63 0x000000ad, 0x000000d4, 0x000000a2, 0x000000af,
[all …]
/freebsd/sys/dev/rl/
H A Dif_rlreg.h36 #define RL_IDR0 0x0000 /* ID register 0 (station addr) */
37 #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
38 #define RL_IDR2 0x0002
39 #define RL_IDR3 0x0003
40 #define RL_IDR4 0x0004
41 #define RL_IDR5 0x0005
43 #define RL_MAR0 0x0008 /* Multicast hash table */
44 #define RL_MAR1 0x0009
45 #define RL_MAR2 0x000A
46 #define RL_MAR3 0x000B
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dmmio.c21 [INT_SOURCE_CSR] = 0xd7010,
22 [INT_MASK_CSR] = 0xd7014,
23 [INT1_SOURCE_CSR] = 0xd7088,
24 [INT1_MASK_CSR] = 0xd708c,
25 [INT_MCU_CMD_SOURCE] = 0xd51f0,
26 [INT_MCU_CMD_EVENT] = 0x3108,
27 [WFDMA0_ADDR] = 0xd4000,
28 [WFDMA0_PCIE1_ADDR] = 0xd8000,
29 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
30 [CBTOP1_PHY_END] = 0x77ffffff,
[all …]
H A Dregs.h129 #define MT_MCU_WFDMA0_BASE 0x2000
132 #define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120)
135 #define MT_MCU_WFDMA1_BASE 0x3000
139 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
145 #define MT_PLE_BASE 0x820c0000
148 #define MT_PLE_HOST_RPT0 MT_PLE(0x030)
153 #define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8)
154 #define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc)
164 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
166 #define MT_PSE_BASE 0x820c8000
[all …]
/freebsd/sys/powerpc/powerpc/
H A Ddb_disasm.c17 Op_A = 0x00000001,
18 Op_B = 0x00000002,
19 Op_BI = 0x00000004,
20 Op_BO = 0x00000008,
22 Op_CRM = 0x00000010,
23 Op_D = 0x00000020,
24 Op_ST = 0x00000020, /* Op_S for store-operations, same as D */
25 Op_S = 0x00000040, /* S-field is swapped with A-field */
27 Op_dA = 0x00000080,
28 Op_LK = 0x00000100,
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300phy.h55 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
58 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
59 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
61 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
64 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
68 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
71 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
73 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
74 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
75 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
[all …]
/freebsd/tests/sys/cddl/zfs/tests/txg_integrity/
H A Dtxg_integrity.c84 #define USE_MMAP 0
90 //partitions[-1] is understood to be 0 and partitions[NUM_CHUNKS] must be 1.0
94 //8 / (NUM_CHUNKS * CLUSTERSIZE) = 1 / 524288 = 0x0.00002
98 //chunk 0 corresponds to bit 1, chunk 1 to bit 2, etc
106 if (chunk == 0){ in get_chunk_range()
107 *begin = 0; in get_chunk_range()
117 leader_syncs = 0,
125 {0x2000000, 0x4000000, 0x6000000, 0x8000000, 0xa000000, 0xc000000, 0xe000000, 0x10000000,
126 0x12000000, 0x14000000, 0x16000000, 0x18000000, 0x1a000000, 0x1c000000, 0x1e000000, 0x20000000,
127 0x22000000, 0x24000000, 0x26000000, 0x28000000, 0x2a000000, 0x2c000000, 0x2e000000, 0x30000000,
[all …]
H A Dfsync_integrity.c61 * Every even-numbered thread, starting with the first (0th), will fsync()
98 //partitions[-1] is understood to be 0 and partitions[NUM_CHUNKS] must be 1.0
102 //8 / (NUM_CHUNKS * CLUSTERSIZE) = 1 / 524288 = 0x0.00002
116 if (chunk == 0){ in get_chunk_range()
117 *begin = 0; in get_chunk_range()
129 {0x2000000, 0x4000000, 0x6000000, 0x8000000, 0xa000000, 0xc000000, 0xe000000, 0x10000000,
130 0x12000000, 0x14000000, 0x16000000, 0x18000000, 0x1a000000, 0x1c000000, 0x1e000000, 0x20000000,
131 0x22000000, 0x24000000, 0x26000000, 0x28000000, 0x2a000000, 0x2c000000, 0x2e000000, 0x30000000,
132 0x32000000, 0x34000000, 0x36000000, 0x38000000, 0x3a000000, 0x3c000000, 0x3e000000, 0x40000000,
133 0x42000000, 0x44000000, 0x46000000, 0x48000000, 0x4a000000, 0x4c000000, 0x4e000000, 0x50000000,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepMask.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
17 0xf0000000,
18 0xb0000000,
19 0x0fe03fe0,
20 0 },
23 0xffc00000,
24 0x76000000,
25 0x00203fe0,
26 0 },
29 0xff800000,
[all …]

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