3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
54 // | 1 | immlo (2) | 1 | 0 0 0 0 | immhi (19) | Rd (5) |
56   return (instr & 0x9f000000) == 0x90000000;  in isADRP()
63 // All loads and stores have 1 (at bit position 27), (0 at bit position 25).
64 // | op0 x op1 (2) | 1 op2 0 op3 (2) | x | op4 (5) | xxxx | op5 (2) | x (10) |
66   return (instr & 0x0a000000) == 0x08000000;  in isLoadStoreClass()
70 // | 0 Q 00 | 1100 | 0 L 00 | 0000 | opcode (4) | size (2) | Rn (5) | Rt (5) |
72 // | 0 Q 00 | 1100 | 1 L 0 | Rm (5)| opcode (4) | size (2) | Rn (5) | Rt (5) |
73 // L == 0 for stores.
82   return (instr & 0x0000f000) == 0x00002000 ||  in isST1MultipleOpcode()
83          (instr & 0x0000f000) == 0x00006000 ||  in isST1MultipleOpcode()
84          (instr & 0x0000f000) == 0x00007000 ||  in isST1MultipleOpcode()
85          (instr & 0x0000f000) == 0x0000a000;  in isST1MultipleOpcode()
89   return (instr & 0xbfff0000) == 0x0c000000 && isST1MultipleOpcode(instr);  in isST1Multiple()
94   return (instr & 0xbfe00000) == 0x0c800000 && isST1MultipleOpcode(instr);  in isST1MultiplePost()
98 // | 0 Q 00 | 1101 | 0 L R 0 | 0000 | opc (3) S | size (2) | Rn (5) | Rt (5)|
100 // | 0 Q 00 | 1101 | 1 L R | Rm (5) | opc (3) S | size (2) | Rn (5) | Rt (5)|
101 // L == 0 for stores
105 // R == 0 for ST1 and ST3, R == 1 for ST2 and ST4.
110   return (instr & 0x0040e000) == 0x00000000 ||  in isST1SingleOpcode()
111          (instr & 0x0040e000) == 0x00004000 ||  in isST1SingleOpcode()
112          (instr & 0x0040e000) == 0x00008000;  in isST1SingleOpcode()
116   return (instr & 0xbfff0000) == 0x0d000000 && isST1SingleOpcode(instr);  in isST1Single()
121   return (instr & 0xbfe00000) == 0x0d800000 && isST1SingleOpcode(instr);  in isST1SinglePost()
131 // L == 0 for Stores.
133   return (instr & 0x3f000000) == 0x08000000;  in isLoadStoreExclusive()
137   return (instr & 0x3f400000) == 0x08400000;  in isLoadExclusive()
143   return (instr & 0x3b000000) == 0x18000000;  in isLoadLiteral()
148 // | opc (2) 10 | 1 V 00 | 0 L | imm7 | Rt2 (5) | Rn (5) | Rt (5) |
149 // L == 0 for stores.
152   return (instr & 0x3bc00000) == 0x28000000;  in isSTNP()
158 // L == 0 for stores, V == 0 for Scalar, V == 1 for Simd/FP
161   return (instr & 0x3bc00000) == 0x28800000;  in isSTPPost()
165 // | opc (2) 10 | 1 V 01 | 0 L | imm7 | Rt2 (5) | Rn (5) | Rt (5) |
167   return (instr & 0x3bc00000) == 0x29000000;  in isSTPOffset()
174   return (instr & 0x3bc00000) == 0x29800000;  in isSTPPre()
182 // | size (2) 11 | 1 V 00 | opc (2) 0 | imm9 | 00 | Rn (5) | Rt (5) |
183 // V == 0 for Scalar, V == 1 for Simd/FP.
185   return (instr & 0x3b000c00) == 0x38000000;  in isLoadStoreUnscaled()
189 // | size (2) 11 | 1 V 00 | opc (2) 0 | imm9 | 01 | Rn (5) | Rt (5) |
191   return (instr & 0x3b200c00) == 0x38000400;  in isLoadStoreImmediatePost()
195 // | size (2) 11 | 1 V 00 | opc (2) 0 | imm9 | 10 | Rn (5) | Rt (5) |
197   return (instr & 0x3b200c00) == 0x38000800;  in isLoadStoreUnpriv()
201 // | size (2) 11 | 1 V 00 | opc (2) 0 | imm9 | 11 | Rn (5) | Rt (5) |
203   return (instr & 0x3b200c00) == 0x38000c00;  in isLoadStoreImmediatePre()
209   return (instr & 0x3b200c00) == 0x38200800;  in isLoadStoreRegisterOff()
215   return (instr & 0x3b000000) == 0x39000000;  in isLoadStoreRegisterUnsigned()
218 // Rt is always in bit position 0 - 4.
219 static uint32_t getRt(uint32_t instr) { return (instr & 0x1f); }  in getRt()
222 static uint32_t getRn(uint32_t instr) { return (instr >> 5) & 0x1f; }  in getRn()
226 // op0 == 010 101 op1 == 0xxx Conditional Branch.
229 // op0 == x01 101 op1 == 0xxx Compare and branch immediate.
232   return ((instr & 0xfe000000) == 0xd6000000) || // Cond branch.  in isBranch()
233          ((instr & 0xfe000000) == 0x54000000) || // Uncond branch reg.  in isBranch()
234          ((instr & 0x7c000000) == 0x14000000) || // Uncond branch imm.  in isBranch()
235          ((instr & 0x7c000000) == 0x34000000);   // Compare and test branch.  in isBranch()
244 // Note that this function refers to v8.0 only and does not include the
256     uint32_t size = (instr >> 30) & 0xff;  in isV8NonStructureLoad()
257     uint32_t v = (instr >> 26) & 0x1;  in isV8NonStructureLoad()
258     uint32_t opc = (instr >> 22) & 0x3;  in isV8NonStructureLoad()
260     // Opc == 0 are all stores.  in isV8NonStructureLoad()
262     // Size == 00 (0), V == 1, Opc == 10 (2) which is a store and  in isV8NonStructureLoad()
263     // Size == 11 (3), V == 0, Opc == 10 (2) which is a prefetch.  in isV8NonStructureLoad()
264     return opc != 0 && !(size == 0 && v == 1 && opc == 2) &&  in isV8NonStructureLoad()
265            !(size == 3 && v == 0 && opc == 2);  in isV8NonStructureLoad()
289 // Full details are available in the Cortex A53 MPCore revision 0 Software
300 //     address of instruction either 0xff8 or 0xffc.
336 // patch or 0 if no patch required.
339   uint64_t isecAddr = isec->getVA(0);  in scanCortexA53Errata843419()
341   // Advance Off so that (isecAddr + Off) modulo 0x1000 is at least 0xff8.  in scanCortexA53Errata843419()
342   uint64_t initialPageOff = (isecAddr + off) & 0xfff;  in scanCortexA53Errata843419()
343   if (initialPageOff < 0xff8)  in scanCortexA53Errata843419()
344     off += 0xff8 - initialPageOff;  in scanCortexA53Errata843419()
350     return 0;  in scanCortexA53Errata843419()
353   uint64_t patchOff = 0;  in scanCortexA53Errata843419()
366   if (((isecAddr + off) & 0xfff) == 0xff8)  in scanCortexA53Errata843419()
369     off += 0xffc;  in scanCortexA53Errata843419()
402       0, getSize(), *this);  in Patch843419Section()
403   addSyntheticLocal(saver().save("$x"), STT_NOTYPE, 0, 0, *this);  in Patch843419Section()
457   // the same type. For example we must remove the redundant $d.1 from $x.0  in init()
458   // $d.0 $d.1 $x.1.  in init()
515   SmallVector<InputSection *, 0> tmp;  in insertPatches()
562     return Relocation{R_PC, R_AARCH64_JUMP26, offset, 0, patchSym};  in implementPatch()
566     ps->addReloc({relIt->expr, relIt->type, 0, relIt->addend, relIt->sym});  in implementPatch()