Lines Matching +full:0 +full:x7c000000
32 #define DOTG_GOTGCTL 0x0000
33 #define DOTG_GOTGINT 0x0004
34 #define DOTG_GAHBCFG 0x0008
35 #define DOTG_GUSBCFG 0x000C
36 #define DOTG_GRSTCTL 0x0010
37 #define DOTG_GINTSTS 0x0014
38 #define DOTG_GINTMSK 0x0018
39 #define DOTG_GRXSTSRD 0x001C
40 #define DOTG_GRXSTSRH 0x001C
41 #define DOTG_GRXSTSPD 0x0020
42 #define DOTG_GRXSTSPH 0x0020
43 #define DOTG_GRXFSIZ 0x0024
44 #define DOTG_GNPTXFSIZ 0x0028
45 #define DOTG_GNPTXSTS 0x002C
46 #define DOTG_GI2CCTL 0x0030
47 #define DOTG_GPVNDCTL 0x0034
48 #define DOTG_GGPIO 0x0038
49 #define DOTG_GUID 0x003C
50 #define DOTG_GSNPSID 0x0040
51 #define DOTG_GSNPSID_REV_2_80a 0x4f54280a /* RPi model B/RPi2 */
52 #define DOTG_GSNPSID_REV_3_10a 0x4f54310a /* ODROID-C1 */
53 #define DOTG_GHWCFG1 0x0044
54 #define DOTG_GHWCFG2 0x0048
55 #define DOTG_GHWCFG3 0x004C
56 #define DOTG_GHWCFG4 0x0050
57 #define DOTG_GLPMCFG 0x0054
58 #define DOTG_GPWRDN 0x0058
59 #define DOTG_GDFIFOCFG 0x005C
60 #define DOTG_GADPCTL 0x0060
62 #define DOTG_HPTXFSIZ 0x0100
63 /* start from 0x104, but fifo0 not exists */
64 #define DOTG_DPTXFSIZ(fifo) (0x0100 + (4*(fifo)))
65 #define DOTG_DIEPTXF(fifo) (0x0100 + (4*(fifo)))
67 #define DOTG_HCFG 0x0400
68 #define DOTG_HFIR 0x0404
69 #define DOTG_HFNUM 0x0408
70 #define DOTG_HPTXSTS 0x0410
71 #define DOTG_HAINT 0x0414
72 #define DOTG_HAINTMSK 0x0418
73 #define DOTG_HPRT 0x0440
75 #define DOTG_HCCHAR(ch) (0x0500 + (32*(ch)))
76 #define DOTG_HCSPLT(ch) (0x0504 + (32*(ch)))
77 #define DOTG_HCINT(ch) (0x0508 + (32*(ch)))
78 #define DOTG_HCINTMSK(ch) (0x050C + (32*(ch)))
79 #define DOTG_HCTSIZ(ch) (0x0510 + (32*(ch)))
80 #define DOTG_HCDMA(ch) (0x0514 + (32*(ch)))
81 #define DOTG_HCDMAI(ch) (0x0514 + (32*(ch)))
82 #define DOTG_HCDMAO(ch) (0x0514 + (32*(ch)))
83 #define DOTG_HCDMAB(ch) (0x051C + (32*(ch)))
86 #define DOTG_DCFG 0x0800
87 #define DOTG_DCTL 0x0804
88 #define DOTG_DSTS 0x0808
89 #define DOTG_DIEPMSK 0x0810
90 #define DOTG_DOEPMSK 0x0814
91 #define DOTG_DAINT 0x0818
92 #define DOTG_DAINTMSK 0x081C
93 #define DOTG_DTKNQR1 0x0820
94 #define DOTG_DTKNQR2 0x0824
95 #define DOTG_DVBUSDIS 0x0828
96 #define DOTG_DVBUSPULSE 0x082C
97 #define DOTG_DTHRCTL 0x0830
98 #define DOTG_DTKNQR4 0x0834
99 #define DOTG_DIEPEMPMSK 0x0834
100 #define DOTG_DEACHINT 0x0838
101 #define DOTG_DEACHINTMSK 0x083C
102 #define DOTG_DIEPEACHINTMSK(ch) (0x0840 + (4*(ch)))
103 #define DOTG_DOEPEACHINTMSK(ch) (0x0880 + (4*(ch)))
105 #define DOTG_DIEPCTL(ep) (0x0900 + (32*(ep)))
106 #define DOTG_DIEPINT(ep) (0x0908 + (32*(ep)))
107 #define DOTG_DIEPTSIZ(ep) (0x0910 + (32*(ep)))
108 #define DOTG_DIEPDMA(ep) (0x0914 + (32*(ep)))
109 #define DOTG_DTXFSTS(ep) (0x0918 + (32*(ep)))
110 #define DOTG_DIEPDMAB(ep) (0x091c + (32*(ep)))
112 #define DOTG_DOEPCTL(ep) (0x0B00 + (32*(ep)))
113 #define DOTG_DOEPFN(ep) (0x0B04 + (32*(ep)))
114 #define DOTG_DOEPINT(ep) (0x0B08 + (32*(ep)))
115 #define DOTG_DOEPTSIZ(ep) (0x0B10 + (32*(ep)))
116 #define DOTG_DOEPDMA(ep) (0x0B14 + (32*(ep)))
117 #define DOTG_DOEPDMAB(ep) (0x0B1c + (32*(ep)))
121 #define DOTG_CTL_STATUS 0x0800
122 #define DOTG_DMA0_INB_CHN0 0x0818
123 #define DOTG_DMA0_INB_CHN1 0x0820
124 #define DOTG_DMA0_INB_CHN2 0x0828
125 #define DOTG_DVBUSDIS 0x0828
126 #define DOTG_DVBUSPULSE 0x082c
127 #define DOTG_DMA0_INB_CHN3 0x0830
128 #define DOTG_DMA0_INB_CHN4 0x0838
129 #define DOTG_DMA0_INB_CHN5 0x0840
130 #define DOTG_DMA0_INB_CHN6 0x0848
131 #define DOTG_DMA0_INB_CHN7 0x0850
132 #define DOTG_DMA0_OUTB_CHN0 0x0858
133 #define DOTG_DMA0_OUTB_CHN1 0x0860
134 #define DOTG_DMA0_OUTB_CHN2 0x0868
135 #define DOTG_DMA0_OUTB_CHN3 0x0870
136 #define DOTG_DMA0_OUTB_CHN4 0x0878
137 #define DOTG_DMA0_OUTB_CHN5 0x0880
138 #define DOTG_DMA0_OUTB_CHN6 0x0888
139 #define DOTG_DMA0_OUTB_CHN7 0x0890
144 #define DOTG_PCGCCTL 0x0E00
148 #define DOTG_DFIFO(n) (0x1000 + (0x1000 * (n)))
160 #define GOTGCTL_SESREQSCS (1<<0)
172 #define GAHBCFG_HBSTLEN_MASK 0x0000001e
174 #define GAHBCFG_GLBLINTRMSK (1<<0)
189 #define GUSBCFG_USBTRDTIM_MASK 0x00003c00
199 #define GUSBCFG_TOUTCAL_MASK 0x00000007
200 #define GUSBCFG_TOUTCAL_SHIFT 0
212 #define GRSTCTL_TXFNUM_MASK 0x000007c0
220 #define GRSTCTL_CSFTRST (1<<0)
253 #define GINTSTS_CURMOD (1<<0)
283 #define GINTMSK_CURMODMSK (1<<0)
285 #define GRXSTSRH_PKTSTS_MASK 0x001e0000
287 #define GRXSTSRH_DPID_MASK 0x00018000
289 #define GRXSTSRH_BCNT_MASK 0x00007ff0
291 #define GRXSTSRH_CHNUM_MASK 0x0000000f
292 #define GRXSTSRH_CHNUM_SHIFT 0
294 #define GRXSTSRD_FN_MASK 0x01e00000
297 #define GRXSTSRD_PKTSTS_MASK 0x001e0000
308 #define GRXSTSRD_DPID_MASK 0x00018000
310 #define GRXSTSRD_DPID_DATA0 (0<<15)
314 #define GRXSTSRD_BCNT_MASK 0x00007ff0
315 #define GRXSTSRD_BCNT_GET(x) (((x) >> 4) & 0x7FF)
317 #define GRXSTSRD_CHNUM_MASK 0x0000000f
319 #define GRXSTSRD_CHNUM_SHIFT 0
321 #define GRXFSIZ_RXFDEP_MASK 0x0000ffff
322 #define GRXFSIZ_RXFDEP_SHIFT 0
324 #define GNPTXFSIZ_NPTXFDEP_MASK 0xffff0000
325 #define GNPTXFSIZ_NPTXFDEP_SHIFT 0
326 #define GNPTXFSIZ_NPTXFSTADDR_MASK 0x0000ffff
330 #define GNPTXSTS_NPTXQTOP_MASK 0x7f000000
332 #define GNPTXSTS_NPTXQSPCAVAIL_MASK 0x00ff0000
333 #define GNPTXSTS_NPTXFSPCAVAIL_SHIFT 0
334 #define GNPTXSTS_NPTXFSPCAVAIL_MASK 0x0000ffff
340 #define GI2CCTL_I2CDEVADR_MASK 0x0c000000
345 #define GI2CCTL_ADDR_MASK 0x007f0000
347 #define GI2CCTL_REGADDR_MASK 0x0000ff00
348 #define GI2CCTL_RWDATA_SHIFT 0
349 #define GI2CCTL_RWDATA_MASK 0x000000ff
357 #define GPVNDCTL_REGADDR_MASK 0x003f0000
359 #define GPVNDCTL_VCTRL_MASK 0x0000ff00
360 #define GPVNDCTL_REGDATA_SHIFT 0
361 #define GPVNDCTL_REGDATA_MASK 0x000000ff
364 #define GGPIO_GPO_MASK 0xffff0000
365 #define GGPIO_GPI_SHIFT 0
366 #define GGPIO_GPI_MASK 0x0000ffff
369 #define GHWCFG1_BIDIR 0
374 #define GHWCFG2_TKNQDEPTH_MASK 0x7c000000
376 #define GHWCFG2_PTXQDEPTH_MASK 0x03000000
378 #define GHWCFG2_NPTXQDEPTH_MASK 0x00c00000
383 #define GHWCFG2_NUMHSTCHNL_MASK 0x0003c000
386 #define GHWCFG2_NUMDEVEPS_MASK 0x00003c00
389 #define GHWCFG2_FSPHYTYPE_MASK 0x00000300
391 #define GHWCFG2_HSPHYTYPE_MASK 0x000000c0
394 #define GHWCFG2_OTGARCH_MASK 0x00000018
395 #define GHWCFG2_OTGMODE_SHIFT 0
396 #define GHWCFG2_OTGMODE_MASK 0x00000007
399 #define GHWCFG3_DFIFODEPTH_MASK 0xffff0000
407 #define GHWCFG3_PKTSIZEWIDTH_MASK 0x00000070
408 #define GHWCFG3_PKTSIZE_GET(x) (0x10<<(((x) >> 4) & 7))
409 #define GHWCFG3_XFERSIZEWIDTH_SHIFT 0
410 #define GHWCFG3_XFERSIZEWIDTH_MASK 0x0000000f
411 #define GHWCFG3_XFRRSIZE_GET(x) (0x400<<(((x) >> 0) & 15))
420 #define GHWCFG4_NUMCTLEPS_MASK 0x000f0000
423 #define GHWCFG4_PHYDATAWIDTH_MASK 0x0000c000
426 #define GHWCFG4_NUMDEVPERIOEPS_SHIFT 0
427 #define GHWCFG4_NUMDEVPERIOEPS_MASK 0x0000000f
428 #define GHWCFG4_NUMDEVPERIOEPS_GET(x) (((x) >> 0) & 15)
448 #define GPWRDN_PMU_IRQ_SEL (1<<0)
451 #define HPTXFSIZ_PTXFSIZE_MASK 0xffff0000
452 #define HPTXFSIZ_PTXFSTADDR_SHIFT 0
453 #define HPTXFSIZ_PTXFSTADDR_MASK 0x0000ffff
456 #define DPTXFSIZN_DPTXFSIZE_MASK 0xffff0000
457 #define DPTXFSIZN_PTXFSTADDR_SHIFT 0
458 #define DPTXFSIZN_PTXFSTADDR_MASK 0x0000ffff
461 #define DIEPTXFN_INEPNTXFDEP_MASK 0xffff0000
462 #define DIEPTXFN_INEPNTXFSTADDR_SHIFT 0
463 #define DIEPTXFN_INEPNTXFSTADDR_MASK 0x0000ffff
468 #define HCFG_FLENTRIES_MASK 0x03000000
469 #define HCFG_FLENTRIES_8 (0)
476 #define HCFG_FSLSPCLKSEL_SHIFT 0
477 #define HCFG_FSLSPCLKSEL_MASK 0x00000003
480 #define HFIR_FRINT_SHIFT 0
481 #define HFIR_FRINT_MASK 0x0000ffff
484 #define HFNUM_FRREM_MASK 0xffff0000
485 #define HFNUM_FRNUM_SHIFT 0
486 #define HFNUM_FRNUM_MASK 0x0000ffff
490 #define HPTXSTS_CHAN_MASK 0x78000000
492 #define HPTXSTS_TOKEN_MASK 0x06000000
493 #define HPTXSTS_TOKEN_ZL 0
498 #define HPTXSTS_PTXQSPCAVAIL_MASK 0x00ff0000
499 #define HPTXSTS_PTXFSPCAVAIL_SHIFT 0
500 #define HPTXSTS_PTXFSPCAVAIL_MASK 0x0000ffff
502 #define HAINT_HAINT_SHIFT 0
503 #define HAINT_HAINT_MASK 0x0000ffff
504 #define HAINTMSK_HAINTMSK_SHIFT 0
505 #define HAINTMSK_HAINTMSK_MASK 0x0000ffff
508 #define HPRT_PRTSPD_MASK 0x00060000
509 #define HPRT_PRTSPD_HIGH 0
512 #define HPRT_PRTSPD_MASK 0x00060000
514 #define HPRT_PRTTSTCTL_MASK 0x0001e000
517 #define HPRT_PRTLNSTS_MASK 0x00000c00
526 #define HPRT_PRTCONNSTS (1<<0)
532 #define HCCHAR_DEVADDR_MASK 0x1fc00000
534 #define HCCHAR_MC_MASK 0x00300000
536 #define HCCHAR_EPTYPE_MASK 0x000c0000
540 #define HCCHAR_EPDIR_OUT 0
542 #define HCCHAR_EPNUM_MASK 0x00007800
543 #define HCCHAR_MPS_SHIFT 0
544 #define HCCHAR_MPS_MASK 0x000007ff
549 #define HCSPLT_XACTPOS_MASK 0x0000c000
550 #define HCSPLT_XACTPOS_MIDDLE 0
556 #define HCSPLT_HUBADDR_MASK 0x00003f80
557 #define HCSPLT_PRTADDR_SHIFT 0
558 #define HCSPLT_PRTADDR_MASK 0x0000007f
584 #define HCINT_XFERCOMPL (1<<0)
596 #define HCINTMSK_XFERCOMPLMSK (1<<0)
600 #define HCTSIZ_PID_MASK 0x60000000
601 #define HCTSIZ_PID_DATA0 0
607 #define HCTSIZ_PKTCNT_MASK 0x1ff80000
608 #define HCTSIZ_XFERSIZE_SHIFT 0
609 #define HCTSIZ_XFERSIZE_MASK 0x0007ffff
612 #define DCFG_EPMISCNT_MASK 0x007c0000
614 #define DCFG_PERFRINT_MASK 0x00001800
616 #define DCFG_DEVADDR_MASK 0x000007f0
617 #define DCFG_DEVADDR_SET(x) (((x) & 0x7F) << 4)
619 #define DCFG_DEVSPD_SHIFT 0
620 #define DCFG_DEVSPD_MASK 0x00000003
621 #define DCFG_DEVSPD_SET(x) ((x) & 0x3)
622 #define DCFG_DEVSPD_HI 0
632 #define DCTL_TSTCTL_MASK 0x00000070
636 #define DCTL_RMTWKUPSIG (1<<0)
639 #define DSTS_SOFFN_MASK 0x003fff00
640 #define DSTS_SOFFN_GET(x) (((x) >> 8) & 0x3FFF)
643 #define DSTS_ENUMSPD_MASK 0x00000006
645 #define DSTS_ENUMSPD_HI 0
649 #define DSTS_SUSPSTS (1<<0)
659 #define DIEPMSK_XFERCOMPLMSK (1<<0)
668 #define DOEPMSK_XFERCOMPLMSK (1<<0)
677 #define DIEPINT_XFERCOMPL (1<<0)
685 #define DOEPINT_XFERCOMPL (1<<0)
687 #define DAINT_INEPINT_MASK 0xffff0000
688 #define DAINT_INEPINT_SHIFT 0
689 #define DAINT_OUTEPINT_MASK 0x0000ffff
692 #define DAINTMSK_INEPINT_MASK 0xffff0000
693 #define DAINTMSK_INEPINT_SHIFT 0
694 #define DAINTMSK_OUTEPINT_MASK 0x0000ffff
698 #define DTKNQR1_EPTKN_MASK 0xffffff00
700 #define DTKNQR1_INTKNWPTR_SHIFT 0
701 #define DTKNQR1_INTKNWPTR_MASK 0x0000001f
703 #define DVBUSDIS_DVBUSDIS_SHIFT 0
704 #define DVBUSDIS_DVBUSDIS_MASK 0x0000ffff
706 #define DVBUSPULSE_DVBUSPULSE_SHIFT 0
707 #define DVBUSPULSE_DVBUSPULSE_MASK 0x00000fff
711 #define DTHRCTL_RXTHRLEN_MASK 0x03fe0000
714 #define DTHRCTL_TXTHRLEN_MASK 0x000007fc
716 #define DTHRCTL_NONISOTHREN (1<<0)
718 #define DIEPEMPMSK_INEPTXFEMPMSK_SHIFT 0
719 #define DIEPEMPMSK_INEPTXFEMPMSK_MASK 0x0000ffff
728 #define DIEPCTL_TXFNUM_MASK 0x03c00000
732 #define DIEPCTL_EPTYPE_MASK 0x000c0000
734 #define DIEPCTL_EPTYPE_CONTROL 0
741 #define DIEPCTL_NEXTEP_MASK 0x00007800
742 #define DIEPCTL_MPS_SHIFT 0
743 #define DIEPCTL_MPS_MASK 0x000007ff
744 #define DIEPCTL_MPS_SET(n) ((n) & 0x7FF)
745 #define DIEPCTL_MPS_64 (0<<0)
746 #define DIEPCTL_MPS_32 (1<<0)
747 #define DIEPCTL_MPS_16 (2<<0)
748 #define DIEPCTL_MPS_8 (3<<0)
759 #define DOEPCTL_EPTYPE_MASK 0x000c0000
763 #define DOEPCTL_MPS_SHIFT 0
764 #define DOEPCTL_MPS_MASK 0x000007ff
765 #define DOEPCTL_MPS_SET(n) ((n) & 0x7FF)
766 #define DOEPCTL_MPS_64 (0<<0)
767 #define DOEPCTL_MPS_32 (1<<0)
768 #define DOEPCTL_MPS_16 (2<<0)
769 #define DOEPCTL_MPS_8 (3<<0)
774 #define DXEPINT_XFER_COMPL (1<<0)
776 #define DIEPTSIZ_XFERSIZE_MASK 0x0007ffff
777 #define DIEPTSIZ_XFERSIZE_SHIFT 0
778 #define DIEPTSIZ_PKTCNT_MASK 0x1ff80000
780 #define DIEPTSIZ_MC_MASK 0x60000000
783 #define DOEPTSIZ_XFERSIZE_MASK 0x0007ffff
784 #define DOEPTSIZ_XFERSIZE_SHIFT 0
785 #define DOEPTSIZ_PKTCNT_MASK 0x1ff80000
787 #define DOEPTSIZ_MC_MASK 0x60000000
792 #define DXEPTSIZ_SET_NPKT(n) (((n) & 0x3FF) << 19)
793 #define DXEPTSIZ_GET_NPKT(n) (((n) >> 19) & 0x3FF)
794 #define DXEPTSIZ_SET_NBYTES(n) (((n) & 0x7FFFFF) << 0)
795 #define DXEPTSIZ_GET_NBYTES(n) (((n) >> 0) & 0x7FFFFF)
801 (0x10000U << ((x) & 15U)))