Lines Matching +full:0 +full:x7c000000
42 #define MT_MCU_INT_EVENT 0x2108
43 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
48 #define MT_PLE_BASE 0x820c0000
51 #define MT_FL_Q_EMPTY MT_PLE(0x360)
52 #define MT_FL_Q0_CTRL MT_PLE(0x3e0)
53 #define MT_FL_Q2_CTRL MT_PLE(0x3e8)
54 #define MT_FL_Q3_CTRL MT_PLE(0x3ec)
56 #define MT_PLE_FREEPG_CNT MT_PLE(0x380)
57 #define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(0x384)
58 #define MT_PLE_PG_HIF_GROUP MT_PLE(0x00c)
59 #define MT_PLE_HIF_PG_INFO MT_PLE(0x388)
61 #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x600 + 0x80 * (ac) + ((n) << 2))
62 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
65 #define MT_MDP_BASE 0x820cc000
68 #define MT_MDP_DCR2 MT_MDP(0x8e8)
71 /* TMAC: band 0(0x820e4000), band 1(0x820f4000), band 2(0x830e4000) */
75 #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0)
78 #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x0c8)
79 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x0cc)
80 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
83 #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x014)
84 #define MT_IFS_EIFS_OFDM GENMASK(8, 0)
89 #define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, 0x018)
90 #define MT_IFS_EIFS_CCK GENMASK(8, 0)
92 /* WF DMA TOP: band 0(0x820e7000), band 1(0x820f7000), band 2(0x830e7000) */
96 #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000)
99 #define MT_DMA_TCRF1(_band) MT_WF_DMA(_band, 0x054)
102 /* WTBLOFF TOP: band 0(0x820e9000), band 1(0x820f9000), band 2(0x830e9000) */
106 #define MT_WTBLOFF_RSCR(_band) MT_WTBLOFF(_band, 0x008)
110 /* ETBF: band 0(0x820ea000), band 1(0x820fa000), band 2(0x830ea000) */
114 #define MT_ETBF_RX_FB_CONT(_band) MT_WF_ETBF(_band, 0x100)
117 #define MT_ETBF_RX_FB_NR GENMASK(3, 0)
119 /* LPON: band 0(0x820eb000), band 1(0x820fb000), band 2(0x830eb000) */
123 #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x360)
124 #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x364)
125 #define MT_LPON_FRCR(_band) MT_WF_LPON(_band, 0x37c)
127 #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (((n) * 4) << 4))
128 #define MT_LPON_TCR_SW_MODE GENMASK(1, 0)
129 #define MT_LPON_TCR_SW_WRITE BIT(0)
131 #define MT_LPON_TCR_SW_READ GENMASK(1, 0)
133 /* MIB: band 0(0x820ed000), band 1(0x820fd000), band 2(0x830ed000)*/
143 #define MT_MIB_BSCR0(_band) MT_WF_MIB(_band, 0x9cc)
144 #define MT_MIB_BSCR1(_band) MT_WF_MIB(_band, 0x9d0)
145 #define MT_MIB_BSCR2(_band) MT_WF_MIB(_band, 0x9d4)
146 #define MT_MIB_BSCR3(_band) MT_WF_MIB(_band, 0x9d8)
147 #define MT_MIB_BSCR4(_band) MT_WF_MIB(_band, 0x9dc)
148 #define MT_MIB_BSCR5(_band) MT_WF_MIB(_band, 0x9e0)
149 #define MT_MIB_BSCR6(_band) MT_WF_MIB(_band, 0x9e4)
150 #define MT_MIB_BSCR7(_band) MT_WF_MIB(_band, 0x9e8)
151 #define MT_MIB_BSCR17(_band) MT_WF_MIB(_band, 0xa10)
153 #define MT_MIB_TSCR5(_band) MT_WF_MIB(_band, 0x6c4)
154 #define MT_MIB_TSCR6(_band) MT_WF_MIB(_band, 0x6c8)
155 #define MT_MIB_TSCR7(_band) MT_WF_MIB(_band, 0x6d0)
157 #define MT_MIB_RSCR1(_band) MT_WF_MIB(_band, 0x7ac)
159 #define MT_MIB_RSCR31(_band) MT_WF_MIB(_band, 0x964)
160 #define MT_MIB_RSCR33(_band) MT_WF_MIB(_band, 0x96c)
162 #define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020)
163 #define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0)
165 #define MT_MIB_RVSR0(_band) MT_WF_MIB(_band, 0x720)
167 #define MT_MIB_RSCR35(_band) MT_WF_MIB(_band, 0x974)
168 #define MT_MIB_RSCR36(_band) MT_WF_MIB(_band, 0x978)
171 #define MT_MIB_TSCR0(_band) MT_WF_MIB(_band, 0x6b0)
172 #define MT_MIB_TSCR2(_band) MT_WF_MIB(_band, 0x6b8)
175 #define MT_MIB_TSCR3(_band) MT_WF_MIB(_band, 0x6bc)
178 #define MT_MIB_TSCR4(_band) MT_WF_MIB(_band, 0x6c0)
181 #define MT_MIB_RSCR27(_band) MT_WF_MIB(_band, 0x954)
184 #define MT_MIB_RSCR28(_band) MT_WF_MIB(_band, 0x958)
187 #define MT_MIB_RSCR29(_band) MT_WF_MIB(_band, 0x95c)
190 #define MT_MIB_RSCR30(_band) MT_WF_MIB(_band, 0x960)
193 #define MT_MIB_SDR27(_band) MT_WF_MIB(_band, 0x080)
194 #define MT_MIB_SDR27_TX_RWP_FAIL_CNT GENMASK(15, 0)
196 #define MT_MIB_SDR28(_band) MT_WF_MIB(_band, 0x084)
197 #define MT_MIB_SDR28_TX_RWP_NEED_CNT GENMASK(15, 0)
199 #define MT_MIB_RVSR1(_band) MT_WF_MIB(_band, 0x724)
202 #define MT_MIB_TSCR1(_band) MT_WF_MIB(_band, 0x6b4)
204 #define MT_MIB_BTSCR0(_band) MT_WF_MIB(_band, 0x5e0)
205 #define MT_MIB_BTSCR5(_band) MT_WF_MIB(_band, 0x788)
206 #define MT_MIB_BTSCR6(_band) MT_WF_MIB(_band, 0x798)
208 #define MT_MIB_BFTFCR(_band) MT_WF_MIB(_band, 0x5d0)
210 #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0xa28 + ((n) << 2))
211 #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x0b0 + ((n) << 2))
212 #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 4)) & GENMASK(9, 0))
215 #define MT_WF_UMIB_BASE 0x820cd000
218 #define MT_UMIB_RPDCR(_band) (MT_WF_UMIB(0x594) + (_band) * 0x164)
221 #define MT_WTBLON_TOP_BASE 0x820d4000
223 #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x370)
224 #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0)
226 #define MT_WTBL_UPDATE MT_WTBLON_TOP(0x380)
227 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(11, 0)
231 #define MT_WTBL_ITCR MT_WTBLON_TOP(0x3b0)
234 #define MT_WTBL_ITDR0 MT_WTBLON_TOP(0x3b8)
235 #define MT_WTBL_ITDR1 MT_WTBLON_TOP(0x3bc)
239 #define MT_WTBL_BASE 0x820d8000
246 /* ARB: band 0(0x820e3000), band 1(0x820f3000), band 2(0x830e3000) */
250 #define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x000)
254 /* RMAC: band 0(0x820e5000), band 1(0x820f5000), band 2(0x830e5000), */
258 #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000)
259 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
280 #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004)
287 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380)
290 #define MT_WF_RMAC_MIB_OBSS_BACKOFF GENMASK(15, 0)
292 #define MT_WF_RMAC_MIB_AIRTIME1(_band) MT_WF_RMAC(_band, 0x0384)
295 #define MT_WF_RMAC_MIB_AIRTIME3(_band) MT_WF_RMAC(_band, 0x038c)
296 #define MT_WF_RMAC_MIB_QOS01_BACKOFF GENMASK(31, 0)
298 #define MT_WF_RMAC_MIB_AIRTIME4(_band) MT_WF_RMAC(_band, 0x0390)
299 #define MT_WF_RMAC_MIB_QOS23_BACKOFF GENMASK(31, 0)
301 #define MT_WF_RMAC_RSVD0(_band) MT_WF_RMAC(_band, 0x03e0)
304 /* RATE: band 0(0x820ee000), band 1(0x820fe000), band 2(0x830ee000) */
308 #define MT_RATE_HRCR0(_band) MT_WF_RATE(_band, 0x050)
309 #define MT_RATE_HRCR0_CFEND_RATE GENMASK(14, 0)
312 #define MT_WFDMA0_BASE 0xd4000
315 #define MT_WFDMA0_RST MT_WFDMA0(0x100)
319 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)
320 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0)
324 #define MT_WFDMA0_RX_INT_PCIE_SEL MT_WFDMA0(0x154)
327 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4)
329 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
330 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
336 #define WF_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0)
340 #define WF_WFDMA0_GLO_CFG_EXT1 MT_WFDMA0(0x2b4)
344 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
345 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
346 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
347 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
350 #define MT_WFDMA1_BASE 0xd5000
353 #define MT_WFDMA_EXT_CSR_BASE 0xd7000
356 #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30)
357 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0)
359 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44)
360 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)
362 #define MT_PCIE_RECOG_ID 0xd7090
363 #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0)
367 #define MT_WFDMA0_PCIE1_BASE 0xd8000
370 #define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c)
371 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
380 #define MT_Q_BASE(q) ((dev->q_wfdma_mask >> (q)) & 0x1 ? \
387 #define MT_MCUQ_RING_BASE(q) (MT_Q_BASE(q) + 0x300)
388 #define MT_TXQ_RING_BASE(q) (MT_Q_BASE(__TXQ(q)) + 0x300)
389 #define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500)
391 #define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \
392 MT_MCUQ_ID(q) * 0x4)
393 #define MT_RXQ_BAND1_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \
394 MT_RXQ_ID(q) * 0x4)
395 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \
396 MT_TXQ_ID(q) * 0x4)
398 #define MT_INT_SOURCE_CSR MT_WFDMA0(0x200)
399 #define MT_INT_MASK_CSR MT_WFDMA0(0x204)
401 #define MT_INT1_SOURCE_CSR MT_WFDMA0_PCIE1(0x200)
402 #define MT_INT1_MASK_CSR MT_WFDMA0_PCIE1(0x204)
407 #define MT_INT_RX_DONE_WM BIT(0)
449 #define MT_MCU_CMD MT_WFDMA0(0x1f0)
461 #define MT_HIF_REMAP_L1 0x155024
463 #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)
465 #define MT_HIF_REMAP_BASE_L1 0x130000
467 #define MT_HIF_REMAP_L2 0x1b4
468 #define MT_HIF_REMAP_L2_MASK GENMASK(19, 0)
469 #define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0)
471 #define MT_HIF_REMAP_BASE_L2 0x1000
473 #define MT_INFRA_BASE 0x18000000
474 #define MT_WFSYS0_PHY_START 0x18400000
475 #define MT_WFSYS1_PHY_START 0x18800000
476 #define MT_WFSYS1_PHY_END 0x18bfffff
477 #define MT_CBTOP1_PHY_START 0x70000000
478 #define MT_CBTOP1_PHY_END 0x77ffffff
479 #define MT_CBTOP2_PHY_START 0xf0000000
480 #define MT_INFRA_MCU_START 0x7c000000
481 #define MT_INFRA_MCU_END 0x7c3fffff
484 #define MT_FW_ASSERT_CNT 0x02208274
485 #define MT_FW_DUMP_STATE 0x02209e90
487 #define MT_SWDEF_BASE 0x00401400
490 #define MT_SWDEF_MODE MT_SWDEF(0x3c)
491 #define MT_SWDEF_NORMAL_MODE 0
493 #define MT_SWDEF_SER_STATS MT_SWDEF(0x040)
494 #define MT_SWDEF_PLE_STATS MT_SWDEF(0x044)
495 #define MT_SWDEF_PLE1_STATS MT_SWDEF(0x048)
496 #define MT_SWDEF_PLE_AMSDU_STATS MT_SWDEF(0x04c)
497 #define MT_SWDEF_PSE_STATS MT_SWDEF(0x050)
498 #define MT_SWDEF_PSE1_STATS MT_SWDEF(0x054)
499 #define MT_SWDEF_LAMC_WISR6_BN0_STATS MT_SWDEF(0x058)
500 #define MT_SWDEF_LAMC_WISR6_BN1_STATS MT_SWDEF(0x05c)
501 #define MT_SWDEF_LAMC_WISR6_BN2_STATS MT_SWDEF(0x060)
502 #define MT_SWDEF_LAMC_WISR7_BN0_STATS MT_SWDEF(0x064)
503 #define MT_SWDEF_LAMC_WISR7_BN1_STATS MT_SWDEF(0x068)
504 #define MT_SWDEF_LAMC_WISR7_BN2_STATS MT_SWDEF(0x06c)
507 #define MT_LED_TOP_BASE 0x18013000
510 #define MT_LED_CTRL(_n) MT_LED_PHYS(0x00 + ((_n) * 4))
515 #define MT_LED_TX_BLINK(_n) MT_LED_PHYS(0x10 + ((_n) * 4))
516 #define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0)
519 #define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4))
522 #define MT_CONN_DBG_CTL_BASE 0x18023000
524 #define MT_CONN_DBG_CTL_OUT_SEL MT_CONN_DBG_CTL(0x604)
525 #define MT_CONN_DBG_CTL_PC_LOG_SEL MT_CONN_DBG_CTL(0x60c)
526 #define MT_CONN_DBG_CTL_PC_LOG MT_CONN_DBG_CTL(0x610)
528 #define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */
529 #define MT_LED_GPIO_MUX3 0x7000505C /* GPIO 26 */
533 #define MT_TOP_BASE 0xe0000
536 #define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10))
537 #define MT_TOP_LPCR_HOST_FW_OWN BIT(0)
541 #define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10))
542 #define MT_TOP_LPCR_HOST_BAND_STAT BIT(0)
544 #define MT_TOP_MISC MT_TOP(0xf0)
545 #define MT_TOP_MISC_FW_STATE GENMASK(2, 0)
547 #define MT_HW_REV 0x70010204
548 #define MT_WF_SUBSYS_RST 0x70028600
551 #define MT_PCIE_MAC_BASE 0x74030000
553 #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188)
555 #define MT_PCIE1_MAC_BASE 0x74090000
558 #define MT_PCIE1_MAC_INT_ENABLE MT_PCIE1_MAC(0x188)
561 #define MT_WF_PHYRX_CSD_BASE 0x83000000
565 #define MT_WF_PHYRX_CSD_IRPI(_band, _wf) MT_WF_PHYRX_CSD(_band, _wf, 0x1000)
568 #define MT_WF_PHYRX_BAND_BASE 0x83080000
572 #define MT_WF_PHYRX_BAND_GID_TAB_VLD0(_band) MT_WF_PHYRX_BAND(_band, 0x1054)
573 #define MT_WF_PHYRX_BAND_GID_TAB_VLD1(_band) MT_WF_PHYRX_BAND(_band, 0x1058)
574 #define MT_WF_PHYRX_BAND_GID_TAB_POS0(_band) MT_WF_PHYRX_BAND(_band, 0x105c)
575 #define MT_WF_PHYRX_BAND_GID_TAB_POS1(_band) MT_WF_PHYRX_BAND(_band, 0x1060)
576 #define MT_WF_PHYRX_BAND_GID_TAB_POS2(_band) MT_WF_PHYRX_BAND(_band, 0x1064)
577 #define MT_WF_PHYRX_BAND_GID_TAB_POS3(_band) MT_WF_PHYRX_BAND(_band, 0x1068)
579 #define MT_WF_PHYRX_BAND_RX_CTRL1(_band) MT_WF_PHYRX_BAND(_band, 0x2004)
580 #define MT_WF_PHYRX_BAND_RX_CTRL1_IPI_EN GENMASK(2, 0)
584 #define MT_WF_PHYRX_CSD_BAND_RXTD12(_band) MT_WF_PHYRX_BAND(_band, 0x8230)
589 #define MT_MCU_WM_EXCP_BASE 0x89050000
591 #define MT_MCU_WM_EXCP_PC_CTRL MT_MCU_WM_EXCP(0x100)
592 #define MT_MCU_WM_EXCP_PC_LOG MT_MCU_WM_EXCP(0x104)
593 #define MT_MCU_WM_EXCP_LR_CTRL MT_MCU_WM_EXCP(0x200)
594 #define MT_MCU_WM_EXCP_LR_LOG MT_MCU_WM_EXCP(0x204)