Lines Matching +full:0 +full:x7c000000
36 #define RL_IDR0 0x0000 /* ID register 0 (station addr) */
37 #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
38 #define RL_IDR2 0x0002
39 #define RL_IDR3 0x0003
40 #define RL_IDR4 0x0004
41 #define RL_IDR5 0x0005
43 #define RL_MAR0 0x0008 /* Multicast hash table */
44 #define RL_MAR1 0x0009
45 #define RL_MAR2 0x000A
46 #define RL_MAR3 0x000B
47 #define RL_MAR4 0x000C
48 #define RL_MAR5 0x000D
49 #define RL_MAR6 0x000E
50 #define RL_MAR7 0x000F
52 #define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */
53 #define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */
54 #define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */
55 #define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */
57 #define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */
58 #define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */
59 #define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */
60 #define RL_TXADDR3 0x002C /* address of TX descriptor 3 */
62 #define RL_RXADDR 0x0030 /* RX ring start address */
63 #define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */
64 #define RL_RX_EARLY_STAT 0x0036 /* RX early status */
65 #define RL_COMMAND 0x0037 /* command register */
66 #define RL_CURRXADDR 0x0038 /* current address of packet read */
67 #define RL_CURRXBUF 0x003A /* current RX buffer address */
68 #define RL_IMR 0x003C /* interrupt mask register */
69 #define RL_ISR 0x003E /* interrupt status register */
70 #define RL_TXCFG 0x0040 /* transmit config */
71 #define RL_RXCFG 0x0044 /* receive config */
72 #define RL_TIMERCNT 0x0048 /* timer count register */
73 #define RL_MISSEDPKT 0x004C /* missed packet counter */
74 #define RL_EECMD 0x0050 /* EEPROM command register */
77 #define RL_8139_CFG0 0x0051 /* config register #0 */
78 #define RL_8139_CFG1 0x0052 /* config register #1 */
79 #define RL_8139_CFG3 0x0059 /* config register #3 */
80 #define RL_8139_CFG4 0x005A /* config register #4 */
81 #define RL_8139_CFG5 0x00D8 /* config register #5 */
83 #define RL_CFG0 0x0051 /* config register #0 */
84 #define RL_CFG1 0x0052 /* config register #1 */
85 #define RL_CFG2 0x0053 /* config register #2 */
86 #define RL_CFG3 0x0054 /* config register #3 */
87 #define RL_CFG4 0x0055 /* config register #4 */
88 #define RL_CFG5 0x0056 /* config register #5 */
90 #define RL_MEDIASTAT 0x0058 /* media status register (8139) */
92 #define RL_MII 0x005A /* 8129 chip only */
93 #define RL_HALTCLK 0x005B
94 #define RL_MULTIINTR 0x005C /* multiple interrupt */
95 #define RL_PCIREV 0x005E /* PCI revision value */
97 #define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */
100 #define RL_BMCR 0x0062 /* PHY basic mode control */
101 #define RL_BMSR 0x0064 /* PHY basic mode status */
102 #define RL_ANAR 0x0066 /* PHY autoneg advert */
103 #define RL_LPAR 0x0068 /* PHY link partner ability */
104 #define RL_ANER 0x006A /* PHY autoneg expansion */
106 #define RL_DISCCNT 0x006C /* disconnect counter */
107 #define RL_FALSECAR 0x006E /* false carrier counter */
108 #define RL_NWAYTST 0x0070 /* NWAY test register */
109 #define RL_RX_ER 0x0072 /* RX_ER counter */
110 #define RL_CSCFG 0x0074 /* CS configuration register */
117 #define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */
118 #define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */
119 #define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */
120 #define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */
121 #define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */
122 #define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */
123 #define RL_CFG2 0x0053
124 #define RL_TIMERINT 0x0054 /* interrupt on timer expire */
125 #define RL_TXSTART 0x00D9 /* 8 bits */
126 #define RL_CPLUS_CMD 0x00E0 /* 16 bits */
127 #define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */
128 #define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */
129 #define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */
134 #define RL_GTXSTART 0x0038 /* 8 bits */
135 #define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */
136 #define RL_PHYAR 0x0060
137 #define RL_TBICSR 0x0064
138 #define RL_TBI_ANAR 0x0068
139 #define RL_TBI_LPAR 0x006A
140 #define RL_GMEDIASTAT 0x006C /* 8 bits */
141 #define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */
142 #define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */
143 #define RL_PMCH 0x006F /* 8 bits */
144 #define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
145 #define RL_INTRMOD 0x00E2 /* 16 bits */
146 #define RL_MISC 0x00F0
151 #define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
152 #define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
153 #define RL_TXCFG_QUEUE_EMPTY 0x00000800 /* 8168E-VL or higher */
154 #define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
155 #define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
156 #define RL_TXCFG_IFG2 0x00080000 /* 8169 only */
157 #define RL_TXCFG_IFG 0x03000000 /* interframe gap */
158 #define RL_TXCFG_HWREV 0x7CC00000
160 #define RL_LOOPTEST_OFF 0x00000000
161 #define RL_LOOPTEST_ON 0x00020000
162 #define RL_LOOPTEST_ON_CPLUS 0x00060000
165 #define RL_HWREV_8169 0x00000000
166 #define RL_HWREV_8169S 0x00800000
167 #define RL_HWREV_8110S 0x04000000
168 #define RL_HWREV_8169_8110SB 0x10000000
169 #define RL_HWREV_8169_8110SC 0x18000000
170 #define RL_HWREV_8401E 0x24000000
171 #define RL_HWREV_8102EL 0x24800000
172 #define RL_HWREV_8102EL_SPIN1 0x24C00000
173 #define RL_HWREV_8168D 0x28000000
174 #define RL_HWREV_8168DP 0x28800000
175 #define RL_HWREV_8168E 0x2C000000
176 #define RL_HWREV_8168E_VL 0x2C800000
177 #define RL_HWREV_8168B_SPIN1 0x30000000
178 #define RL_HWREV_8100E 0x30800000
179 #define RL_HWREV_8101E 0x34000000
180 #define RL_HWREV_8102E 0x34800000
181 #define RL_HWREV_8103E 0x34C00000
182 #define RL_HWREV_8168B_SPIN2 0x38000000
183 #define RL_HWREV_8168B_SPIN3 0x38400000
184 #define RL_HWREV_8168C 0x3C000000
185 #define RL_HWREV_8168C_SPIN2 0x3C400000
186 #define RL_HWREV_8168CP 0x3C800000
187 #define RL_HWREV_8105E 0x40800000
188 #define RL_HWREV_8105E_SPIN1 0x40C00000
189 #define RL_HWREV_8402 0x44000000
190 #define RL_HWREV_8106E 0x44800000
191 #define RL_HWREV_8168F 0x48000000
192 #define RL_HWREV_8411 0x48800000
193 #define RL_HWREV_8168G 0x4C000000
194 #define RL_HWREV_8168EP 0x50000000
195 #define RL_HWREV_8168GU 0x50800000
196 #define RL_HWREV_8168H 0x54000000
197 #define RL_HWREV_8168FP 0x54800000
198 #define RL_HWREV_8411B 0x5C800000
199 #define RL_HWREV_8139 0x60000000
200 #define RL_HWREV_8139A 0x70000000
201 #define RL_HWREV_8139AG 0x70800000
202 #define RL_HWREV_8139B 0x78000000
203 #define RL_HWREV_8130 0x7C000000
204 #define RL_HWREV_8139C 0x74000000
205 #define RL_HWREV_8139D 0x74400000
206 #define RL_HWREV_8139CPLUS 0x74800000
207 #define RL_HWREV_8101 0x74C00000
208 #define RL_HWREV_8100 0x78800000
209 #define RL_HWREV_8169_8110SBL 0x7CC00000
210 #define RL_HWREV_8169_8110SCE 0x98000000
212 #define RL_TXDMA_16BYTES 0x00000000
213 #define RL_TXDMA_32BYTES 0x00000100
214 #define RL_TXDMA_64BYTES 0x00000200
215 #define RL_TXDMA_128BYTES 0x00000300
216 #define RL_TXDMA_256BYTES 0x00000400
217 #define RL_TXDMA_512BYTES 0x00000500
218 #define RL_TXDMA_1024BYTES 0x00000600
219 #define RL_TXDMA_2048BYTES 0x00000700
224 #define RL_TXSTAT_LENMASK 0x00001FFF
225 #define RL_TXSTAT_OWN 0x00002000
226 #define RL_TXSTAT_TX_UNDERRUN 0x00004000
227 #define RL_TXSTAT_TX_OK 0x00008000
228 #define RL_TXSTAT_EARLY_THRESH 0x003F0000
229 #define RL_TXSTAT_COLLCNT 0x0F000000
230 #define RL_TXSTAT_CARR_HBEAT 0x10000000
231 #define RL_TXSTAT_OUTOFWIN 0x20000000
232 #define RL_TXSTAT_TXABRT 0x40000000
233 #define RL_TXSTAT_CARRLOSS 0x80000000
238 #define RL_ISR_RX_OK 0x0001
239 #define RL_ISR_RX_ERR 0x0002
240 #define RL_ISR_TX_OK 0x0004
241 #define RL_ISR_TX_ERR 0x0008
242 #define RL_ISR_RX_OVERRUN 0x0010
243 #define RL_ISR_PKT_UNDERRUN 0x0020
244 #define RL_ISR_LINKCHG 0x0020 /* 8169 only */
245 #define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
246 #define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */
247 #define RL_ISR_SWI 0x0100 /* C+ only */
248 #define RL_ISR_CABLE_LEN_CHGD 0x2000
249 #define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
250 #define RL_ISR_TIMEOUT_EXPIRED 0x4000
251 #define RL_ISR_SYSTEM_ERR 0x8000
273 #define RL_MEDIASTAT_RXPAUSE 0x01
274 #define RL_MEDIASTAT_TXPAUSE 0x02
275 #define RL_MEDIASTAT_LINK 0x04
276 #define RL_MEDIASTAT_SPEED10 0x08
277 #define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */
278 #define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */
283 #define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */
284 #define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */
285 #define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */
286 #define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */
287 #define RL_RXCFG_RX_RUNT 0x00000010
288 #define RL_RXCFG_RX_ERRPKT 0x00000020
289 #define RL_RXCFG_WRAP 0x00000080
290 #define RL_RXCFG_EARLYOFFV2 0x00000800
291 #define RL_RXCFG_MAXDMA 0x00000700
292 #define RL_RXCFG_BUFSZ 0x00001800
293 #define RL_RXCFG_EARLYOFF 0x00003800
294 #define RL_RXCFG_FIFOTHRESH 0x0000E000
295 #define RL_RXCFG_EARLYTHRESH 0x07000000
297 #define RL_RXDMA_16BYTES 0x00000000
298 #define RL_RXDMA_32BYTES 0x00000100
299 #define RL_RXDMA_64BYTES 0x00000200
300 #define RL_RXDMA_128BYTES 0x00000300
301 #define RL_RXDMA_256BYTES 0x00000400
302 #define RL_RXDMA_512BYTES 0x00000500
303 #define RL_RXDMA_1024BYTES 0x00000600
304 #define RL_RXDMA_UNLIMITED 0x00000700
306 #define RL_RXBUF_8 0x00000000
307 #define RL_RXBUF_16 0x00000800
308 #define RL_RXBUF_32 0x00001000
309 #define RL_RXBUF_64 0x00001800
311 #define RL_RXFIFO_16BYTES 0x00000000
312 #define RL_RXFIFO_32BYTES 0x00002000
313 #define RL_RXFIFO_64BYTES 0x00004000
314 #define RL_RXFIFO_128BYTES 0x00006000
315 #define RL_RXFIFO_256BYTES 0x00008000
316 #define RL_RXFIFO_512BYTES 0x0000A000
317 #define RL_RXFIFO_1024BYTES 0x0000C000
318 #define RL_RXFIFO_NOTHRESH 0x0000E000
324 #define RL_RXSTAT_RXOK 0x00000001
325 #define RL_RXSTAT_ALIGNERR 0x00000002
326 #define RL_RXSTAT_CRCERR 0x00000004
327 #define RL_RXSTAT_GIANT 0x00000008
328 #define RL_RXSTAT_RUNT 0x00000010
329 #define RL_RXSTAT_BADSYM 0x00000020
330 #define RL_RXSTAT_BROAD 0x00002000
331 #define RL_RXSTAT_INDIV 0x00004000
332 #define RL_RXSTAT_MULTI 0x00008000
333 #define RL_RXSTAT_LENMASK 0xFFFF0000
334 #define RL_RXSTAT_UNFINISHED 0x0000FFF0 /* DMA still in progress */
339 #define RL_CMD_EMPTY_RXBUF 0x0001
340 #define RL_CMD_TX_ENB 0x0004
341 #define RL_CMD_RX_ENB 0x0008
342 #define RL_CMD_RESET 0x0010
343 #define RL_CMD_STOPREQ 0x0080
349 #define RL_CSCFG_LINK_OK 0x0400
350 #define RL_CSCFG_CHANGE 0x0800
351 #define RL_CSCFG_STATUS 0xf000
352 #define RL_CSCFG_ROW3 0x7000
353 #define RL_CSCFG_ROW2 0x3000
354 #define RL_CSCFG_ROW1 0x1000
355 #define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0
356 #define RL_CSCFG_LINK_DOWN_CMD 0xf3c0
358 #define RL_NWAYTST_RESET 0
359 #define RL_NWAYTST_CBL_TEST 0x20
361 #define RL_PARA78 0x78
362 #define RL_PARA78_DEF 0x78fa8388
363 #define RL_PARA7C 0x7C
364 #define RL_PARA7C_DEF 0xcb38de43
365 #define RL_PARA7C_RETUNE 0xfb38de03
370 #define RL_EE_DATAOUT 0x01 /* Data out */
371 #define RL_EE_DATAIN 0x02 /* Data in */
372 #define RL_EE_CLK 0x04 /* clock */
373 #define RL_EE_SEL 0x08 /* chip select */
374 #define RL_EE_MODE (0x40|0x80)
376 #define RL_EEMODE_OFF 0x00
377 #define RL_EEMODE_AUTOLOAD 0x40
378 #define RL_EEMODE_PROGRAM 0x80
379 #define RL_EEMODE_WRITECFG (0x80|0x40)
385 #define RL_9346_WRITE 0x5
386 #define RL_9346_READ 0x6
387 #define RL_9346_ERASE 0x7
388 #define RL_9346_EWEN 0x4
389 #define RL_9346_EWEN_ADDR 0x30
390 #define RL_9456_EWDS 0x4
391 #define RL_9346_EWDS_ADDR 0x00
393 #define RL_EECMD_WRITE 0x140
394 #define RL_EECMD_READ_6BIT 0x180
395 #define RL_EECMD_READ_8BIT 0x600
396 #define RL_EECMD_ERASE 0x1c0
398 #define RL_EE_ID 0x00
399 #define RL_EE_PCI_VID 0x01
400 #define RL_EE_PCI_DID 0x02
402 #define RL_EE_EADDR 0x07
407 #define RL_MII_CLK 0x01
408 #define RL_MII_DATAIN 0x02
409 #define RL_MII_DATAOUT 0x04
410 #define RL_MII_DIR 0x80 /* 0 == input, 1 == output */
413 * Config 0 register
415 #define RL_CFG0_ROM0 0x01
416 #define RL_CFG0_ROM1 0x02
417 #define RL_CFG0_ROM2 0x04
418 #define RL_CFG0_PL0 0x08
419 #define RL_CFG0_PL1 0x10
420 #define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */
421 #define RL_CFG0_PCS 0x40
422 #define RL_CFG0_SCR 0x80
427 #define RL_CFG1_PWRDWN 0x01
428 #define RL_CFG1_PME 0x01
429 #define RL_CFG1_SLEEP 0x02
430 #define RL_CFG1_VPDEN 0x02
431 #define RL_CFG1_IOMAP 0x04
432 #define RL_CFG1_MEMMAP 0x08
433 #define RL_CFG1_RSVD 0x10
434 #define RL_CFG1_LWACT 0x10
435 #define RL_CFG1_DRVLOAD 0x20
436 #define RL_CFG1_LED0 0x40
437 #define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */
438 #define RL_CFG1_LED1 0x80
443 #define RL_CFG2_PCI33MHZ 0x00
444 #define RL_CFG2_PCI66MHZ 0x01
445 #define RL_CFG2_PCI64BIT 0x08
446 #define RL_CFG2_AUXPWR 0x10
447 #define RL_CFG2_MSI 0x20
452 #define RL_CFG3_GRANTSEL 0x80
453 #define RL_CFG3_WOL_MAGIC 0x20
454 #define RL_CFG3_WOL_LINK 0x10
455 #define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */
456 #define RL_CFG3_FAST_B2B 0x01
461 #define RL_CFG4_LWPTN 0x04
462 #define RL_CFG4_LWPME 0x10
463 #define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */
468 #define RL_CFG5_WOL_BCAST 0x40
469 #define RL_CFG5_WOL_MCAST 0x20
470 #define RL_CFG5_WOL_UCAST 0x10
471 #define RL_CFG5_WOL_LANWAKE 0x02
472 #define RL_CFG5_PME_STS 0x01
479 #define RL_DUMPSTATS_START 0x00000008
482 #define RL_TXSTART_SWI 0x01 /* generate TX interrupt */
483 #define RL_TXSTART_START 0x40 /* start normal queue transmit */
484 #define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */
489 #define RL_CFG2_BUSFREQ 0x07
490 #define RL_CFG2_BUSWIDTH 0x08
491 #define RL_CFG2_AUXPWRSTS 0x10
493 #define RL_BUSFREQ_33MHZ 0x00
494 #define RL_BUSFREQ_66MHZ 0x01
496 #define RL_BUSWIDTH_32BITS 0x00
497 #define RL_BUSWIDTH_64BITS 0x08
500 #define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
501 #define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
502 #define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
503 #define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
504 #define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
505 #define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */
506 #define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */
507 #define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */
508 #define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */
509 #define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */
510 #define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */
511 #define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */
512 #define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */
513 #define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */
514 #define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */
517 #define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
520 #define RL_TIMERINT_8169_VAL 0x00001FFF
521 #define RL_TIMER_MIN 0
530 #define RL_PHYAR_PHYDATA 0x0000FFFF
531 #define RL_PHYAR_PHYREG 0x001F0000
532 #define RL_PHYAR_BUSY 0x80000000
537 #define RL_GMEDIASTAT_FDX 0x01 /* full duplex */
538 #define RL_GMEDIASTAT_LINK 0x02 /* link up */
539 #define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */
540 #define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */
541 #define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */
542 #define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */
543 #define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */
544 #define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */
653 #define RL_TDESC_CMD_FRAGLEN 0x0000FFFF
654 #define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */
655 #define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */
656 #define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
657 #define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
659 #define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */
660 #define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */
661 #define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */
662 #define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */
663 #define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */
665 #define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
666 #define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
668 #define RL_TDESC_CMD_UDPCSUMV2 0x80000000
669 #define RL_TDESC_CMD_TCPCSUMV2 0x40000000
670 #define RL_TDESC_CMD_IPCSUMV2 0x20000000
671 #define RL_TDESC_CMD_MSSVALV2 0x1FFC0000
678 #define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */
679 #define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */
680 #define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */
681 #define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */
682 #define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */
683 #define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occurred */
684 #define RL_TDESC_STAT_OWN 0x80000000
689 #define RL_RDESC_CMD_EOR 0x40000000
690 #define RL_RDESC_CMD_OWN 0x80000000
691 #define RL_RDESC_CMD_BUFLEN 0x00001FFF
693 #define RL_RDESC_STAT_OWN 0x80000000
694 #define RL_RDESC_STAT_EOR 0x40000000
695 #define RL_RDESC_STAT_SOF 0x20000000
696 #define RL_RDESC_STAT_EOF 0x10000000
697 #define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */
698 #define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */
699 #define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */
700 #define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */
701 #define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */
702 #define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */
703 #define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */
704 #define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */
705 #define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */
706 #define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */
707 #define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */
708 #define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */
709 #define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */
710 #define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */
711 #define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */
712 #define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */
713 #define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */
714 #define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */
718 #define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available
720 #define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
722 #define RL_RDESC_IPV6 0x80000000
723 #define RL_RDESC_IPV4 0x40000000
725 #define RL_PROTOID_NONIP 0x00000000
726 #define RL_PROTOID_TCPIP 0x00010000
727 #define RL_PROTOID_UDPIP 0x00020000
728 #define RL_PROTOID_IP 0x00030000
794 #define RE_ETHER_ALIGN 0
800 #define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
904 int suspended; /* 0 = normal 1 = suspended */
915 #define RL_FLAG_MSI 0x00000001
916 #define RL_FLAG_AUTOPAD 0x00000002
917 #define RL_FLAG_PHYWAKE_PM 0x00000004
918 #define RL_FLAG_PHYWAKE 0x00000008
919 #define RL_FLAG_JUMBOV2 0x00000010
920 #define RL_FLAG_PAR 0x00000020
921 #define RL_FLAG_DESCV2 0x00000040
922 #define RL_FLAG_MACSTAT 0x00000080
923 #define RL_FLAG_FASTETHER 0x00000100
924 #define RL_FLAG_CMDSTOP 0x00000200
925 #define RL_FLAG_MACRESET 0x00000400
926 #define RL_FLAG_MSIX 0x00000800
927 #define RL_FLAG_WOLRXENB 0x00001000
928 #define RL_FLAG_MACSLEEP 0x00002000
929 #define RL_FLAG_WAIT_TXPOLL 0x00004000
930 #define RL_FLAG_CMDSTOP_WAIT_TXQ 0x00008000
931 #define RL_FLAG_WOL_MANLINK 0x00010000
932 #define RL_FLAG_EARLYOFF 0x00020000
933 #define RL_FLAG_8168G_PLUS 0x00040000
934 #define RL_FLAG_PCIE 0x40000000
935 #define RL_FLAG_LINK 0x80000000
990 #define RT_VENDORID 0x10EC
995 #define RT_DEVICEID_2600 0x2600
996 #define RT_DEVICEID_8139D 0x8039
997 #define RT_DEVICEID_8129 0x8129
998 #define RT_DEVICEID_8101E 0x8136
999 #define RT_DEVICEID_8138 0x8138
1000 #define RT_DEVICEID_8139 0x8139
1001 #define RT_DEVICEID_8169SC 0x8167
1002 #define RT_DEVICEID_8161 0x8161
1003 #define RT_DEVICEID_8168 0x8168
1004 #define RT_DEVICEID_8169 0x8169
1005 #define RT_DEVICEID_8100 0x8100
1007 #define RT_REVID_8139CPLUS 0x20
1012 #define ACCTON_VENDORID 0x1113
1017 #define ACCTON_DEVICEID_5030 0x1211
1022 #define NORTEL_VENDORID 0x126C
1027 #define DELTA_VENDORID 0x1500
1032 #define DELTA_DEVICEID_8139 0x1360
1037 #define ADDTRON_VENDORID 0x4033
1042 #define ADDTRON_DEVICEID_8139 0x1360
1047 #define DLINK_VENDORID 0x1186
1052 #define DLINK_DEVICEID_530TXPLUS 0x1300
1057 #define DLINK_DEVICEID_520TX_REVC1 0x4200
1062 #define DLINK_DEVICEID_528T 0x4300
1063 #define DLINK_DEVICEID_530T_REVC 0x4302
1068 #define DLINK_DEVICEID_690TXD 0x1340
1073 #define COREGA_VENDORID 0x1259
1078 #define COREGA_DEVICEID_FETHERCBTXD 0xa117
1083 #define COREGA_DEVICEID_FETHERIICBTXD 0xa11e
1088 #define COREGA_DEVICEID_CGLAPCIGT 0xc107
1093 #define LINKSYS_VENDORID 0x1737
1098 #define LINKSYS_DEVICEID_EG1032 0x1032
1103 #define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024
1108 #define PEPPERCON_VENDORID 0x1743
1113 #define PEPPERCON_DEVICEID_ROLF 0x8139
1118 #define PLANEX_VENDORID 0x14ea
1123 #define PLANEX_DEVICEID_FNW3603TX 0xab06
1128 #define PLANEX_DEVICEID_FNW3800TX 0xab07
1133 #define LEVEL1_VENDORID 0x018A
1138 #define LEVEL1_DEVICEID_FPC0106TX 0x0106
1143 #define CP_VENDORID 0x021B
1148 #define EDIMAX_VENDORID 0x13D1
1153 #define EDIMAX_DEVICEID_EP4103DL 0xAB06
1157 #define USR_VENDORID 0x16EC
1161 #define USR_DEVICEID_997902 0x0116
1166 #define NCUBE_VENDORID 0x10FF