Lines Matching +full:0 +full:x7c000000
16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
26 clocks = <&pmd0clk 0>;
31 reg = <0x0 0x001>;
33 cpu-release-addr = <0x1 0x0000fff8>;
36 clocks = <&pmd0clk 0>;
41 reg = <0x0 0x100>;
43 cpu-release-addr = <0x1 0x0000fff8>;
46 clocks = <&pmd1clk 0>;
51 reg = <0x0 0x101>;
53 cpu-release-addr = <0x1 0x0000fff8>;
56 clocks = <&pmd1clk 0>;
61 reg = <0x0 0x200>;
63 cpu-release-addr = <0x1 0x0000fff8>;
66 clocks = <&pmd2clk 0>;
71 reg = <0x0 0x201>;
73 cpu-release-addr = <0x1 0x0000fff8>;
76 clocks = <&pmd2clk 0>;
81 reg = <0x0 0x300>;
83 cpu-release-addr = <0x1 0x0000fff8>;
86 clocks = <&pmd3clk 0>;
91 reg = <0x0 0x301>;
93 cpu-release-addr = <0x1 0x0000fff8>;
96 clocks = <&pmd3clk 0>;
98 xgene_L2_0: l2-cache-0 {
126 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
127 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
128 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
129 <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
130 <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
131 <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
132 v2m0: v2m@0 {
135 reg = <0x0 0x0 0x0 0x1000>;
140 reg = <0x0 0x10000 0x0 0x1000>;
145 reg = <0x0 0x20000 0x0 0x1000>;
150 reg = <0x0 0x30000 0x0 0x1000>;
155 reg = <0x0 0x40000 0x0 0x1000>;
160 reg = <0x0 0x50000 0x0 0x1000>;
165 reg = <0x0 0x60000 0x0 0x1000>;
170 reg = <0x0 0x70000 0x0 0x1000>;
175 reg = <0x0 0x80000 0x0 0x1000>;
180 reg = <0x0 0x90000 0x0 0x1000>;
185 reg = <0x0 0xa0000 0x0 0x1000>;
190 reg = <0x0 0xb0000 0x0 0x1000>;
195 reg = <0x0 0xc0000 0x0 0x1000>;
200 reg = <0x0 0xd0000 0x0 0x1000>;
205 reg = <0x0 0xe0000 0x0 0x1000>;
210 reg = <0x0 0xf0000 0x0 0x1000>;
216 interrupts = <1 12 0xff04>;
221 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
222 <1 13 0xff08>, /* Non-secure Phys IRQ */
223 <1 14 0xff08>, /* Virt IRQ */
224 <1 15 0xff08>; /* Hyp IRQ */
249 clocks = <&refclk 0>;
250 reg = <0x0 0x170000f0 0x0 0x10>;
257 clocks = <&pmdpll 0>;
258 reg = <0x0 0x7e200200 0x0 0x10>;
265 clocks = <&pmdpll 0>;
266 reg = <0x0 0x7e200210 0x0 0x10>;
273 clocks = <&pmdpll 0>;
274 reg = <0x0 0x7e200220 0x0 0x10>;
281 clocks = <&pmdpll 0>;
282 reg = <0x0 0x7e200230 0x0 0x10>;
289 clocks = <&refclk 0>;
290 reg = <0x0 0x17000120 0x0 0x1000>;
297 clocks = <&socpll 0>;
306 clocks = <&socplldiv2 0>;
307 reg = <0x0 0x17000000 0x0 0x2000>;
309 divider-offset = <0x164>;
310 divider-width = <0x5>;
311 divider-shift = <0x0>;
318 clocks = <&ahbclk 0>;
319 reg = <0x0 0x1704c000 0x0 0x2000>;
321 divider-offset = <0x10>;
322 divider-width = <0x2>;
323 divider-shift = <0x0>;
330 clocks = <&socplldiv2 0>;
331 reg = <0x0 0x1f2ac000 0x0 0x1000
332 0x0 0x17000000 0x0 0x2000>;
334 csr-offset = <0x0>;
335 csr-mask = <0x2>;
336 enable-offset = <0x8>;
337 enable-mask = <0x2>;
338 divider-offset = <0x178>;
339 divider-width = <0x8>;
340 divider-shift = <0x0>;
347 clocks = <&socplldiv2 0>;
348 reg = <0x0 0x1f2bc000 0x0 0x1000>;
356 clocks = <&socplldiv2 0>;
357 reg = <0x0 0x1f2cc000 0x0 0x1000>;
365 clocks = <&socplldiv2 0>;
366 reg = <0x0 0x1f61c000 0x0 0x1000>;
368 enable-mask = <0x3>;
369 csr-mask = <0x3>;
376 clocks = <&socplldiv2 0>;
377 reg = <0x0 0x1f62c000 0x0 0x1000>;
379 enable-mask = <0x3>;
380 csr-mask = <0x3>;
387 clocks = <&socplldiv2 0>;
388 reg = <0x0 0x17000000 0x0 0x2000>;
390 csr-offset = <0xc>;
391 csr-mask = <0x10>;
392 enable-offset = <0x10>;
393 enable-mask = <0x10>;
400 clocks = <&sbapbclk 0>;
401 reg = <0x0 0x1704c000 0x0 0x1000>;
403 csr-offset = <0x0>;
404 csr-mask = <0x40>;
405 enable-offset = <0x8>;
406 enable-mask = <0x40>;
413 reg = <0x0 0x17000000 0x0 0x400>;
419 offset = <0x14>;
420 mask = <0x1>;
425 reg = <0x0 0x7e200000 0x0 0x1000>;
430 reg = <0x0 0x7e700000 0x0 0x1000>;
435 reg = <0x0 0x7e720000 0x0 0x1000>;
440 reg = <0x0 0x1054a000 0x0 0x20>;
452 reg = <0x0 0x78800000 0x0 0x100>;
453 interrupts = <0x0 0x20 0x4>,
454 <0x0 0x21 0x4>,
455 <0x0 0x27 0x4>;
459 reg = <0x0 0x7e800000 0x0 0x1000>;
460 memory-controller = <0>;
465 reg = <0x0 0x7e840000 0x0 0x1000>;
471 reg = <0x0 0x7e880000 0x0 0x1000>;
477 reg = <0x0 0x7e8c0000 0x0 0x1000>;
483 reg = <0x0 0x7c000000 0x0 0x200000>;
484 pmd-controller = <0>;
489 reg = <0x0 0x7c200000 0x0 0x200000>;
495 reg = <0x0 0x7c400000 0x0 0x200000>;
501 reg = <0x0 0x7c600000 0x0 0x200000>;
507 reg = <0x0 0x7e600000 0x0 0x1000>;
512 reg = <0x0 0x7e930000 0x0 0x1000>;
524 reg = <0x0 0x78810000 0x0 0x1000>;
525 interrupts = <0x0 0x22 0x4>;
529 reg = <0x0 0x7e610000 0x0 0x1000>;
534 reg = <0x0 0x7e940000 0x0 0x1000>;
539 reg = <0x0 0x7e710000 0x0 0x1000>;
540 enable-bit-index = <0>;
545 reg = <0x0 0x7e730000 0x0 0x1000>;
551 reg = <0x0 0x7e810000 0x0 0x1000>;
552 enable-bit-index = <0>;
557 reg = <0x0 0x7e850000 0x0 0x1000>;
563 reg = <0x0 0x7e890000 0x0 0x1000>;
569 reg = <0x0 0x7e8d0000 0x0 0x1000>;
576 reg = <0x0 0x10540000 0x0 0x8000>;
578 interrupts = <0x0 0x0 0x4
579 0x0 0x1 0x4
580 0x0 0x2 0x4
581 0x0 0x3 0x4
582 0x0 0x4 0x4
583 0x0 0x5 0x4
584 0x0 0x6 0x4
585 0x0 0x7 0x4>;
590 mboxes = <&mailbox 0>;
600 reg = <0 0x10600000 0x0 0x1000>;
604 interrupts = <0x0 0x4c 0x4>;
611 reg = <0x0 0x19000000 0x0 0x100000>;
612 interrupts = <0x0 0x5d 0x4>;
624 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
625 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */
627 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
628 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */
629 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */
630 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
631 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
632 bus-range = <0x00 0xff>;
633 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
634 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4
635 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4
636 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4
637 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>;
639 clocks = <&pcie0clk 0>;
650 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
651 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
653 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
654 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */
655 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
656 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
657 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
658 bus-range = <0x00 0xff>;
659 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
660 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4
661 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4
662 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4
663 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>;
665 clocks = <&pcie1clk 0>;
671 reg = <0x0 0x1a000000 0x0 0x1000>,
672 <0x0 0x1f200000 0x0 0x1000>,
673 <0x0 0x1f20d000 0x0 0x1000>,
674 <0x0 0x1f20e000 0x0 0x1000>;
675 interrupts = <0x0 0x5a 0x4>;
681 reg = <0x0 0x1a200000 0x0 0x1000>,
682 <0x0 0x1f210000 0x0 0x1000>,
683 <0x0 0x1f21d000 0x0 0x1000>,
684 <0x0 0x1f21e000 0x0 0x1000>;
685 interrupts = <0x0 0x5b 0x4>;
691 reg = <0x0 0x1a400000 0x0 0x1000>,
692 <0x0 0x1f220000 0x0 0x1000>,
693 <0x0 0x1f22d000 0x0 0x1000>,
694 <0x0 0x1f22e000 0x0 0x1000>;
695 interrupts = <0x0 0x5c 0x4>;
701 reg = <0x0 0x1c000000 0x0 0x100>;
702 interrupts = <0x0 0x49 0x4>;
706 clocks = <&sdioclk 0>, <&ahbclk 0>;
711 reg = <0x0 0x1f63c000 0x0 0x40>;
718 reg = <0x0 0x1c024000 0x0 0x1000>;
720 #size-cells = <0>;
722 porta: gpio-controller@0 {
727 reg = <0>;
733 reg = <0x0 0x17001000 0x0 0x400>;
736 interrupts = <0x0 0x28 0x1>,
737 <0x0 0x29 0x1>,
738 <0x0 0x2a 0x1>,
739 <0x0 0x2b 0x1>,
740 <0x0 0x2c 0x1>,
741 <0x0 0x2d 0x1>,
742 <0x0 0x2e 0x1>,
743 <0x0 0x2f 0x1>;
755 #size-cells = <0>;
756 reg = <0x0 0x1f610000 0x0 0xd100>;
757 clocks = <&xge0clk 0>;
763 reg = <0x0 0x1f610000 0x0 0xd100>,
764 <0x0 0x1f600000 0x0 0xd100>,
765 <0x0 0x20000000 0x0 0x20000>;
766 interrupts = <0 96 4>,
767 <0 97 4>;
769 clocks = <&xge0clk 0>;
778 reg = <0x0 0x1f620000 0x0 0x10000>,
779 <0x0 0x1f600000 0x0 0xd100>,
780 <0x0 0x20000000 0x0 0x220000>;
781 interrupts = <0 108 4>,
782 <0 109 4>,
783 <0 110 4>,
784 <0 111 4>,
785 <0 112 4>,
786 <0 113 4>,
787 <0 114 4>,
788 <0 115 4>;
792 clocks = <&xge1clk 0>;
799 reg = <0x0 0x10520000 0x0 0x100>;
800 interrupts = <0x0 0x41 0x4>;
801 clocks = <&rngpkaclk 0>;
806 #size-cells = <0>;
808 reg = <0x0 0x10511000 0x0 0x1000>;
809 interrupts = <0 0x45 0x4>;
811 clocks = <&sbapbclk 0>;
817 #size-cells = <0>;
819 reg = <0x0 0x10640000 0x0 0x1000>;
820 interrupts = <0 0x3a 0x4>;
821 clocks = <&i2c4clk 0>;