Lines Matching +full:0 +full:x7c000000

28 #define R92C_FLAGS0_BMCAST	0x01
29 #define R92C_FLAGS0_LSG		0x04
30 #define R92C_FLAGS0_FSG		0x08
31 #define R92C_FLAGS0_OWN		0x80
34 #define R92C_TXDW1_MACID_M	0x0000001f
35 #define R92C_TXDW1_MACID_S	0
36 #define R92C_TXDW1_AGGEN	0x00000020
37 #define R92C_TXDW1_AGGBK	0x00000040
39 #define R92C_TXDW1_QSEL_M	0x00001f00
42 #define R92C_TXDW1_QSEL_BE	0x00	/* or 0x03 */
43 #define R92C_TXDW1_QSEL_BK	0x01	/* or 0x02 */
44 #define R92C_TXDW1_QSEL_VI	0x04	/* or 0x05 */
45 #define R92C_TXDW1_QSEL_VO	0x06	/* or 0x07 */
48 #define R92C_TXDW1_QSEL_BEACON	0x10
49 #define R92C_TXDW1_QSEL_MGNT	0x12
51 #define R92C_TXDW1_RAID_M	0x000f0000
53 #define R92C_TXDW1_CIPHER_M	0x00c00000
55 #define R92C_TXDW1_CIPHER_NONE	0
58 #define R92C_TXDW1_PKTOFF_M	0x7c000000
62 #define R92C_TXDW2_CCX_RPT	0x00080000
63 #define R92C_TXDW2_AMPDU_DEN_M	0x00700000
70 #define R92C_TXDW4_RTSRATE_M	0x0000001f
71 #define R92C_TXDW4_RTSRATE_S	0
72 #define R92C_TXDW4_SEQ_SEL_M	0x00000040
74 #define R92C_TXDW4_HWSEQ_EN	0x00000080
75 #define R92C_TXDW4_DRVRATE	0x00000100
76 #define R92C_TXDW4_CTS2SELF	0x00000800
77 #define R92C_TXDW4_RTSEN	0x00001000
78 #define R92C_TXDW4_HWRTSEN	0x00002000
79 #define R92C_TXDW4_PORT_ID_M	0x00004000
81 #define R92C_TXDW4_DATA_SCO_M	0x00300000
85 #define R92C_TXDW4_DATA_SHPRE	0x01000000
86 #define R92C_TXDW4_DATA_BW40	0x02000000
87 #define R92C_TXDW4_RTS_SHORT	0x04000000
88 #define R92C_TXDW4_RTS_BW40	0x08000000
89 #define R92C_TXDW4_RTS_SCO_M	0x30000000
93 #define R92C_TXDW5_DATARATE_M		0x0000003f
94 #define R92C_TXDW5_DATARATE_S		0
95 #define R92C_TXDW5_SGI			0x00000040
96 #define R92C_TXDW5_DATARATE_FB_LMT_M	0x00001f00
98 #define R92C_TXDW5_RTSRATE_FB_LMT_M	0x0001e000
100 #define R92C_TXDW5_RTY_LMT_ENA		0x00020000
101 #define R92C_TXDW5_RTY_LMT_M		0x00fc0000
103 #define R92C_TXDW5_AGGNUM_M		0xff000000
107 #define R92C_TXDW6_MAX_AGG_M		0x0000f800
112 #define R92C_RAID_11BGN		0