Lines Matching +full:0 +full:x7c000000

37 #define MT_HW_REV			MT_HW_INFO(0x000)
38 #define MT_HW_CHIPID MT_HW_INFO(0x008)
39 #define MT_TOP_STRAP_STA MT_HW_INFO(0x010)
42 #define MT_TOP_OFF_RSV 0x1128
45 #define MT_TOP_MISC2 ((dev)->reg_map[MT_TOP_CFG_BASE] + 0x134)
46 #define MT_TOP_MISC2_FW_STATE GENMASK(2, 0)
51 #define MT_MCU_BASE 0x2000
54 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)
55 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
57 #define MT_PCIE_REMAP_BASE_1 0x40000
60 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
64 #define MT_MCU_CIRQ_BASE 0xc0000
70 #define MT_HIF_RST MT_HIF(0x100)
73 #define MT_PDMA_SLP_PROT MT_HIF(0x154)
74 #define MT_PDMA_AXI_SLPPROT_ENABLE BIT(0)
77 #define MT_PDMA_BUSY_STATUS MT_HIF(0x168)
81 #define MT_WPDMA_TX_RING0_CTRL0 MT_HIF(0x300)
82 #define MT_WPDMA_TX_RING0_CTRL1 MT_HIF(0x304)
84 #define MT7663_MCU_PCIE_REMAP_2_OFFSET GENMASK(15, 0)
87 #define MT_HIF2_BASE 0xf0000
89 #define MT_PCIE_IRQ_ENABLE MT_HIF2(0x188)
90 #define MT_PCIE_DOORBELL_PUSH MT_HIF2(0x1484)
92 #define MT_CFG_LPCR_HOST MT_HIF(0x1f0)
93 #define MT_CFG_LPCR_HOST_FW_OWN BIT(0)
96 #define MT_MCU2HOST_INT_STATUS MT_HIF(0x1f0)
97 #define MT_MCU2HOST_INT_ENABLE MT_HIF(0x1f4)
99 #define MT7663_MCU_INT_EVENT MT_HIF(0x108)
100 #define MT_MCU_INT_EVENT MT_HIF(0x1f8)
101 #define MT_MCU_INT_EVENT_PDMA_STOPPED BIT(0)
106 #define MT_INT_SOURCE_CSR MT_HIF(0x200)
107 #define MT_INT_MASK_CSR MT_HIF(0x204)
108 #define MT_DELAY_INT_CFG MT_HIF(0x210)
111 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
117 #define MT_WPDMA_GLO_CFG MT_HIF(0x208)
118 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
134 #define MT_WPDMA_RST_IDX MT_HIF(0x20c)
136 #define MT_WPDMA_MEM_RNG_ERR MT_HIF(0x224)
138 #define MT_MCU_CMD MT_HIF(0x234)
139 #define MT_MCU_CMD_CLEAR_FW_OWN BIT(0)
153 #define MT_TX_RING_BASE MT_HIF(0x300)
154 #define MT_RX_RING_BASE MT_HIF(0x400)
156 #define MT_WPDMA_GLO_CFG1 MT_HIF(0x500)
157 #define MT_WPDMA_TX_PRE_CFG MT_HIF(0x510)
158 #define MT_WPDMA_RX_PRE_CFG MT_HIF(0x520)
159 #define MT_WPDMA_ABT_CFG MT_HIF(0x530)
160 #define MT_WPDMA_ABT_CFG1 MT_HIF(0x534)
163 #define MT_CONN_HIF_ON_LPCTL MT_CSR(0x000)
167 #define MT_PLE_PG_HIF0_GROUP MT_PLE(0x110)
168 #define MT_HIF0_MIN_QUOTA GENMASK(11, 0)
169 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x1b0)
170 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x1b4)
171 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x1b8)
172 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x1bc)
174 #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x300 + 0x10 * (ac) + \
178 #define MT_PSE_PG_HIF0_GROUP MT_PSE(0x110)
179 #define MT_HIF0_MIN_QUOTA GENMASK(11, 0)
180 #define MT_PSE_PG_HIF1_GROUP MT_PSE(0x118)
181 #define MT_HIF1_MIN_QUOTA GENMASK(11, 0)
182 #define MT_PSE_QUEUE_EMPTY MT_PSE(0x0b4)
186 #define MT_PSE_PG_INFO MT_PSE(0x194)
190 #define MT_PP_TXDWCNT MT_PP(0x0)
191 #define MT_PP_TXDWCNT_TX0_ADD_DW_CNT GENMASK(7, 0)
194 #define MT_WF_PHY_BASE 0x82070000
197 #define MT_WF_PHY_WF2_RFCTRL0(n) MT_WF_PHY(0x1900 + (n) * 0x400)
200 #define MT_WF_PHY_R0_PHYMUX_5(_phy) MT_WF_PHY(0x0614 + ((_phy) << 9))
201 #define MT7663_WF_PHY_R0_PHYMUX_5 MT_WF_PHY(0x0414)
203 #define MT_WF_PHY_R0_PHYCTRL_STS0(_phy) MT_WF_PHY(0x020c + ((_phy) << 9))
205 #define MT_WF_PHYCTRL_STAT_PD_CCK GENMASK(15, 0)
207 #define MT7663_WF_PHY_R0_PHYCTRL_STS0(_phy) MT_WF_PHY(0x0210 + ((_phy) << 12))
209 #define MT_WF_PHY_R0_PHYCTRL_STS5(_phy) MT_WF_PHY(0x0220 + ((_phy) << 9))
211 #define MT_WF_PHYCTRL_STAT_MDRDY_CCK GENMASK(15, 0)
213 #define MT7663_WF_PHY_R0_PHYCTRL_STS5(_phy) MT_WF_PHY(0x0224 + ((_phy) << 12))
215 #define MT_WF_PHY_GID_TAB_VLD(_phy, i) MT_WF_PHY(0x0254 + (i) * 4 + \
217 #define MT7663_WF_PHY_GID_TAB_VLD(_phy, i) MT_WF_PHY(0x0254 + (i) * 4 + \
219 #define MT_WF_PHY_GID_TAB_POS(_phy, i) MT_WF_PHY(0x025c + (i) * 4 + \
221 #define MT7663_WF_PHY_GID_TAB_POS(_phy, i) MT_WF_PHY(0x025c + (i) * 4 + \
224 #define MT_WF_PHY_MIN_PRI_PWR(_phy) MT_WF_PHY((_phy) ? 0x084 : 0x229c)
230 #define MT7663_WF_PHY_MIN_PRI_PWR(_phy) MT_WF_PHY((_phy) ? 0x2aec : 0x22f0)
232 #define MT_WF_PHY_RXTD_BASE MT_WF_PHY(0x2200)
235 #define MT7663_WF_PHY_RXTD(_n) (MT_WF_PHY(0x25b0) + ((_n) << 2))
237 #define MT_WF_PHY_RXTD_CCK_PD(_phy) MT_WF_PHY((_phy) ? 0x2314 : 0x2310)
242 #define MT7663_WF_PHY_RXTD_CCK_PD(_phy) MT_WF_PHY((_phy) ? 0x2350 : 0x234c)
244 #define MT_WF_PHY_RXTD2_BASE MT_WF_PHY(0x2a00)
247 #define MT_WF_PHY_RFINTF3_0(_n) MT_WF_PHY(0x1100 + (_n) * 0x400)
253 #define MT_CFG_CCR MT_WF_CFG(0x000)
262 #define MT_AGG_ARCR MT_WF_AGG(0x010)
263 #define MT_AGG_ARCR_INIT_RATE1 BIT(0)
269 #define MT_AGG_ARUCR(_band) MT_WF_AGG(0x018 + (_band) * 0x100)
270 #define MT_AGG_ARDCR(_band) MT_WF_AGG(0x01c + (_band) * 0x100)
276 #define MT_AGG_ASRCR0 MT_WF_AGG(0x060)
277 #define MT_AGG_ASRCR1 MT_WF_AGG(0x064)
278 #define MT_AGG_ASRCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(5, 0))
280 #define MT_AGG_ACR(_band) MT_WF_AGG(0x070 + (_band) * 0x100)
281 #define MT_AGG_ACR_NO_BA_RULE BIT(0)
287 #define MT_AGG_SCR MT_WF_AGG(0x0fc)
293 #define MT_ARB_RQCR MT_WF_ARB(0x070)
294 #define MT_ARB_RQCR_RX_START BIT(0)
300 #define MT_ARB_SCR MT_WF_ARB(0x080)
309 #define MT_TMAC_CDTR MT_WF_TMAC(0x090)
310 #define MT_TMAC_ODTR MT_WF_TMAC(0x094)
311 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
314 #define MT_TMAC_TRCR(_band) MT_WF_TMAC((_band) ? 0x070 : 0x09c)
318 #define MT_TMAC_ICR(_band) MT_WF_TMAC((_band) ? 0x074 : 0x0a4)
319 #define MT_IFS_EIFS GENMASK(8, 0)
324 #define MT_TMAC_CTCR0 MT_WF_TMAC(0x0f4)
325 #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
333 #define MT_WF_RFCR(_band) MT_WF_RMAC((_band) ? 0x100 : 0x000)
334 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
356 #define MT_WF_RMAC_MORE(_band) MT_WF_RMAC((_band) ? 0x124 : 0x024)
359 #define MT_WF_RFCR1(_band) MT_WF_RMAC((_band) ? 0x104 : 0x004)
366 #define MT_CHFREQ(_band) MT_WF_RMAC((_band) ? 0x130 : 0x030)
368 #define MT_WF_RMAC_MAR0 MT_WF_RMAC(0x025c)
369 #define MT_WF_RMAC_MAR1 MT_WF_RMAC(0x0260)
370 #define MT_WF_RMAC_MAR1_ADDR GENMASK(15, 0)
376 #define MT_WF_RMAC_MIB_TIME0 MT_WF_RMAC(0x03c4)
380 #define MT_WF_RMAC_MIB_AIRTIME0 MT_WF_RMAC(0x0380)
382 #define MT_WF_RMAC_MIB_TIME5 MT_WF_RMAC(0x03d8)
383 #define MT_WF_RMAC_MIB_TIME6 MT_WF_RMAC(0x03dc)
384 #define MT_MIB_OBSSTIME_MASK GENMASK(23, 0)
389 #define MT_DMA_DCR0 MT_WF_DMA(0x000)
395 #define MT_DMA_RCFR0(_band) MT_WF_DMA(0x070 + (_band) * 0x40)
407 #define MT_WF_PFCR MT_WF_PF(0x000)
422 #define MT_WTBL_UPDATE MT_WTBL_OFF(0x030)
423 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(7, 0)
431 #define MT_CONN_ON_MISC MT_TOP_MISC(0x1140)
437 #define MT_WTBL_RICR0 MT_WTBL_ON(0x010)
438 #define MT_WTBL_RICR1 MT_WTBL_ON(0x014)
440 #define MT_WTBL_RIUCR0 MT_WTBL_ON(0x020)
442 #define MT_WTBL_RIUCR1 MT_WTBL_ON(0x024)
443 #define MT_WTBL_RIUCR1_RATE0 GENMASK(11, 0)
447 #define MT_WTBL_RIUCR2 MT_WTBL_ON(0x028)
448 #define MT_WTBL_RIUCR2_RATE2_HI GENMASK(3, 0)
453 #define MT_WTBL_RIUCR3 MT_WTBL_ON(0x02c)
454 #define MT_WTBL_RIUCR3_RATE5_HI GENMASK(7, 0)
474 #define MT_LPON_TCR0(_n) MT_LPON(0x010 + ((_n) * 4))
475 #define MT_LPON_TCR2(_n) MT_LPON(0x0f8 + ((_n) - 2) * 4)
476 #define MT_LPON_TCR_MODE GENMASK(1, 0)
477 #define MT_LPON_TCR_READ GENMASK(1, 0)
478 #define MT_LPON_TCR_WRITE BIT(0)
481 #define MT_LPON_UTTR0 MT_LPON(0x018)
482 #define MT_LPON_UTTR1 MT_LPON(0x01c)
485 #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE + (ofs) + (_band) * 0x200)
487 #define MT_WF_MIB_SCR0 MT_WF_MIB(0, 0)
490 #define MT_MIB_M0_MISC_CR(_band) MT_WF_MIB(_band, 0x00c)
492 #define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x014)
493 #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0)
495 #define MT_MIB_SDR9(_band) MT_WF_MIB(_band, 0x02c)
496 #define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0)
498 #define MT_MIB_SDR14(_band) MT_WF_MIB(_band, 0x040)
499 #define MT_MIB_AMPDU_MPDU_COUNT GENMASK(23, 0)
501 #define MT_MIB_SDR15(_band) MT_WF_MIB(_band, 0x044)
502 #define MT_MIB_AMPDU_ACK_COUNT GENMASK(23, 0)
504 #define MT_MIB_SDR16(_band) MT_WF_MIB(_band, 0x048)
505 #define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0)
507 #define MT_MIB_SDR36(_band) MT_WF_MIB(_band, 0x098)
508 #define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0)
509 #define MT_MIB_SDR37(_band) MT_WF_MIB(_band, 0x09c)
510 #define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0)
512 #define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, 0x100 + ((n) << 4))
514 #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
516 #define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, 0x104 + ((n) << 4))
517 #define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0)
520 #define MT_MIB_ARNG(n) MT_WF_MIB(0, 0x4b8 + ((n) << 2))
522 #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0xa8 + ((n) << 2))
526 #define MT_DMASHDL_BASE 0x5000a000
527 #define MT_DMASHDL_OPTIONAL 0x008
528 #define MT_DMASHDL_PAGE 0x00c
530 #define MT_DMASHDL_REFILL 0x010
532 #define MT_DMASHDL_PKT_MAX_SIZE 0x01c
533 #define MT_DMASHDL_PKT_MAX_SIZE_PLE GENMASK(11, 0)
536 #define MT_DMASHDL_GROUP_QUOTA(_n) (0x020 + ((_n) << 2))
537 #define MT_DMASHDL_GROUP_QUOTA_MIN GENMASK(11, 0)
540 #define MT_DMASHDL_SCHED_SET0 0x0b0
541 #define MT_DMASHDL_SCHED_SET1 0x0b4
543 #define MT_DMASHDL_Q_MAP(_n) (0x0d0 + ((_n) << 2))
544 #define MT_DMASHDL_Q_MAP_MASK GENMASK(3, 0)
547 #define MT_LED_BASE_PHYS 0x80024000
550 #define MT_LED_CTRL MT_LED_PHYS(0x00)
552 #define MT_LED_CTRL_REPLAY(_n) BIT(0 + (8 * (_n)))
560 #define MT_LED_STATUS_0(_n) MT_LED_PHYS(0x10 + ((_n) * 8))
561 #define MT_LED_STATUS_1(_n) MT_LED_PHYS(0x14 + ((_n) * 8))
564 #define MT_LED_STATUS_DURATION GENMASK(15, 0)
566 #define MT_PDMA_BUSY 0x82000504
567 #define MT_PDMA_TX_BUSY BIT(0)
571 #define MT_EFUSE_BASE_CTRL 0x000
574 #define MT_EFUSE_CTRL 0x008
575 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
584 #define MT_EFUSE_WDATA(_i) (0x010 + ((_i) * 4))
585 #define MT_EFUSE_RDATA(_i) (0x030 + ((_i) * 4))
588 #define MT_INFRACFG_MISC 0x700
591 #define MT_UMAC_BASE 0x7c000000
593 #define MT_UDMA_TX_QSEL MT_UMAC(0x008)
596 #define MT_UDMA_WLCFG_1 MT_UMAC(0x00c)
597 #define MT_WL_RX_AGG_PKT_LMT GENMASK(7, 0)
600 #define MT_UDMA_WLCFG_0 MT_UMAC(0x18)
601 #define MT_WL_RX_AGG_TO GENMASK(7, 0)
614 #define MT_MCU_PTA_BASE 0x81060000
617 #define MT_ANT_SWITCH_CON(_n) MT_MCU_PTA(0x0c8 + ((_n) - 1) * 4)
618 #define MT_ANT_SWITCH_CON_MODE(_n) (GENMASK(4, 0) << (_n * 8))
619 #define MT_ANT_SWITCH_CON_MODE1(_n) (GENMASK(3, 0) << (_n * 8))