21 	[INT_SOURCE_CSR]		= 0xd7010,
22 	[INT_MASK_CSR]			= 0xd7014,
23 	[INT1_SOURCE_CSR]		= 0xd7088,
24 	[INT1_MASK_CSR]			= 0xd708c,
25 	[INT_MCU_CMD_SOURCE]		= 0xd51f0,
26 	[INT_MCU_CMD_EVENT]		= 0x3108,
27 	[WFDMA0_ADDR]			= 0xd4000,
28 	[WFDMA0_PCIE1_ADDR]		= 0xd8000,
29 	[WFDMA_EXT_CSR_ADDR]		= 0xd7000,
30 	[CBTOP1_PHY_END]		= 0x77ffffff,
31 	[INFRA_MCU_ADDR_END]		= 0x7c3fffff,
32 	[FW_ASSERT_STAT_ADDR]		= 0x219848,
33 	[FW_EXCEPT_TYPE_ADDR]		= 0x21987c,
34 	[FW_EXCEPT_COUNT_ADDR]		= 0x219848,
35 	[FW_CIRQ_COUNT_ADDR]		= 0x216f94,
36 	[FW_CIRQ_IDX_ADDR]		= 0x216ef8,
37 	[FW_CIRQ_LISR_ADDR]		= 0x2170ac,
38 	[FW_TASK_ID_ADDR]		= 0x216f90,
39 	[FW_TASK_IDX_ADDR]		= 0x216f9c,
40 	[FW_TASK_QID1_ADDR]		= 0x219680,
41 	[FW_TASK_QID2_ADDR]		= 0x219760,
42 	[FW_TASK_START_ADDR]		= 0x219558,
43 	[FW_TASK_END_ADDR]		= 0x219554,
44 	[FW_TASK_SIZE_ADDR]		= 0x219560,
45 	[FW_LAST_MSG_ID_ADDR]		= 0x216f70,
46 	[FW_EINT_INFO_ADDR]		= 0x219818,
47 	[FW_SCHED_INFO_ADDR]		= 0x219828,
48 	[SWDEF_BASE_ADDR]		= 0x41f200,
49 	[TXQ_WED_RING_BASE]		= 0xd7300,
50 	[RXQ_WED_RING_BASE]		= 0xd7410,
51 	[RXQ_WED_DATA_RING_BASE]	= 0xd4500,
55 	[INT_SOURCE_CSR]		= 0xd4200,
56 	[INT_MASK_CSR]			= 0xd4204,
57 	[INT1_SOURCE_CSR]		= 0xd8200,
58 	[INT1_MASK_CSR]			= 0xd8204,
59 	[INT_MCU_CMD_SOURCE]		= 0xd41f0,
60 	[INT_MCU_CMD_EVENT]		= 0x2108,
61 	[WFDMA0_ADDR]			= 0xd4000,
62 	[WFDMA0_PCIE1_ADDR]		= 0xd8000,
63 	[WFDMA_EXT_CSR_ADDR]		= 0xd7000,
64 	[CBTOP1_PHY_END]		= 0x7fffffff,
65 	[INFRA_MCU_ADDR_END]		= 0x7c085fff,
66 	[FW_ASSERT_STAT_ADDR]		= 0x02204c14,
67 	[FW_EXCEPT_TYPE_ADDR]		= 0x022051a4,
68 	[FW_EXCEPT_COUNT_ADDR]		= 0x022050bc,
69 	[FW_CIRQ_COUNT_ADDR]		= 0x022001ac,
70 	[FW_CIRQ_IDX_ADDR]		= 0x02204f84,
71 	[FW_CIRQ_LISR_ADDR]		= 0x022050d0,
72 	[FW_TASK_ID_ADDR]		= 0x0220406c,
73 	[FW_TASK_IDX_ADDR]		= 0x0220500c,
74 	[FW_TASK_QID1_ADDR]		= 0x022028c8,
75 	[FW_TASK_QID2_ADDR]		= 0x02202a38,
76 	[FW_TASK_START_ADDR]		= 0x0220286c,
77 	[FW_TASK_END_ADDR]		= 0x02202870,
78 	[FW_TASK_SIZE_ADDR]		= 0x02202878,
79 	[FW_LAST_MSG_ID_ADDR]		= 0x02204fe8,
80 	[FW_EINT_INFO_ADDR]		= 0x0220525c,
81 	[FW_SCHED_INFO_ADDR]		= 0x0220516c,
82 	[SWDEF_BASE_ADDR]		= 0x411400,
83 	[TXQ_WED_RING_BASE]		= 0xd7300,
84 	[RXQ_WED_RING_BASE]		= 0xd7410,
85 	[RXQ_WED_DATA_RING_BASE]	= 0xd4540,
89 	[INT_SOURCE_CSR]		= 0x24200,
90 	[INT_MASK_CSR]			= 0x24204,
91 	[INT1_SOURCE_CSR]		= 0x28200,
92 	[INT1_MASK_CSR]			= 0x28204,
93 	[INT_MCU_CMD_SOURCE]		= 0x241f0,
94 	[INT_MCU_CMD_EVENT]		= 0x54000108,
95 	[WFDMA0_ADDR]			= 0x24000,
96 	[WFDMA0_PCIE1_ADDR]		= 0x28000,
97 	[WFDMA_EXT_CSR_ADDR]		= 0x27000,
98 	[CBTOP1_PHY_END]		= 0x7fffffff,
99 	[INFRA_MCU_ADDR_END]		= 0x7c085fff,
100 	[FW_ASSERT_STAT_ADDR]		= 0x02204b54,
101 	[FW_EXCEPT_TYPE_ADDR]		= 0x022050dc,
102 	[FW_EXCEPT_COUNT_ADDR]		= 0x02204ffc,
103 	[FW_CIRQ_COUNT_ADDR]		= 0x022001ac,
104 	[FW_CIRQ_IDX_ADDR]		= 0x02204ec4,
105 	[FW_CIRQ_LISR_ADDR]		= 0x02205010,
106 	[FW_TASK_ID_ADDR]		= 0x02204fac,
107 	[FW_TASK_IDX_ADDR]		= 0x02204f4c,
108 	[FW_TASK_QID1_ADDR]		= 0x02202814,
109 	[FW_TASK_QID2_ADDR]		= 0x02202984,
110 	[FW_TASK_START_ADDR]		= 0x022027b8,
111 	[FW_TASK_END_ADDR]		= 0x022027bc,
112 	[FW_TASK_SIZE_ADDR]		= 0x022027c4,
113 	[FW_LAST_MSG_ID_ADDR]		= 0x02204f28,
114 	[FW_EINT_INFO_ADDR]		= 0x02205194,
115 	[FW_SCHED_INFO_ADDR]		= 0x022051a4,
116 	[SWDEF_BASE_ADDR]		= 0x411400,
117 	[TXQ_WED_RING_BASE]		= 0x24420,
118 	[RXQ_WED_RING_BASE]		= 0x24520,
119 	[RXQ_WED_DATA_RING_BASE]	= 0x24540,
123 	[TMAC_CDTR]		= 0x090,
124 	[TMAC_ODTR]		= 0x094,
125 	[TMAC_ATCR]		= 0x098,
126 	[TMAC_TRCR0]		= 0x09c,
127 	[TMAC_ICR0]		= 0x0a4,
128 	[TMAC_ICR1]		= 0x0b4,
129 	[TMAC_CTCR0]		= 0x0f4,
130 	[TMAC_TFCR0]		= 0x1e0,
131 	[MDP_BNRCFR0]		= 0x070,
132 	[MDP_BNRCFR1]		= 0x074,
133 	[ARB_DRNGR0]		= 0x194,
134 	[ARB_SCR]		= 0x080,
135 	[RMAC_MIB_AIRTIME14]	= 0x3b8,
136 	[AGG_AWSCR0]		= 0x05c,
137 	[AGG_PCR0]		= 0x06c,
138 	[AGG_ACR0]		= 0x084,
139 	[AGG_ACR4]		= 0x08c,
140 	[AGG_MRCR]		= 0x098,
141 	[AGG_ATCR1]		= 0x0f0,
142 	[AGG_ATCR3]		= 0x0f4,
143 	[LPON_UTTR0]		= 0x080,
144 	[LPON_UTTR1]		= 0x084,
145 	[LPON_FRCR]		= 0x314,
146 	[MIB_SDR3]		= 0x014,
147 	[MIB_SDR4]		= 0x018,
148 	[MIB_SDR5]		= 0x01c,
149 	[MIB_SDR7]		= 0x024,
150 	[MIB_SDR8]		= 0x028,
151 	[MIB_SDR9]		= 0x02c,
152 	[MIB_SDR10]		= 0x030,
153 	[MIB_SDR11]		= 0x034,
154 	[MIB_SDR12]		= 0x038,
155 	[MIB_SDR13]		= 0x03c,
156 	[MIB_SDR14]		= 0x040,
157 	[MIB_SDR15]		= 0x044,
158 	[MIB_SDR16]		= 0x048,
159 	[MIB_SDR17]		= 0x04c,
160 	[MIB_SDR18]		= 0x050,
161 	[MIB_SDR19]		= 0x054,
162 	[MIB_SDR20]		= 0x058,
163 	[MIB_SDR21]		= 0x05c,
164 	[MIB_SDR22]		= 0x060,
165 	[MIB_SDR23]		= 0x064,
166 	[MIB_SDR24]		= 0x068,
167 	[MIB_SDR25]		= 0x06c,
168 	[MIB_SDR27]		= 0x074,
169 	[MIB_SDR28]		= 0x078,
170 	[MIB_SDR29]		= 0x07c,
171 	[MIB_SDRVEC]		= 0x080,
172 	[MIB_SDR31]		= 0x084,
173 	[MIB_SDR32]		= 0x088,
174 	[MIB_SDRMUBF]		= 0x090,
175 	[MIB_DR8]		= 0x0c0,
176 	[MIB_DR9]		= 0x0c4,
177 	[MIB_DR11]		= 0x0cc,
178 	[MIB_MB_SDR0]		= 0x100,
179 	[MIB_MB_SDR1]		= 0x104,
180 	[TX_AGG_CNT]		= 0x0a8,
181 	[TX_AGG_CNT2]		= 0x164,
182 	[MIB_ARNG]		= 0x4b8,
183 	[WTBLON_TOP_WDUCR]	= 0x0,
184 	[WTBL_UPDATE]		= 0x030,
185 	[PLE_FL_Q_EMPTY]	= 0x0b0,
186 	[PLE_FL_Q_CTRL]		= 0x1b0,
187 	[PLE_AC_QEMPTY]		= 0x500,
188 	[PLE_FREEPG_CNT]	= 0x100,
189 	[PLE_FREEPG_HEAD_TAIL]	= 0x104,
190 	[PLE_PG_HIF_GROUP]	= 0x110,
191 	[PLE_HIF_PG_INFO]	= 0x114,
192 	[AC_OFFSET]		= 0x040,
193 	[ETBF_PAR_RPT0]		= 0x068,
197 	[TMAC_CDTR]		= 0x0c8,
198 	[TMAC_ODTR]		= 0x0cc,
199 	[TMAC_ATCR]		= 0x00c,
200 	[TMAC_TRCR0]		= 0x010,
201 	[TMAC_ICR0]		= 0x014,
202 	[TMAC_ICR1]		= 0x018,
203 	[TMAC_CTCR0]		= 0x114,
204 	[TMAC_TFCR0]		= 0x0e4,
205 	[MDP_BNRCFR0]		= 0x090,
206 	[MDP_BNRCFR1]		= 0x094,
207 	[ARB_DRNGR0]		= 0x1e0,
208 	[ARB_SCR]		= 0x000,
209 	[RMAC_MIB_AIRTIME14]	= 0x0398,
210 	[AGG_AWSCR0]		= 0x030,
211 	[AGG_PCR0]		= 0x040,
212 	[AGG_ACR0]		= 0x054,
213 	[AGG_ACR4]		= 0x05c,
214 	[AGG_MRCR]		= 0x068,
215 	[AGG_ATCR1]		= 0x1a8,
216 	[AGG_ATCR3]		= 0x080,
217 	[LPON_UTTR0]		= 0x360,
218 	[LPON_UTTR1]		= 0x364,
219 	[LPON_FRCR]		= 0x37c,
220 	[MIB_SDR3]		= 0x698,
221 	[MIB_SDR4]		= 0x788,
222 	[MIB_SDR5]		= 0x780,
223 	[MIB_SDR7]		= 0x5a8,
224 	[MIB_SDR8]		= 0x78c,
225 	[MIB_SDR9]		= 0x024,
226 	[MIB_SDR10]		= 0x76c,
227 	[MIB_SDR11]		= 0x790,
228 	[MIB_SDR12]		= 0x558,
229 	[MIB_SDR13]		= 0x560,
230 	[MIB_SDR14]		= 0x564,
231 	[MIB_SDR15]		= 0x568,
232 	[MIB_SDR16]		= 0x7fc,
233 	[MIB_SDR17]		= 0x800,
234 	[MIB_SDR18]		= 0x030,
235 	[MIB_SDR19]		= 0x5ac,
236 	[MIB_SDR20]		= 0x5b0,
237 	[MIB_SDR21]		= 0x5b4,
238 	[MIB_SDR22]		= 0x770,
239 	[MIB_SDR23]		= 0x774,
240 	[MIB_SDR24]		= 0x778,
241 	[MIB_SDR25]		= 0x77c,
242 	[MIB_SDR27]		= 0x080,
243 	[MIB_SDR28]		= 0x084,
244 	[MIB_SDR29]		= 0x650,
245 	[MIB_SDRVEC]		= 0x5a8,
246 	[MIB_SDR31]		= 0x55c,
247 	[MIB_SDR32]		= 0x7a8,
248 	[MIB_SDRMUBF]		= 0x7ac,
249 	[MIB_DR8]		= 0x56c,
250 	[MIB_DR9]		= 0x570,
251 	[MIB_DR11]		= 0x574,
252 	[MIB_MB_SDR0]		= 0x688,
253 	[MIB_MB_SDR1]		= 0x690,
254 	[TX_AGG_CNT]		= 0x7dc,
255 	[TX_AGG_CNT2]		= 0x7ec,
256 	[MIB_ARNG]		= 0x0b0,
257 	[WTBLON_TOP_WDUCR]	= 0x200,
258 	[WTBL_UPDATE]		= 0x230,
259 	[PLE_FL_Q_EMPTY]	= 0x360,
260 	[PLE_FL_Q_CTRL]		= 0x3e0,
261 	[PLE_AC_QEMPTY]		= 0x600,
262 	[PLE_FREEPG_CNT]	= 0x380,
263 	[PLE_FREEPG_HEAD_TAIL]	= 0x384,
264 	[PLE_PG_HIF_GROUP]	= 0x00c,
265 	[PLE_HIF_PG_INFO]	= 0x388,
266 	[AC_OFFSET]		= 0x080,
267 	[ETBF_PAR_RPT0]		= 0x100,
271 	{ 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
272 	{ 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */
273 	{ 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
274 	{ 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */
275 	{ 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */
276 	{ 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
277 	{ 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */
278 	{ 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
279 	{ 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
280 	{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
281 	{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
282 	{ 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
283 	{ 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
284 	{ 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
285 	{ 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
286 	{ 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
287 	{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
288 	{ 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
289 	{ 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
290 	{ 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
291 	{ 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
292 	{ 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
293 	{ 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
294 	{ 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
295 	{ 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
296 	{ 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
297 	{ 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
298 	{ 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
299 	{ 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
300 	{ 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
301 	{ 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
302 	{ 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
303 	{ 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
304 	{ 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
305 	{ 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
306 	{ 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
307 	{ 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
308 	{ 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
309 	{ 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
310 	{ 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
311 	{ 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
312 	{ 0x0, 0x0, 0x0 }, /* imply end of search */
316 	{ 0x54000000, 0x02000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
317 	{ 0x55000000, 0x03000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
318 	{ 0x56000000, 0x04000, 0x01000 }, /* WFDMA_2 (Reserved) */
319 	{ 0x57000000, 0x05000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */
320 	{ 0x58000000, 0x06000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
321 	{ 0x59000000, 0x07000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
322 	{ 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
323 	{ 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
324 	{ 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
325 	{ 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
326 	{ 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
327 	{ 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
328 	{ 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
329 	{ 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
330 	{ 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
331 	{ 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
332 	{ 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
333 	{ 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
334 	{ 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
335 	{ 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
336 	{ 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
337 	{ 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
338 	{ 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
339 	{ 0x820ca000, 0x26000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
340 	{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
341 	{ 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
342 	{ 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure cr) */
343 	{ 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
344 	{ 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
345 	{ 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
346 	{ 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
347 	{ 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
348 	{ 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
349 	{ 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
350 	{ 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
351 	{ 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
352 	{ 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
353 	{ 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
354 	{ 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
355 	{ 0x820c4000, 0xa8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
356 	{ 0x820b0000, 0xae000, 0x01000 }, /* [APB2] WFSYS_ON */
357 	{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
358 	{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
359 	{ 0x0, 0x0, 0x0 }, /* imply end of search */
363 	{ 0x54000000, 0x402000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
364 	{ 0x55000000, 0x403000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
365 	{ 0x56000000, 0x404000, 0x01000 }, /* WFDMA_2 (Reserved) */
366 	{ 0x57000000, 0x405000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */
367 	{ 0x58000000, 0x406000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
368 	{ 0x59000000, 0x407000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
369 	{ 0x820c0000, 0x408000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
370 	{ 0x820c8000, 0x40c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
371 	{ 0x820cc000, 0x40e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
372 	{ 0x820e0000, 0x420000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
373 	{ 0x820e1000, 0x420400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
374 	{ 0x820e2000, 0x420800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
375 	{ 0x820e3000, 0x420c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
376 	{ 0x820e4000, 0x421000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
377 	{ 0x820e5000, 0x421400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
378 	{ 0x820ce000, 0x421c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
379 	{ 0x820e7000, 0x421e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
380 	{ 0x820cf000, 0x422000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
381 	{ 0x820e9000, 0x423400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
382 	{ 0x820ea000, 0x424000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
383 	{ 0x820eb000, 0x424200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
384 	{ 0x820ec000, 0x424600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
385 	{ 0x820ed000, 0x424800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
386 	{ 0x820ca000, 0x426000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
387 	{ 0x820d0000, 0x430000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
388 	{ 0x00400000, 0x480000, 0x10000 }, /* WF_MCU_SYSRAM */
389 	{ 0x00410000, 0x490000, 0x10000 }, /* WF_MCU_SYSRAM */
390 	{ 0x820f0000, 0x4a0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
391 	{ 0x820f1000, 0x4a0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
392 	{ 0x820f2000, 0x4a0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
393 	{ 0x820f3000, 0x4a0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
394 	{ 0x820f4000, 0x4a1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
395 	{ 0x820f5000, 0x4a1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
396 	{ 0x820f7000, 0x4a1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
397 	{ 0x820f9000, 0x4a3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
398 	{ 0x820fa000, 0x4a4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
399 	{ 0x820fb000, 0x4a4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
400 	{ 0x820fc000, 0x4a4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
401 	{ 0x820fd000, 0x4a4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
402 	{ 0x820c4000, 0x4a8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
403 	{ 0x820b0000, 0x4ae000, 0x01000 }, /* [APB2] WFSYS_ON */
404 	{ 0x80020000, 0x4b0000, 0x10000 }, /* WF_TOP_MISC_OFF */
405 	{ 0x81020000, 0x4c0000, 0x10000 }, /* WF_TOP_MISC_ON */
406 	{ 0x89000000, 0x4d0000, 0x01000 }, /* WF_MCU_CFG_ON */
407 	{ 0x89010000, 0x4d1000, 0x01000 }, /* WF_MCU_CIRQ */
408 	{ 0x89020000, 0x4d2000, 0x01000 }, /* WF_MCU_GPT */
409 	{ 0x89030000, 0x4d3000, 0x01000 }, /* WF_MCU_WDT */
410 	{ 0x80010000, 0x4d4000, 0x01000 }, /* WF_AXIDMA */
411 	{ 0x0, 0x0, 0x0 }, /* imply end of search */
450 		u32 ofs = is_mt798x(&dev->mt76) ? 0x400000 : 0;  in mt7915_reg_map_l2()
472 	if (addr < 0x100000)  in __mt7915_reg_addr()
480 	for (i = 0; i < dev->reg.map_size; i++) {  in __mt7915_reg_addr()
580 	for (i = 0; i < dev->mt76.rx_token_size; i++) {  in mt7915_mmio_wed_release_rx_buf()
608 	for (i = 0; i < size; i++) {  in mt7915_mmio_wed_init_rx_buf()
629 		if (token < 0) {  in mt7915_mmio_wed_init_rx_buf()
639 	return 0;  in mt7915_mmio_wed_init_rx_buf()
718 		return 0;  in mt7915_mmio_wed_init()
726 					      pci_resource_start(pci_dev, 0),  in mt7915_mmio_wed_init()
727 					      pci_resource_len(pci_dev, 0));  in mt7915_mmio_wed_init()
728 		wed->wlan.phy_base = pci_resource_start(pci_dev, 0);  in mt7915_mmio_wed_init()
729 		wed->wlan.wpdma_int = pci_resource_start(pci_dev, 0) +  in mt7915_mmio_wed_init()
731 		wed->wlan.wpdma_mask = pci_resource_start(pci_dev, 0) +  in mt7915_mmio_wed_init()
733 		wed->wlan.wpdma_phys = pci_resource_start(pci_dev, 0) +  in mt7915_mmio_wed_init()
735 		wed->wlan.wpdma_tx = pci_resource_start(pci_dev, 0) +  in mt7915_mmio_wed_init()
737 		wed->wlan.wpdma_txfree = pci_resource_start(pci_dev, 0) +  in mt7915_mmio_wed_init()
739 		wed->wlan.wpdma_rx_glo = pci_resource_start(pci_dev, 0) +  in mt7915_mmio_wed_init()
741 		wed->wlan.wpdma_rx = pci_resource_start(pci_dev, 0) +  in mt7915_mmio_wed_init()
747 		res = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);  in mt7915_mmio_wed_init()
764 	wed->wlan.tx_tbit[0] = is_mt7915(&dev->mt76) ? 4 : 30;  in mt7915_mmio_wed_init()
774 		wed->wlan.rx_tbit[0] = 16;  in mt7915_mmio_wed_init()
777 		wed->wlan.rx_tbit[0] = 22;  in mt7915_mmio_wed_init()
780 		wed->wlan.rx_tbit[0] = 18;  in mt7915_mmio_wed_init()
796 		return 0;  in mt7915_mmio_wed_init()
807 	return 0;  in mt7915_mmio_wed_init()
822 	case 0x7915:  in mt7915_mmio_init()
828 	case 0x7906:  in mt7915_mmio_init()
834 	case 0x7981:  in mt7915_mmio_init()
835 	case 0x7986:  in mt7915_mmio_init()
857 		    (mt76_rr(dev, MT_HW_REV) & 0xff);  in mt7915_mmio_init()
860 	return 0;  in mt7915_mmio_init()
903 		mtk_wed_device_irq_set_mask(wed, 0);  in mt7915_irq_tasklet()
905 			mt76_wr(dev, MT_INT1_MASK_CSR, 0);  in mt7915_irq_tasklet()
908 		mt76_wr(dev, MT_INT_MASK_CSR, 0);  in mt7915_irq_tasklet()
910 			mt76_wr(dev, MT_INT1_MASK_CSR, 0);  in mt7915_irq_tasklet()
972 		mtk_wed_device_irq_set_mask(wed, 0);  in mt7915_irq_handler()
974 		mt76_wr(dev, MT_INT_MASK_CSR, 0);  in mt7915_irq_handler()
977 		mt76_wr(dev, MT_INT1_MASK_CSR, 0);  in mt7915_irq_handler()
1050 	return 0;  in mt7915_init()