Lines Matching +full:0 +full:x7c000000
15 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
16 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
17 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
18 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
19 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
20 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
21 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
22 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
23 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
24 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
28 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
29 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
30 { 0x56000000, 0x04000, 0x1000 }, /* WFDMA reserved */
31 { 0x57000000, 0x05000, 0x1000 }, /* WFDMA MCU wrap CR */
32 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
33 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
34 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
35 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
36 { 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */
37 { 0x74030000, 0x10000, 0x1000 }, /* PCIe MAC */
38 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
39 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
40 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
41 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
42 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
43 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
44 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
45 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
46 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
47 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
48 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
49 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
50 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
51 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
52 { 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
53 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
54 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
55 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
56 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
57 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
58 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
59 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
60 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
61 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
62 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
63 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
64 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
65 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
66 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
67 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
68 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
69 { 0x820cc000, 0xa5000, 0x2000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
70 { 0x820c4000, 0xa8000, 0x4000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
71 { 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */
72 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
73 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
74 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, wfdma */
75 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
76 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
77 { 0x0, 0x0, 0x0 }, /* imply end of search */
115 dev->reg_l1_backup = 0; in mt7996_reg_remap_restore()
120 dev->reg_l2_backup = 0; in mt7996_reg_remap_restore()
130 if (addr < 0x100000) in __mt7996_reg_addr()
133 for (i = 0; i < dev->reg.map_size; i++) { in __mt7996_reg_addr()
209 case 0x7990: in mt7996_mmio_init()
229 mdev->rev = (device_id << 16) | (mt76_rr(dev, MT_HW_REV) & 0xff); in mt7996_mmio_init()
233 return 0; in mt7996_mmio_init()
269 mt76_wr(dev, MT_INT_MASK_CSR, 0); in mt7996_irq_tasklet()
271 mt76_wr(dev, MT_INT1_MASK_CSR, 0); in mt7996_irq_tasklet()
295 for (i = 0; i < __MT_RXQ_MAX; i++) { in mt7996_irq_tasklet()
315 mt76_wr(dev, MT_INT_MASK_CSR, 0); in mt7996_irq_handler()
317 mt76_wr(dev, MT_INT1_MASK_CSR, 0); in mt7996_irq_handler()
365 mt76_wr(dev, MT_INT_MASK_CSR, 0); in mt7996_mmio_probe()