16c92544dSBjoern A. Zeeb /* SPDX-License-Identifier: ISC */ 26c92544dSBjoern A. Zeeb /* Copyright (C) 2019 MediaTek Inc. */ 36c92544dSBjoern A. Zeeb 46c92544dSBjoern A. Zeeb #ifndef __MT7615_REGS_H 56c92544dSBjoern A. Zeeb #define __MT7615_REGS_H 66c92544dSBjoern A. Zeeb 76c92544dSBjoern A. Zeeb enum mt7615_reg_base { 86c92544dSBjoern A. Zeeb MT_TOP_CFG_BASE, 96c92544dSBjoern A. Zeeb MT_HW_BASE, 106c92544dSBjoern A. Zeeb MT_DMA_SHDL_BASE, 116c92544dSBjoern A. Zeeb MT_PCIE_REMAP_2, 126c92544dSBjoern A. Zeeb MT_ARB_BASE, 136c92544dSBjoern A. Zeeb MT_HIF_BASE, 146c92544dSBjoern A. Zeeb MT_CSR_BASE, 156c92544dSBjoern A. Zeeb MT_PLE_BASE, 166c92544dSBjoern A. Zeeb MT_PSE_BASE, 176c92544dSBjoern A. Zeeb MT_CFG_BASE, 186c92544dSBjoern A. Zeeb MT_AGG_BASE, 196c92544dSBjoern A. Zeeb MT_TMAC_BASE, 206c92544dSBjoern A. Zeeb MT_RMAC_BASE, 216c92544dSBjoern A. Zeeb MT_DMA_BASE, 226c92544dSBjoern A. Zeeb MT_PF_BASE, 236c92544dSBjoern A. Zeeb MT_WTBL_BASE_ON, 246c92544dSBjoern A. Zeeb MT_WTBL_BASE_OFF, 256c92544dSBjoern A. Zeeb MT_LPON_BASE, 266c92544dSBjoern A. Zeeb MT_MIB_BASE, 276c92544dSBjoern A. Zeeb MT_WTBL_BASE_ADDR, 286c92544dSBjoern A. Zeeb MT_PCIE_REMAP_BASE2, 296c92544dSBjoern A. Zeeb MT_TOP_MISC_BASE, 306c92544dSBjoern A. Zeeb MT_EFUSE_ADDR_BASE, 316c92544dSBjoern A. Zeeb MT_PP_BASE, 326c92544dSBjoern A. Zeeb __MT_BASE_MAX, 336c92544dSBjoern A. Zeeb }; 346c92544dSBjoern A. Zeeb 356c92544dSBjoern A. Zeeb #define MT_HW_INFO_BASE ((dev)->reg_map[MT_HW_BASE]) 366c92544dSBjoern A. Zeeb #define MT_HW_INFO(ofs) (MT_HW_INFO_BASE + (ofs)) 376c92544dSBjoern A. Zeeb #define MT_HW_REV MT_HW_INFO(0x000) 386c92544dSBjoern A. Zeeb #define MT_HW_CHIPID MT_HW_INFO(0x008) 396c92544dSBjoern A. Zeeb #define MT_TOP_STRAP_STA MT_HW_INFO(0x010) 406c92544dSBjoern A. Zeeb #define MT_TOP_3NSS BIT(24) 416c92544dSBjoern A. Zeeb 426c92544dSBjoern A. Zeeb #define MT_TOP_OFF_RSV 0x1128 436c92544dSBjoern A. Zeeb #define MT_TOP_OFF_RSV_FW_STATE GENMASK(18, 16) 446c92544dSBjoern A. Zeeb 456c92544dSBjoern A. Zeeb #define MT_TOP_MISC2 ((dev)->reg_map[MT_TOP_CFG_BASE] + 0x134) 466c92544dSBjoern A. Zeeb #define MT_TOP_MISC2_FW_STATE GENMASK(2, 0) 476c92544dSBjoern A. Zeeb 486c92544dSBjoern A. Zeeb #define MT7663_TOP_MISC2_FW_STATE GENMASK(3, 1) 496c92544dSBjoern A. Zeeb #define MT_TOP_MISC2_FW_PWR_ON BIT(1) 506c92544dSBjoern A. Zeeb 516c92544dSBjoern A. Zeeb #define MT_MCU_BASE 0x2000 526c92544dSBjoern A. Zeeb #define MT_MCU(ofs) (MT_MCU_BASE + (ofs)) 536c92544dSBjoern A. Zeeb 546c92544dSBjoern A. Zeeb #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500) 556c92544dSBjoern A. Zeeb #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0) 566c92544dSBjoern A. Zeeb #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18) 576c92544dSBjoern A. Zeeb #define MT_PCIE_REMAP_BASE_1 0x40000 586c92544dSBjoern A. Zeeb 596c92544dSBjoern A. Zeeb #define MT_MCU_PCIE_REMAP_2 ((dev)->reg_map[MT_PCIE_REMAP_2]) 606c92544dSBjoern A. Zeeb #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0) 616c92544dSBjoern A. Zeeb #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19) 626c92544dSBjoern A. Zeeb #define MT_PCIE_REMAP_BASE_2 ((dev)->reg_map[MT_PCIE_REMAP_BASE2]) 636c92544dSBjoern A. Zeeb 646c92544dSBjoern A. Zeeb #define MT_MCU_CIRQ_BASE 0xc0000 656c92544dSBjoern A. Zeeb #define MT_MCU_CIRQ(ofs) (MT_MCU_CIRQ_BASE + (ofs)) 666c92544dSBjoern A. Zeeb 676c92544dSBjoern A. Zeeb #define MT_MCU_CIRQ_IRQ_SEL(n) MT_MCU_CIRQ((n) << 2) 686c92544dSBjoern A. Zeeb 696c92544dSBjoern A. Zeeb #define MT_HIF(ofs) ((dev)->reg_map[MT_HIF_BASE] + (ofs)) 706c92544dSBjoern A. Zeeb #define MT_HIF_RST MT_HIF(0x100) 716c92544dSBjoern A. Zeeb #define MT_HIF_LOGIC_RST_N BIT(4) 726c92544dSBjoern A. Zeeb 736c92544dSBjoern A. Zeeb #define MT_PDMA_SLP_PROT MT_HIF(0x154) 746c92544dSBjoern A. Zeeb #define MT_PDMA_AXI_SLPPROT_ENABLE BIT(0) 756c92544dSBjoern A. Zeeb #define MT_PDMA_AXI_SLPPROT_RDY BIT(16) 766c92544dSBjoern A. Zeeb 776c92544dSBjoern A. Zeeb #define MT_PDMA_BUSY_STATUS MT_HIF(0x168) 786c92544dSBjoern A. Zeeb #define MT_PDMA_TX_IDX_BUSY BIT(2) 796c92544dSBjoern A. Zeeb #define MT_PDMA_BUSY_IDX BIT(31) 806c92544dSBjoern A. Zeeb 816c92544dSBjoern A. Zeeb #define MT_WPDMA_TX_RING0_CTRL0 MT_HIF(0x300) 826c92544dSBjoern A. Zeeb #define MT_WPDMA_TX_RING0_CTRL1 MT_HIF(0x304) 836c92544dSBjoern A. Zeeb 846c92544dSBjoern A. Zeeb #define MT7663_MCU_PCIE_REMAP_2_OFFSET GENMASK(15, 0) 856c92544dSBjoern A. Zeeb #define MT7663_MCU_PCIE_REMAP_2_BASE GENMASK(31, 16) 866c92544dSBjoern A. Zeeb 876c92544dSBjoern A. Zeeb #define MT_HIF2_BASE 0xf0000 886c92544dSBjoern A. Zeeb #define MT_HIF2(ofs) (MT_HIF2_BASE + (ofs)) 896c92544dSBjoern A. Zeeb #define MT_PCIE_IRQ_ENABLE MT_HIF2(0x188) 906c92544dSBjoern A. Zeeb #define MT_PCIE_DOORBELL_PUSH MT_HIF2(0x1484) 916c92544dSBjoern A. Zeeb 926c92544dSBjoern A. Zeeb #define MT_CFG_LPCR_HOST MT_HIF(0x1f0) 936c92544dSBjoern A. Zeeb #define MT_CFG_LPCR_HOST_FW_OWN BIT(0) 946c92544dSBjoern A. Zeeb #define MT_CFG_LPCR_HOST_DRV_OWN BIT(1) 956c92544dSBjoern A. Zeeb 966c92544dSBjoern A. Zeeb #define MT_MCU2HOST_INT_STATUS MT_HIF(0x1f0) 976c92544dSBjoern A. Zeeb #define MT_MCU2HOST_INT_ENABLE MT_HIF(0x1f4) 986c92544dSBjoern A. Zeeb 996c92544dSBjoern A. Zeeb #define MT7663_MCU_INT_EVENT MT_HIF(0x108) 1006c92544dSBjoern A. Zeeb #define MT_MCU_INT_EVENT MT_HIF(0x1f8) 1016c92544dSBjoern A. Zeeb #define MT_MCU_INT_EVENT_PDMA_STOPPED BIT(0) 1026c92544dSBjoern A. Zeeb #define MT_MCU_INT_EVENT_PDMA_INIT BIT(1) 1036c92544dSBjoern A. Zeeb #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2) 1046c92544dSBjoern A. Zeeb #define MT_MCU_INT_EVENT_RESET_DONE BIT(3) 1056c92544dSBjoern A. Zeeb 1066c92544dSBjoern A. Zeeb #define MT_INT_SOURCE_CSR MT_HIF(0x200) 1076c92544dSBjoern A. Zeeb #define MT_INT_MASK_CSR MT_HIF(0x204) 1086c92544dSBjoern A. Zeeb #define MT_DELAY_INT_CFG MT_HIF(0x210) 1096c92544dSBjoern A. Zeeb 1106c92544dSBjoern A. Zeeb #define MT_INT_RX_DONE(_n) BIT(_n) 1116c92544dSBjoern A. Zeeb #define MT_INT_RX_DONE_ALL GENMASK(1, 0) 1126c92544dSBjoern A. Zeeb #define MT_INT_TX_DONE_ALL GENMASK(19, 4) 1136c92544dSBjoern A. Zeeb #define MT_INT_TX_DONE(_n) BIT((_n) + 4) 1146c92544dSBjoern A. Zeeb #define MT7663_INT_MCU_CMD BIT(29) 1156c92544dSBjoern A. Zeeb #define MT_INT_MCU_CMD BIT(30) 1166c92544dSBjoern A. Zeeb 1176c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG MT_HIF(0x208) 1186c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0) 1196c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1) 1206c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2) 1216c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3) 1226c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4) 1236c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6) 1246c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) 1256c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0 BIT(9) 1266c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_BYPASS_TX_SCH BIT(9) /* MT7622 */ 1276c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10) 1286c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12) 1296c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21 GENMASK(23, 22) 1306c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_SW_RESET BIT(24) 1316c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26) 1326c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28) 1336c92544dSBjoern A. Zeeb 1346c92544dSBjoern A. Zeeb #define MT_WPDMA_RST_IDX MT_HIF(0x20c) 1356c92544dSBjoern A. Zeeb 1366c92544dSBjoern A. Zeeb #define MT_WPDMA_MEM_RNG_ERR MT_HIF(0x224) 1376c92544dSBjoern A. Zeeb 1386c92544dSBjoern A. Zeeb #define MT_MCU_CMD MT_HIF(0x234) 1396c92544dSBjoern A. Zeeb #define MT_MCU_CMD_CLEAR_FW_OWN BIT(0) 1406c92544dSBjoern A. Zeeb #define MT_MCU_CMD_STOP_PDMA_FW_RELOAD BIT(1) 1416c92544dSBjoern A. Zeeb #define MT_MCU_CMD_STOP_PDMA BIT(2) 1426c92544dSBjoern A. Zeeb #define MT_MCU_CMD_RESET_DONE BIT(3) 1436c92544dSBjoern A. Zeeb #define MT_MCU_CMD_RECOVERY_DONE BIT(4) 1446c92544dSBjoern A. Zeeb #define MT_MCU_CMD_NORMAL_STATE BIT(5) 1456c92544dSBjoern A. Zeeb #define MT_MCU_CMD_LMAC_ERROR BIT(24) 1466c92544dSBjoern A. Zeeb #define MT_MCU_CMD_PSE_ERROR BIT(25) 1476c92544dSBjoern A. Zeeb #define MT_MCU_CMD_PLE_ERROR BIT(26) 1486c92544dSBjoern A. Zeeb #define MT_MCU_CMD_PDMA_ERROR BIT(27) 1496c92544dSBjoern A. Zeeb #define MT_MCU_CMD_PCIE_ERROR BIT(28) 1506c92544dSBjoern A. Zeeb #define MT_MCU_CMD_ERROR_MASK (GENMASK(5, 1) | GENMASK(28, 24)) 1516c92544dSBjoern A. Zeeb #define MT7663_MCU_CMD_ERROR_MASK GENMASK(5, 2) 1526c92544dSBjoern A. Zeeb 1536c92544dSBjoern A. Zeeb #define MT_TX_RING_BASE MT_HIF(0x300) 1546c92544dSBjoern A. Zeeb #define MT_RX_RING_BASE MT_HIF(0x400) 1556c92544dSBjoern A. Zeeb 1566c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG1 MT_HIF(0x500) 1576c92544dSBjoern A. Zeeb #define MT_WPDMA_TX_PRE_CFG MT_HIF(0x510) 1586c92544dSBjoern A. Zeeb #define MT_WPDMA_RX_PRE_CFG MT_HIF(0x520) 1596c92544dSBjoern A. Zeeb #define MT_WPDMA_ABT_CFG MT_HIF(0x530) 1606c92544dSBjoern A. Zeeb #define MT_WPDMA_ABT_CFG1 MT_HIF(0x534) 1616c92544dSBjoern A. Zeeb 1626c92544dSBjoern A. Zeeb #define MT_CSR(ofs) ((dev)->reg_map[MT_CSR_BASE] + (ofs)) 1636c92544dSBjoern A. Zeeb #define MT_CONN_HIF_ON_LPCTL MT_CSR(0x000) 1646c92544dSBjoern A. Zeeb 1656c92544dSBjoern A. Zeeb #define MT_PLE(ofs) ((dev)->reg_map[MT_PLE_BASE] + (ofs)) 1666c92544dSBjoern A. Zeeb 1676c92544dSBjoern A. Zeeb #define MT_PLE_PG_HIF0_GROUP MT_PLE(0x110) 1686c92544dSBjoern A. Zeeb #define MT_HIF0_MIN_QUOTA GENMASK(11, 0) 1696c92544dSBjoern A. Zeeb #define MT_PLE_FL_Q0_CTRL MT_PLE(0x1b0) 1706c92544dSBjoern A. Zeeb #define MT_PLE_FL_Q1_CTRL MT_PLE(0x1b4) 1716c92544dSBjoern A. Zeeb #define MT_PLE_FL_Q2_CTRL MT_PLE(0x1b8) 1726c92544dSBjoern A. Zeeb #define MT_PLE_FL_Q3_CTRL MT_PLE(0x1bc) 1736c92544dSBjoern A. Zeeb 1746c92544dSBjoern A. Zeeb #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x300 + 0x10 * (ac) + \ 1756c92544dSBjoern A. Zeeb ((n) << 2)) 1766c92544dSBjoern A. Zeeb 1776c92544dSBjoern A. Zeeb #define MT_PSE(ofs) ((dev)->reg_map[MT_PSE_BASE] + (ofs)) 1786c92544dSBjoern A. Zeeb #define MT_PSE_PG_HIF0_GROUP MT_PSE(0x110) 1796c92544dSBjoern A. Zeeb #define MT_HIF0_MIN_QUOTA GENMASK(11, 0) 1806c92544dSBjoern A. Zeeb #define MT_PSE_PG_HIF1_GROUP MT_PSE(0x118) 1816c92544dSBjoern A. Zeeb #define MT_HIF1_MIN_QUOTA GENMASK(11, 0) 1826c92544dSBjoern A. Zeeb #define MT_PSE_QUEUE_EMPTY MT_PSE(0x0b4) 1836c92544dSBjoern A. Zeeb #define MT_HIF_0_EMPTY_MASK BIT(16) 1846c92544dSBjoern A. Zeeb #define MT_HIF_1_EMPTY_MASK BIT(17) 1856c92544dSBjoern A. Zeeb #define MT_HIF_ALL_EMPTY_MASK GENMASK(17, 16) 1866c92544dSBjoern A. Zeeb #define MT_PSE_PG_INFO MT_PSE(0x194) 1876c92544dSBjoern A. Zeeb #define MT_PSE_SRC_CNT GENMASK(27, 16) 1886c92544dSBjoern A. Zeeb 1896c92544dSBjoern A. Zeeb #define MT_PP(ofs) ((dev)->reg_map[MT_PP_BASE] + (ofs)) 1906c92544dSBjoern A. Zeeb #define MT_PP_TXDWCNT MT_PP(0x0) 1916c92544dSBjoern A. Zeeb #define MT_PP_TXDWCNT_TX0_ADD_DW_CNT GENMASK(7, 0) 1926c92544dSBjoern A. Zeeb #define MT_PP_TXDWCNT_TX1_ADD_DW_CNT GENMASK(15, 8) 1936c92544dSBjoern A. Zeeb 1946c92544dSBjoern A. Zeeb #define MT_WF_PHY_BASE 0x82070000 1956c92544dSBjoern A. Zeeb #define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs)) 1966c92544dSBjoern A. Zeeb 1976c92544dSBjoern A. Zeeb #define MT_WF_PHY_WF2_RFCTRL0(n) MT_WF_PHY(0x1900 + (n) * 0x400) 1986c92544dSBjoern A. Zeeb #define MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN BIT(9) 1996c92544dSBjoern A. Zeeb 2006c92544dSBjoern A. Zeeb #define MT_WF_PHY_R0_PHYMUX_5(_phy) MT_WF_PHY(0x0614 + ((_phy) << 9)) 2016c92544dSBjoern A. Zeeb #define MT7663_WF_PHY_R0_PHYMUX_5 MT_WF_PHY(0x0414) 2026c92544dSBjoern A. Zeeb 2036c92544dSBjoern A. Zeeb #define MT_WF_PHY_R0_PHYCTRL_STS0(_phy) MT_WF_PHY(0x020c + ((_phy) << 9)) 2046c92544dSBjoern A. Zeeb #define MT_WF_PHYCTRL_STAT_PD_OFDM GENMASK(31, 16) 2056c92544dSBjoern A. Zeeb #define MT_WF_PHYCTRL_STAT_PD_CCK GENMASK(15, 0) 2066c92544dSBjoern A. Zeeb 2076c92544dSBjoern A. Zeeb #define MT7663_WF_PHY_R0_PHYCTRL_STS0(_phy) MT_WF_PHY(0x0210 + ((_phy) << 12)) 2086c92544dSBjoern A. Zeeb 2096c92544dSBjoern A. Zeeb #define MT_WF_PHY_R0_PHYCTRL_STS5(_phy) MT_WF_PHY(0x0220 + ((_phy) << 9)) 2106c92544dSBjoern A. Zeeb #define MT_WF_PHYCTRL_STAT_MDRDY_OFDM GENMASK(31, 16) 2116c92544dSBjoern A. Zeeb #define MT_WF_PHYCTRL_STAT_MDRDY_CCK GENMASK(15, 0) 2126c92544dSBjoern A. Zeeb 2136c92544dSBjoern A. Zeeb #define MT7663_WF_PHY_R0_PHYCTRL_STS5(_phy) MT_WF_PHY(0x0224 + ((_phy) << 12)) 2146c92544dSBjoern A. Zeeb 215*cbb3ec25SBjoern A. Zeeb #define MT_WF_PHY_GID_TAB_VLD(_phy, i) MT_WF_PHY(0x0254 + (i) * 4 + \ 216*cbb3ec25SBjoern A. Zeeb ((_phy) << 9)) 217*cbb3ec25SBjoern A. Zeeb #define MT7663_WF_PHY_GID_TAB_VLD(_phy, i) MT_WF_PHY(0x0254 + (i) * 4 + \ 218*cbb3ec25SBjoern A. Zeeb ((_phy) << 12)) 219*cbb3ec25SBjoern A. Zeeb #define MT_WF_PHY_GID_TAB_POS(_phy, i) MT_WF_PHY(0x025c + (i) * 4 + \ 220*cbb3ec25SBjoern A. Zeeb ((_phy) << 9)) 221*cbb3ec25SBjoern A. Zeeb #define MT7663_WF_PHY_GID_TAB_POS(_phy, i) MT_WF_PHY(0x025c + (i) * 4 + \ 222*cbb3ec25SBjoern A. Zeeb ((_phy) << 12)) 223*cbb3ec25SBjoern A. Zeeb 2246c92544dSBjoern A. Zeeb #define MT_WF_PHY_MIN_PRI_PWR(_phy) MT_WF_PHY((_phy) ? 0x084 : 0x229c) 2256c92544dSBjoern A. Zeeb #define MT_WF_PHY_PD_OFDM_MASK(_phy) ((_phy) ? GENMASK(24, 16) : \ 2266c92544dSBjoern A. Zeeb GENMASK(28, 20)) 2276c92544dSBjoern A. Zeeb #define MT_WF_PHY_PD_OFDM(_phy, v) ((v) << ((_phy) ? 16 : 20)) 2286c92544dSBjoern A. Zeeb #define MT_WF_PHY_PD_BLK(_phy) ((_phy) ? BIT(25) : BIT(19)) 2296c92544dSBjoern A. Zeeb 2306c92544dSBjoern A. Zeeb #define MT7663_WF_PHY_MIN_PRI_PWR(_phy) MT_WF_PHY((_phy) ? 0x2aec : 0x22f0) 2316c92544dSBjoern A. Zeeb 2326c92544dSBjoern A. Zeeb #define MT_WF_PHY_RXTD_BASE MT_WF_PHY(0x2200) 2336c92544dSBjoern A. Zeeb #define MT_WF_PHY_RXTD(_n) (MT_WF_PHY_RXTD_BASE + ((_n) << 2)) 2346c92544dSBjoern A. Zeeb 2356c92544dSBjoern A. Zeeb #define MT7663_WF_PHY_RXTD(_n) (MT_WF_PHY(0x25b0) + ((_n) << 2)) 2366c92544dSBjoern A. Zeeb 2376c92544dSBjoern A. Zeeb #define MT_WF_PHY_RXTD_CCK_PD(_phy) MT_WF_PHY((_phy) ? 0x2314 : 0x2310) 2386c92544dSBjoern A. Zeeb #define MT_WF_PHY_PD_CCK_MASK(_phy) (_phy) ? GENMASK(31, 24) : \ 2396c92544dSBjoern A. Zeeb GENMASK(8, 1) 2406c92544dSBjoern A. Zeeb #define MT_WF_PHY_PD_CCK(_phy, v) ((v) << ((_phy) ? 24 : 1)) 2416c92544dSBjoern A. Zeeb 2426c92544dSBjoern A. Zeeb #define MT7663_WF_PHY_RXTD_CCK_PD(_phy) MT_WF_PHY((_phy) ? 0x2350 : 0x234c) 2436c92544dSBjoern A. Zeeb 2446c92544dSBjoern A. Zeeb #define MT_WF_PHY_RXTD2_BASE MT_WF_PHY(0x2a00) 2456c92544dSBjoern A. Zeeb #define MT_WF_PHY_RXTD2(_n) (MT_WF_PHY_RXTD2_BASE + ((_n) << 2)) 2466c92544dSBjoern A. Zeeb 2476c92544dSBjoern A. Zeeb #define MT_WF_PHY_RFINTF3_0(_n) MT_WF_PHY(0x1100 + (_n) * 0x400) 2486c92544dSBjoern A. Zeeb #define MT_WF_PHY_RFINTF3_0_ANT GENMASK(7, 4) 2496c92544dSBjoern A. Zeeb 2506c92544dSBjoern A. Zeeb #define MT_WF_CFG_BASE ((dev)->reg_map[MT_CFG_BASE]) 2516c92544dSBjoern A. Zeeb #define MT_WF_CFG(ofs) (MT_WF_CFG_BASE + (ofs)) 2526c92544dSBjoern A. Zeeb 2536c92544dSBjoern A. Zeeb #define MT_CFG_CCR MT_WF_CFG(0x000) 2546c92544dSBjoern A. Zeeb #define MT_CFG_CCR_MAC_D1_1X_GC_EN BIT(24) 2556c92544dSBjoern A. Zeeb #define MT_CFG_CCR_MAC_D0_1X_GC_EN BIT(25) 2566c92544dSBjoern A. Zeeb #define MT_CFG_CCR_MAC_D1_2X_GC_EN BIT(30) 2576c92544dSBjoern A. Zeeb #define MT_CFG_CCR_MAC_D0_2X_GC_EN BIT(31) 2586c92544dSBjoern A. Zeeb 2596c92544dSBjoern A. Zeeb #define MT_WF_AGG_BASE ((dev)->reg_map[MT_AGG_BASE]) 2606c92544dSBjoern A. Zeeb #define MT_WF_AGG(ofs) (MT_WF_AGG_BASE + (ofs)) 2616c92544dSBjoern A. Zeeb 2626c92544dSBjoern A. Zeeb #define MT_AGG_ARCR MT_WF_AGG(0x010) 2636c92544dSBjoern A. Zeeb #define MT_AGG_ARCR_INIT_RATE1 BIT(0) 2646c92544dSBjoern A. Zeeb #define MT_AGG_ARCR_RTS_RATE_THR GENMASK(12, 8) 2656c92544dSBjoern A. Zeeb #define MT_AGG_ARCR_RATE_DOWN_RATIO GENMASK(17, 16) 2666c92544dSBjoern A. Zeeb #define MT_AGG_ARCR_RATE_DOWN_RATIO_EN BIT(19) 2676c92544dSBjoern A. Zeeb #define MT_AGG_ARCR_RATE_UP_EXTRA_TH GENMASK(22, 20) 2686c92544dSBjoern A. Zeeb 2696c92544dSBjoern A. Zeeb #define MT_AGG_ARUCR(_band) MT_WF_AGG(0x018 + (_band) * 0x100) 2706c92544dSBjoern A. Zeeb #define MT_AGG_ARDCR(_band) MT_WF_AGG(0x01c + (_band) * 0x100) 2716c92544dSBjoern A. Zeeb #define MT_AGG_ARxCR_LIMIT_SHIFT(_n) (4 * (_n)) 2726c92544dSBjoern A. Zeeb #define MT_AGG_ARxCR_LIMIT(_n) GENMASK(2 + \ 2736c92544dSBjoern A. Zeeb MT_AGG_ARxCR_LIMIT_SHIFT(_n), \ 2746c92544dSBjoern A. Zeeb MT_AGG_ARxCR_LIMIT_SHIFT(_n)) 2756c92544dSBjoern A. Zeeb 2766c92544dSBjoern A. Zeeb #define MT_AGG_ASRCR0 MT_WF_AGG(0x060) 2776c92544dSBjoern A. Zeeb #define MT_AGG_ASRCR1 MT_WF_AGG(0x064) 2786c92544dSBjoern A. Zeeb #define MT_AGG_ASRCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(5, 0)) 2796c92544dSBjoern A. Zeeb 2806c92544dSBjoern A. Zeeb #define MT_AGG_ACR(_band) MT_WF_AGG(0x070 + (_band) * 0x100) 2816c92544dSBjoern A. Zeeb #define MT_AGG_ACR_NO_BA_RULE BIT(0) 2826c92544dSBjoern A. Zeeb #define MT_AGG_ACR_NO_BA_AR_RULE BIT(1) 2836c92544dSBjoern A. Zeeb #define MT_AGG_ACR_PKT_TIME_EN BIT(2) 2846c92544dSBjoern A. Zeeb #define MT_AGG_ACR_CFEND_RATE GENMASK(15, 4) 2856c92544dSBjoern A. Zeeb #define MT_AGG_ACR_BAR_RATE GENMASK(31, 20) 2866c92544dSBjoern A. Zeeb 2876c92544dSBjoern A. Zeeb #define MT_AGG_SCR MT_WF_AGG(0x0fc) 2886c92544dSBjoern A. Zeeb #define MT_AGG_SCR_NLNAV_MID_PTEC_DIS BIT(3) 2896c92544dSBjoern A. Zeeb 2906c92544dSBjoern A. Zeeb #define MT_WF_ARB_BASE ((dev)->reg_map[MT_ARB_BASE]) 2916c92544dSBjoern A. Zeeb #define MT_WF_ARB(ofs) (MT_WF_ARB_BASE + (ofs)) 2926c92544dSBjoern A. Zeeb 2936c92544dSBjoern A. Zeeb #define MT_ARB_RQCR MT_WF_ARB(0x070) 2946c92544dSBjoern A. Zeeb #define MT_ARB_RQCR_RX_START BIT(0) 2956c92544dSBjoern A. Zeeb #define MT_ARB_RQCR_RXV_START BIT(4) 2966c92544dSBjoern A. Zeeb #define MT_ARB_RQCR_RXV_R_EN BIT(7) 2976c92544dSBjoern A. Zeeb #define MT_ARB_RQCR_RXV_T_EN BIT(8) 2986c92544dSBjoern A. Zeeb #define MT_ARB_RQCR_BAND_SHIFT 16 2996c92544dSBjoern A. Zeeb 3006c92544dSBjoern A. Zeeb #define MT_ARB_SCR MT_WF_ARB(0x080) 3016c92544dSBjoern A. Zeeb #define MT_ARB_SCR_TX0_DISABLE BIT(8) 3026c92544dSBjoern A. Zeeb #define MT_ARB_SCR_RX0_DISABLE BIT(9) 3036c92544dSBjoern A. Zeeb #define MT_ARB_SCR_TX1_DISABLE BIT(10) 3046c92544dSBjoern A. Zeeb #define MT_ARB_SCR_RX1_DISABLE BIT(11) 3056c92544dSBjoern A. Zeeb 3066c92544dSBjoern A. Zeeb #define MT_WF_TMAC_BASE ((dev)->reg_map[MT_TMAC_BASE]) 3076c92544dSBjoern A. Zeeb #define MT_WF_TMAC(ofs) (MT_WF_TMAC_BASE + (ofs)) 3086c92544dSBjoern A. Zeeb 3096c92544dSBjoern A. Zeeb #define MT_TMAC_CDTR MT_WF_TMAC(0x090) 3106c92544dSBjoern A. Zeeb #define MT_TMAC_ODTR MT_WF_TMAC(0x094) 3116c92544dSBjoern A. Zeeb #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) 3126c92544dSBjoern A. Zeeb #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) 3136c92544dSBjoern A. Zeeb 3146c92544dSBjoern A. Zeeb #define MT_TMAC_TRCR(_band) MT_WF_TMAC((_band) ? 0x070 : 0x09c) 3156c92544dSBjoern A. Zeeb #define MT_TMAC_TRCR_CCA_SEL GENMASK(31, 30) 3166c92544dSBjoern A. Zeeb #define MT_TMAC_TRCR_SEC_CCA_SEL GENMASK(29, 28) 3176c92544dSBjoern A. Zeeb 3186c92544dSBjoern A. Zeeb #define MT_TMAC_ICR(_band) MT_WF_TMAC((_band) ? 0x074 : 0x0a4) 3196c92544dSBjoern A. Zeeb #define MT_IFS_EIFS GENMASK(8, 0) 3206c92544dSBjoern A. Zeeb #define MT_IFS_RIFS GENMASK(14, 10) 3216c92544dSBjoern A. Zeeb #define MT_IFS_SIFS GENMASK(22, 16) 3226c92544dSBjoern A. Zeeb #define MT_IFS_SLOT GENMASK(30, 24) 3236c92544dSBjoern A. Zeeb 3246c92544dSBjoern A. Zeeb #define MT_TMAC_CTCR0 MT_WF_TMAC(0x0f4) 3256c92544dSBjoern A. Zeeb #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0) 3266c92544dSBjoern A. Zeeb #define MT_TMAC_CTCR0_INS_DDLMT_DENSITY GENMASK(15, 12) 3276c92544dSBjoern A. Zeeb #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17) 3286c92544dSBjoern A. Zeeb #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18) 3296c92544dSBjoern A. Zeeb 3306c92544dSBjoern A. Zeeb #define MT_WF_RMAC_BASE ((dev)->reg_map[MT_RMAC_BASE]) 3316c92544dSBjoern A. Zeeb #define MT_WF_RMAC(ofs) (MT_WF_RMAC_BASE + (ofs)) 3326c92544dSBjoern A. Zeeb 3336c92544dSBjoern A. Zeeb #define MT_WF_RFCR(_band) MT_WF_RMAC((_band) ? 0x100 : 0x000) 3346c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) 3356c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) 3366c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_VERSION BIT(3) 3376c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) 3386c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_MCAST BIT(5) 3396c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_BCAST BIT(6) 3406c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) 3416c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_A3_MAC BIT(8) 3426c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) 3436c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) 3446c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) 3456c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) 3466c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) 3476c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_CTS BIT(14) 3486c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_RTS BIT(15) 3496c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) 3506c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) 3516c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) 3526c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) 3536c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_NDPA BIT(20) 3546c92544dSBjoern A. Zeeb #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) 3556c92544dSBjoern A. Zeeb 3566c92544dSBjoern A. Zeeb #define MT_WF_RMAC_MORE(_band) MT_WF_RMAC((_band) ? 0x124 : 0x024) 3576c92544dSBjoern A. Zeeb #define MT_WF_RMAC_MORE_MUAR_MODE GENMASK(31, 30) 3586c92544dSBjoern A. Zeeb 3596c92544dSBjoern A. Zeeb #define MT_WF_RFCR1(_band) MT_WF_RMAC((_band) ? 0x104 : 0x004) 3606c92544dSBjoern A. Zeeb #define MT_WF_RFCR1_DROP_ACK BIT(4) 3616c92544dSBjoern A. Zeeb #define MT_WF_RFCR1_DROP_BF_POLL BIT(5) 3626c92544dSBjoern A. Zeeb #define MT_WF_RFCR1_DROP_BA BIT(6) 3636c92544dSBjoern A. Zeeb #define MT_WF_RFCR1_DROP_CFEND BIT(7) 3646c92544dSBjoern A. Zeeb #define MT_WF_RFCR1_DROP_CFACK BIT(8) 3656c92544dSBjoern A. Zeeb 3666c92544dSBjoern A. Zeeb #define MT_CHFREQ(_band) MT_WF_RMAC((_band) ? 0x130 : 0x030) 3676c92544dSBjoern A. Zeeb 3686c92544dSBjoern A. Zeeb #define MT_WF_RMAC_MAR0 MT_WF_RMAC(0x025c) 3696c92544dSBjoern A. Zeeb #define MT_WF_RMAC_MAR1 MT_WF_RMAC(0x0260) 3706c92544dSBjoern A. Zeeb #define MT_WF_RMAC_MAR1_ADDR GENMASK(15, 0) 3716c92544dSBjoern A. Zeeb #define MT_WF_RMAC_MAR1_START BIT(16) 3726c92544dSBjoern A. Zeeb #define MT_WF_RMAC_MAR1_WRITE BIT(17) 3736c92544dSBjoern A. Zeeb #define MT_WF_RMAC_MAR1_IDX GENMASK(29, 24) 3746c92544dSBjoern A. Zeeb #define MT_WF_RMAC_MAR1_GROUP GENMASK(31, 30) 3756c92544dSBjoern A. Zeeb 3766c92544dSBjoern A. Zeeb #define MT_WF_RMAC_MIB_TIME0 MT_WF_RMAC(0x03c4) 3776c92544dSBjoern A. Zeeb #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31) 3786c92544dSBjoern A. Zeeb #define MT_WF_RMAC_MIB_RXTIME_EN BIT(30) 3796c92544dSBjoern A. Zeeb 3806c92544dSBjoern A. Zeeb #define MT_WF_RMAC_MIB_AIRTIME0 MT_WF_RMAC(0x0380) 3816c92544dSBjoern A. Zeeb 3826c92544dSBjoern A. Zeeb #define MT_WF_RMAC_MIB_TIME5 MT_WF_RMAC(0x03d8) 3836c92544dSBjoern A. Zeeb #define MT_WF_RMAC_MIB_TIME6 MT_WF_RMAC(0x03dc) 3846c92544dSBjoern A. Zeeb #define MT_MIB_OBSSTIME_MASK GENMASK(23, 0) 3856c92544dSBjoern A. Zeeb 3866c92544dSBjoern A. Zeeb #define MT_WF_DMA_BASE ((dev)->reg_map[MT_DMA_BASE]) 3876c92544dSBjoern A. Zeeb #define MT_WF_DMA(ofs) (MT_WF_DMA_BASE + (ofs)) 3886c92544dSBjoern A. Zeeb 3896c92544dSBjoern A. Zeeb #define MT_DMA_DCR0 MT_WF_DMA(0x000) 3906c92544dSBjoern A. Zeeb #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 2) 3916c92544dSBjoern A. Zeeb #define MT_DMA_DCR0_DAMSDU_EN BIT(16) 3926c92544dSBjoern A. Zeeb #define MT_DMA_DCR0_RX_VEC_DROP BIT(17) 3936c92544dSBjoern A. Zeeb #define MT_DMA_DCR0_RX_HDR_TRANS_EN BIT(19) 3946c92544dSBjoern A. Zeeb 3956c92544dSBjoern A. Zeeb #define MT_DMA_RCFR0(_band) MT_WF_DMA(0x070 + (_band) * 0x40) 3966c92544dSBjoern A. Zeeb #define MT_DMA_RCFR0_MCU_RX_MGMT BIT(2) 3976c92544dSBjoern A. Zeeb #define MT_DMA_RCFR0_MCU_RX_CTL_NON_BAR BIT(3) 3986c92544dSBjoern A. Zeeb #define MT_DMA_RCFR0_MCU_RX_CTL_BAR BIT(4) 3996c92544dSBjoern A. Zeeb #define MT_DMA_RCFR0_MCU_RX_TDLS BIT(19) 4006c92544dSBjoern A. Zeeb #define MT_DMA_RCFR0_MCU_RX_BYPASS BIT(21) 4016c92544dSBjoern A. Zeeb #define MT_DMA_RCFR0_RX_DROPPED_UCAST GENMASK(25, 24) 4026c92544dSBjoern A. Zeeb #define MT_DMA_RCFR0_RX_DROPPED_MCAST GENMASK(27, 26) 4036c92544dSBjoern A. Zeeb 4046c92544dSBjoern A. Zeeb #define MT_WF_PF_BASE ((dev)->reg_map[MT_PF_BASE]) 4056c92544dSBjoern A. Zeeb #define MT_WF_PF(ofs) (MT_WF_PF_BASE + (ofs)) 4066c92544dSBjoern A. Zeeb 4076c92544dSBjoern A. Zeeb #define MT_WF_PFCR MT_WF_PF(0x000) 4086c92544dSBjoern A. Zeeb #define MT_WF_PFCR_TDLS_EN BIT(9) 4096c92544dSBjoern A. Zeeb 4106c92544dSBjoern A. Zeeb #define MT_WTBL_BASE(dev) ((dev)->reg_map[MT_WTBL_BASE_ADDR]) 4116c92544dSBjoern A. Zeeb #define MT_WTBL_ENTRY_SIZE 256 4126c92544dSBjoern A. Zeeb 4136c92544dSBjoern A. Zeeb #define MT_WTBL_OFF_BASE ((dev)->reg_map[MT_WTBL_BASE_OFF]) 4146c92544dSBjoern A. Zeeb #define MT_WTBL_OFF(n) (MT_WTBL_OFF_BASE + (n)) 4156c92544dSBjoern A. Zeeb 4166c92544dSBjoern A. Zeeb #define MT_WTBL_W0_KEY_IDX GENMASK(24, 23) 4176c92544dSBjoern A. Zeeb #define MT_WTBL_W0_RX_KEY_VALID BIT(26) 4186c92544dSBjoern A. Zeeb #define MT_WTBL_W0_RX_IK_VALID BIT(27) 4196c92544dSBjoern A. Zeeb 4206c92544dSBjoern A. Zeeb #define MT_WTBL_W2_KEY_TYPE GENMASK(7, 4) 4216c92544dSBjoern A. Zeeb 4226c92544dSBjoern A. Zeeb #define MT_WTBL_UPDATE MT_WTBL_OFF(0x030) 4236c92544dSBjoern A. Zeeb #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(7, 0) 4246c92544dSBjoern A. Zeeb #define MT_WTBL_UPDATE_RXINFO_UPDATE BIT(11) 4256c92544dSBjoern A. Zeeb #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12) 4266c92544dSBjoern A. Zeeb #define MT_WTBL_UPDATE_RATE_UPDATE BIT(13) 4276c92544dSBjoern A. Zeeb #define MT_WTBL_UPDATE_TX_COUNT_CLEAR BIT(14) 4286c92544dSBjoern A. Zeeb #define MT_WTBL_UPDATE_BUSY BIT(31) 4296c92544dSBjoern A. Zeeb 4306c92544dSBjoern A. Zeeb #define MT_TOP_MISC(ofs) ((dev)->reg_map[MT_TOP_MISC_BASE] + (ofs)) 4316c92544dSBjoern A. Zeeb #define MT_CONN_ON_MISC MT_TOP_MISC(0x1140) 4326c92544dSBjoern A. Zeeb #define MT_TOP_MISC2_FW_N9_RDY BIT(2) 4336c92544dSBjoern A. Zeeb 4346c92544dSBjoern A. Zeeb #define MT_WTBL_ON_BASE ((dev)->reg_map[MT_WTBL_BASE_ON]) 4356c92544dSBjoern A. Zeeb #define MT_WTBL_ON(_n) (MT_WTBL_ON_BASE + (_n)) 4366c92544dSBjoern A. Zeeb 4376c92544dSBjoern A. Zeeb #define MT_WTBL_RICR0 MT_WTBL_ON(0x010) 4386c92544dSBjoern A. Zeeb #define MT_WTBL_RICR1 MT_WTBL_ON(0x014) 4396c92544dSBjoern A. Zeeb 4406c92544dSBjoern A. Zeeb #define MT_WTBL_RIUCR0 MT_WTBL_ON(0x020) 4416c92544dSBjoern A. Zeeb 4426c92544dSBjoern A. Zeeb #define MT_WTBL_RIUCR1 MT_WTBL_ON(0x024) 4436c92544dSBjoern A. Zeeb #define MT_WTBL_RIUCR1_RATE0 GENMASK(11, 0) 4446c92544dSBjoern A. Zeeb #define MT_WTBL_RIUCR1_RATE1 GENMASK(23, 12) 4456c92544dSBjoern A. Zeeb #define MT_WTBL_RIUCR1_RATE2_LO GENMASK(31, 24) 4466c92544dSBjoern A. Zeeb 4476c92544dSBjoern A. Zeeb #define MT_WTBL_RIUCR2 MT_WTBL_ON(0x028) 4486c92544dSBjoern A. Zeeb #define MT_WTBL_RIUCR2_RATE2_HI GENMASK(3, 0) 4496c92544dSBjoern A. Zeeb #define MT_WTBL_RIUCR2_RATE3 GENMASK(15, 4) 4506c92544dSBjoern A. Zeeb #define MT_WTBL_RIUCR2_RATE4 GENMASK(27, 16) 4516c92544dSBjoern A. Zeeb #define MT_WTBL_RIUCR2_RATE5_LO GENMASK(31, 28) 4526c92544dSBjoern A. Zeeb 4536c92544dSBjoern A. Zeeb #define MT_WTBL_RIUCR3 MT_WTBL_ON(0x02c) 4546c92544dSBjoern A. Zeeb #define MT_WTBL_RIUCR3_RATE5_HI GENMASK(7, 0) 4556c92544dSBjoern A. Zeeb #define MT_WTBL_RIUCR3_RATE6 GENMASK(19, 8) 4566c92544dSBjoern A. Zeeb #define MT_WTBL_RIUCR3_RATE7 GENMASK(31, 20) 4576c92544dSBjoern A. Zeeb 458*cbb3ec25SBjoern A. Zeeb #define MT_WTBL_W3_RTS BIT(22) 459*cbb3ec25SBjoern A. Zeeb 4606c92544dSBjoern A. Zeeb #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5) 4616c92544dSBjoern A. Zeeb #define MT_WTBL_W5_SHORT_GI_20 BIT(8) 4626c92544dSBjoern A. Zeeb #define MT_WTBL_W5_SHORT_GI_40 BIT(9) 4636c92544dSBjoern A. Zeeb #define MT_WTBL_W5_SHORT_GI_80 BIT(10) 4646c92544dSBjoern A. Zeeb #define MT_WTBL_W5_SHORT_GI_160 BIT(11) 4656c92544dSBjoern A. Zeeb #define MT_WTBL_W5_BW_CAP GENMASK(13, 12) 4666c92544dSBjoern A. Zeeb #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23) 4676c92544dSBjoern A. Zeeb #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26) 4686c92544dSBjoern A. Zeeb #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29) 4696c92544dSBjoern A. Zeeb 4706c92544dSBjoern A. Zeeb #define MT_WTBL_W27_CC_BW_SEL GENMASK(6, 5) 4716c92544dSBjoern A. Zeeb 4726c92544dSBjoern A. Zeeb #define MT_LPON(_n) ((dev)->reg_map[MT_LPON_BASE] + (_n)) 4736c92544dSBjoern A. Zeeb 4746c92544dSBjoern A. Zeeb #define MT_LPON_TCR0(_n) MT_LPON(0x010 + ((_n) * 4)) 4756c92544dSBjoern A. Zeeb #define MT_LPON_TCR2(_n) MT_LPON(0x0f8 + ((_n) - 2) * 4) 4766c92544dSBjoern A. Zeeb #define MT_LPON_TCR_MODE GENMASK(1, 0) 4776c92544dSBjoern A. Zeeb #define MT_LPON_TCR_READ GENMASK(1, 0) 4786c92544dSBjoern A. Zeeb #define MT_LPON_TCR_WRITE BIT(0) 4796c92544dSBjoern A. Zeeb #define MT_LPON_TCR_ADJUST BIT(1) 4806c92544dSBjoern A. Zeeb 4816c92544dSBjoern A. Zeeb #define MT_LPON_UTTR0 MT_LPON(0x018) 4826c92544dSBjoern A. Zeeb #define MT_LPON_UTTR1 MT_LPON(0x01c) 4836c92544dSBjoern A. Zeeb 4846c92544dSBjoern A. Zeeb #define MT_WF_MIB_BASE (dev->reg_map[MT_MIB_BASE]) 4856c92544dSBjoern A. Zeeb #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE + (ofs) + (_band) * 0x200) 4866c92544dSBjoern A. Zeeb 4876c92544dSBjoern A. Zeeb #define MT_WF_MIB_SCR0 MT_WF_MIB(0, 0) 4886c92544dSBjoern A. Zeeb #define MT_MIB_SCR0_AGG_CNT_RANGE_EN BIT(21) 4896c92544dSBjoern A. Zeeb 4906c92544dSBjoern A. Zeeb #define MT_MIB_M0_MISC_CR(_band) MT_WF_MIB(_band, 0x00c) 4916c92544dSBjoern A. Zeeb 4926c92544dSBjoern A. Zeeb #define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x014) 4936c92544dSBjoern A. Zeeb #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0) 4946c92544dSBjoern A. Zeeb 4956c92544dSBjoern A. Zeeb #define MT_MIB_SDR9(_band) MT_WF_MIB(_band, 0x02c) 4966c92544dSBjoern A. Zeeb #define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0) 4976c92544dSBjoern A. Zeeb 4986c92544dSBjoern A. Zeeb #define MT_MIB_SDR14(_band) MT_WF_MIB(_band, 0x040) 4996c92544dSBjoern A. Zeeb #define MT_MIB_AMPDU_MPDU_COUNT GENMASK(23, 0) 5006c92544dSBjoern A. Zeeb 5016c92544dSBjoern A. Zeeb #define MT_MIB_SDR15(_band) MT_WF_MIB(_band, 0x044) 5026c92544dSBjoern A. Zeeb #define MT_MIB_AMPDU_ACK_COUNT GENMASK(23, 0) 5036c92544dSBjoern A. Zeeb 5046c92544dSBjoern A. Zeeb #define MT_MIB_SDR16(_band) MT_WF_MIB(_band, 0x048) 5056c92544dSBjoern A. Zeeb #define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0) 5066c92544dSBjoern A. Zeeb 5076c92544dSBjoern A. Zeeb #define MT_MIB_SDR36(_band) MT_WF_MIB(_band, 0x098) 5086c92544dSBjoern A. Zeeb #define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0) 5096c92544dSBjoern A. Zeeb #define MT_MIB_SDR37(_band) MT_WF_MIB(_band, 0x09c) 5106c92544dSBjoern A. Zeeb #define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0) 5116c92544dSBjoern A. Zeeb 5126c92544dSBjoern A. Zeeb #define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, 0x100 + ((n) << 4)) 5136c92544dSBjoern A. Zeeb #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16) 5146c92544dSBjoern A. Zeeb #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0) 5156c92544dSBjoern A. Zeeb 5166c92544dSBjoern A. Zeeb #define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, 0x104 + ((n) << 4)) 5176c92544dSBjoern A. Zeeb #define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0) 5186c92544dSBjoern A. Zeeb #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16) 5196c92544dSBjoern A. Zeeb 5206c92544dSBjoern A. Zeeb #define MT_MIB_ARNG(n) MT_WF_MIB(0, 0x4b8 + ((n) << 2)) 5216c92544dSBjoern A. Zeeb 5226c92544dSBjoern A. Zeeb #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0xa8 + ((n) << 2)) 5236c92544dSBjoern A. Zeeb 5246c92544dSBjoern A. Zeeb #define MT_DMA_SHDL(ofs) (dev->reg_map[MT_DMA_SHDL_BASE] + (ofs)) 5256c92544dSBjoern A. Zeeb 5266c92544dSBjoern A. Zeeb #define MT_DMASHDL_BASE 0x5000a000 5276c92544dSBjoern A. Zeeb #define MT_DMASHDL_OPTIONAL 0x008 5286c92544dSBjoern A. Zeeb #define MT_DMASHDL_PAGE 0x00c 5296c92544dSBjoern A. Zeeb 5306c92544dSBjoern A. Zeeb #define MT_DMASHDL_REFILL 0x010 5316c92544dSBjoern A. Zeeb 5326c92544dSBjoern A. Zeeb #define MT_DMASHDL_PKT_MAX_SIZE 0x01c 5336c92544dSBjoern A. Zeeb #define MT_DMASHDL_PKT_MAX_SIZE_PLE GENMASK(11, 0) 5346c92544dSBjoern A. Zeeb #define MT_DMASHDL_PKT_MAX_SIZE_PSE GENMASK(27, 16) 5356c92544dSBjoern A. Zeeb 5366c92544dSBjoern A. Zeeb #define MT_DMASHDL_GROUP_QUOTA(_n) (0x020 + ((_n) << 2)) 5376c92544dSBjoern A. Zeeb #define MT_DMASHDL_GROUP_QUOTA_MIN GENMASK(11, 0) 5386c92544dSBjoern A. Zeeb #define MT_DMASHDL_GROUP_QUOTA_MAX GENMASK(27, 16) 5396c92544dSBjoern A. Zeeb 5406c92544dSBjoern A. Zeeb #define MT_DMASHDL_SCHED_SET0 0x0b0 5416c92544dSBjoern A. Zeeb #define MT_DMASHDL_SCHED_SET1 0x0b4 5426c92544dSBjoern A. Zeeb 5436c92544dSBjoern A. Zeeb #define MT_DMASHDL_Q_MAP(_n) (0x0d0 + ((_n) << 2)) 5446c92544dSBjoern A. Zeeb #define MT_DMASHDL_Q_MAP_MASK GENMASK(3, 0) 5456c92544dSBjoern A. Zeeb #define MT_DMASHDL_Q_MAP_SHIFT(_n) (4 * ((_n) % 8)) 5466c92544dSBjoern A. Zeeb 5476c92544dSBjoern A. Zeeb #define MT_LED_BASE_PHYS 0x80024000 5486c92544dSBjoern A. Zeeb #define MT_LED_PHYS(_n) (MT_LED_BASE_PHYS + (_n)) 5496c92544dSBjoern A. Zeeb 5506c92544dSBjoern A. Zeeb #define MT_LED_CTRL MT_LED_PHYS(0x00) 5516c92544dSBjoern A. Zeeb 5526c92544dSBjoern A. Zeeb #define MT_LED_CTRL_REPLAY(_n) BIT(0 + (8 * (_n))) 5536c92544dSBjoern A. Zeeb #define MT_LED_CTRL_POLARITY(_n) BIT(1 + (8 * (_n))) 5546c92544dSBjoern A. Zeeb #define MT_LED_CTRL_TX_BLINK_MODE(_n) BIT(2 + (8 * (_n))) 5556c92544dSBjoern A. Zeeb #define MT_LED_CTRL_TX_MANUAL_BLINK(_n) BIT(3 + (8 * (_n))) 556*cbb3ec25SBjoern A. Zeeb #define MT_LED_CTRL_BAND(_n) BIT(4 + (8 * (_n))) 5576c92544dSBjoern A. Zeeb #define MT_LED_CTRL_TX_OVER_BLINK(_n) BIT(5 + (8 * (_n))) 5586c92544dSBjoern A. Zeeb #define MT_LED_CTRL_KICK(_n) BIT(7 + (8 * (_n))) 5596c92544dSBjoern A. Zeeb 5606c92544dSBjoern A. Zeeb #define MT_LED_STATUS_0(_n) MT_LED_PHYS(0x10 + ((_n) * 8)) 5616c92544dSBjoern A. Zeeb #define MT_LED_STATUS_1(_n) MT_LED_PHYS(0x14 + ((_n) * 8)) 5626c92544dSBjoern A. Zeeb #define MT_LED_STATUS_OFF GENMASK(31, 24) 5636c92544dSBjoern A. Zeeb #define MT_LED_STATUS_ON GENMASK(23, 16) 5646c92544dSBjoern A. Zeeb #define MT_LED_STATUS_DURATION GENMASK(15, 0) 5656c92544dSBjoern A. Zeeb 5666c92544dSBjoern A. Zeeb #define MT_PDMA_BUSY 0x82000504 5676c92544dSBjoern A. Zeeb #define MT_PDMA_TX_BUSY BIT(0) 5686c92544dSBjoern A. Zeeb #define MT_PDMA_RX_BUSY BIT(1) 5696c92544dSBjoern A. Zeeb 5706c92544dSBjoern A. Zeeb #define MT_EFUSE_BASE ((dev)->reg_map[MT_EFUSE_ADDR_BASE]) 5716c92544dSBjoern A. Zeeb #define MT_EFUSE_BASE_CTRL 0x000 5726c92544dSBjoern A. Zeeb #define MT_EFUSE_BASE_CTRL_EMPTY BIT(30) 5736c92544dSBjoern A. Zeeb 5746c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL 0x008 5756c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0) 5766c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL_MODE GENMASK(7, 6) 5776c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8) 5786c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14) 5796c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL_AIN GENMASK(25, 16) 5806c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL_VALID BIT(29) 5816c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL_KICK BIT(30) 5826c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL_SEL BIT(31) 5836c92544dSBjoern A. Zeeb 5846c92544dSBjoern A. Zeeb #define MT_EFUSE_WDATA(_i) (0x010 + ((_i) * 4)) 5856c92544dSBjoern A. Zeeb #define MT_EFUSE_RDATA(_i) (0x030 + ((_i) * 4)) 5866c92544dSBjoern A. Zeeb 5876c92544dSBjoern A. Zeeb /* INFRACFG host register range on MT7622 */ 5886c92544dSBjoern A. Zeeb #define MT_INFRACFG_MISC 0x700 5896c92544dSBjoern A. Zeeb #define MT_INFRACFG_MISC_AP2CONN_WAKE BIT(1) 5906c92544dSBjoern A. Zeeb 5916c92544dSBjoern A. Zeeb #define MT_UMAC_BASE 0x7c000000 5926c92544dSBjoern A. Zeeb #define MT_UMAC(ofs) (MT_UMAC_BASE + (ofs)) 5936c92544dSBjoern A. Zeeb #define MT_UDMA_TX_QSEL MT_UMAC(0x008) 5946c92544dSBjoern A. Zeeb #define MT_FW_DL_EN BIT(3) 5956c92544dSBjoern A. Zeeb 5966c92544dSBjoern A. Zeeb #define MT_UDMA_WLCFG_1 MT_UMAC(0x00c) 5976c92544dSBjoern A. Zeeb #define MT_WL_RX_AGG_PKT_LMT GENMASK(7, 0) 5986c92544dSBjoern A. Zeeb #define MT_WL_TX_TMOUT_LMT GENMASK(27, 8) 5996c92544dSBjoern A. Zeeb 6006c92544dSBjoern A. Zeeb #define MT_UDMA_WLCFG_0 MT_UMAC(0x18) 6016c92544dSBjoern A. Zeeb #define MT_WL_RX_AGG_TO GENMASK(7, 0) 6026c92544dSBjoern A. Zeeb #define MT_WL_RX_AGG_LMT GENMASK(15, 8) 6036c92544dSBjoern A. Zeeb #define MT_WL_TX_TMOUT_FUNC_EN BIT(16) 6046c92544dSBjoern A. Zeeb #define MT_WL_TX_DPH_CHK_EN BIT(17) 6056c92544dSBjoern A. Zeeb #define MT_WL_RX_MPSZ_PAD0 BIT(18) 6066c92544dSBjoern A. Zeeb #define MT_WL_RX_FLUSH BIT(19) 6076c92544dSBjoern A. Zeeb #define MT_TICK_1US_EN BIT(20) 6086c92544dSBjoern A. Zeeb #define MT_WL_RX_AGG_EN BIT(21) 6096c92544dSBjoern A. Zeeb #define MT_WL_RX_EN BIT(22) 6106c92544dSBjoern A. Zeeb #define MT_WL_TX_EN BIT(23) 6116c92544dSBjoern A. Zeeb #define MT_WL_RX_BUSY BIT(30) 6126c92544dSBjoern A. Zeeb #define MT_WL_TX_BUSY BIT(31) 6136c92544dSBjoern A. Zeeb 6146c92544dSBjoern A. Zeeb #define MT_MCU_PTA_BASE 0x81060000 6156c92544dSBjoern A. Zeeb #define MT_MCU_PTA(_n) (MT_MCU_PTA_BASE + (_n)) 6166c92544dSBjoern A. Zeeb 6176c92544dSBjoern A. Zeeb #define MT_ANT_SWITCH_CON(_n) MT_MCU_PTA(0x0c8 + ((_n) - 1) * 4) 6186c92544dSBjoern A. Zeeb #define MT_ANT_SWITCH_CON_MODE(_n) (GENMASK(4, 0) << (_n * 8)) 6196c92544dSBjoern A. Zeeb #define MT_ANT_SWITCH_CON_MODE1(_n) (GENMASK(3, 0) << (_n * 8)) 6206c92544dSBjoern A. Zeeb 6216c92544dSBjoern A. Zeeb #endif 622