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/linux/Documentation/devicetree/bindings/pci/
H A Dst,spear1340-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/st,spear1340-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST SPEAr1340 PCIe controller
10 - Pratyush Anand <pratyush.anand@gmail.com>
13 SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
20 const: st,spear1340-pcie
22 - compatible
27 - const: st,spear1340-pcie
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8 SoC series PCIe PHY
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
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H A Dapm,xgene-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/apm,xgene-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: APM X-Gene 15Gbps Multi-purpose PHY
10 - Khuong Dinh <khuong@os.amperecomputing.com>
13 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
19 - const: apm,xgene-phy
24 '#phy-cells':
26 Possible values are 0 (SATA), 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
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/linux/drivers/infiniband/hw/hfi1/
H A Dpcie.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015 - 2019 Intel Corporation.
18 * This file contains PCIe utility routines.
22 * Do all the common PCIe setup and initialization.
27 struct pci_dev *pdev = dd->pcidev; in hfi1_pcie_init()
43 dd_dev_err(dd, "pci enable failed: error %d\n", -ret); in hfi1_pcie_init()
49 dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret); in hfi1_pcie_init()
53 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in hfi1_pcie_init()
60 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in hfi1_pcie_init()
89 * Do remaining PCIe setup, once dd is allocated, and save away
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/linux/arch/mips/include/asm/octeon/
H A Dpci-octeon.h2 * This file is subject to the terms and conditions of the GNU General Public
6 * Copyright (C) 2005-2009 Cavium Networks
18 #define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28))
22 * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
23 * place BAR1 so it is the same for both.
28 * pcibios_map_irq() is defined inside pci-octeon.c. All it does is
30 * function needs to change for PCI or PCIe based hosts.
36 * For PCI (not PCIe) the BAR2 base address.
41 * For PCI (not PCIe) the base of the memory mapped by BAR1
61 * This tells the DMA mapping system in dma-octeon.c how to map PCI
/linux/drivers/pci/controller/
H A Dpcie-rockchip-host.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe host controller driver
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
29 #include "pcie-rockchip.h"
68 if (pci_is_root_bus(bus) || pci_is_root_bus(bus->parent)) in rockchip_pcie_valid_device()
79 if (rockchip->legacy_phy) in rockchip_pcie_lane_map()
80 return GENMASK(MAX_LANE_NUM - 1, 0); in rockchip_pcie_lane_map()
85 /* The link may be using a reverse-indexed mapping. */ in rockchip_pcie_lane_map()
97 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where; in rockchip_pcie_rd_own_conf()
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
11 tristate "Aardvark PCIe controller"
18 Add support for Aardvark 64bit PCIe Host Controller. This
19 controller is part of the South Bridge of the Marvel Armada
23 tristate "Altera PCIe controller"
26 Say Y here if you want to enable PCIe controller support on Altera
30 tristate "Altera PCIe MSI feature"
35 Say Y here if you want PCIe MSI support for the Altera FPGA.
44 tristate "Apple PCIe controller"
51 Say Y here if you want to enable PCIe controller support on Apple
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H A Dpcie-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek PCIe host controller driver.
15 #include <linux/irqchip/irq-msi-lib.h>
33 /* PCIe shared registers */
39 /* PCIe per port registers */
70 /* PCIe V2 share registers */
75 /* PCIe V2 per-port registers */
98 * Define PCIe to AHB window size as 2^33 to support max 8GB address space
104 /* PCIe V2 configuration transaction header */
128 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
[all …]
H A Dpcie-rockchip-ep.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe endpoint controller driver
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
18 #include <linux/pci-epc.h>
20 #include <linux/pci-epf.h>
24 #include "pcie-rockchip.h"
27 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
28 * @rockchip: Rockchip PCIe controller
34 * dedicated outbound regions is mapped.
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/linux/drivers/pci/controller/dwc/
H A Dpcie-spear13xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
5 * SPEAr13xx PCIe Glue Layer Source Code
7 * Copyright (C) 2010-2014 ST Microelectronics
22 #include "pcie-designware.h"
67 #define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev)
72 struct pcie_app_reg __iomem *app_reg = spear13xx_pcie->app_base; in spear13xx_pcie_start_link()
78 &app_reg->app_ctrl_0); in spear13xx_pcie_start_link()
86 struct pcie_app_reg __iomem *app_reg = spear13xx_pcie->app_base; in spear13xx_pcie_irq_handler()
87 struct dw_pcie *pci = spear13xx_pcie->pci; in spear13xx_pcie_irq_handler()
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H A Dpci-imx6.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Freescale i.MX6 SoCs
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
31 #include <linux/phy/pcie.h>
37 #include "pcie-designware.h"
82 #define to_imx_pcie(x) dev_get_drvdata((x)->dev)
111 * Because of ERR005723 (PCIe does not support L2 power down) we need to
118 #define imx_check_flag(pci, val) (pci->drvdata->flags & val)
135 int (*init_phy)(struct imx_pcie *pcie);
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H A Dpcie-dw-rockchip.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Rockchip SoCs.
6 * http://www.rock-chips.com
8 * Author: Simon Xue <xxm@rock-chips.com>
26 #include "pcie-designware.h"
36 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
91 return readl_relaxed(rockchip->apb_base + reg); in rockchip_pcie_readl_apb()
97 writel_relaxed(val, rockchip->apb_base + reg); in rockchip_pcie_writel_apb()
111 generic_handle_domain_irq(rockchip->irq_domain, hwirq); in rockchip_pcie_intx_handler()
119 HIWORD_UPDATE_BIT(BIT(data->hwirq)), in rockchip_intx_mask()
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8m-pcie.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
79 pad_mode = imx8_phy->refclk_pad_mode; in imx8_pcie_phy_power_on()
80 switch (imx8_phy->drvdata->variant) { in imx8_pcie_phy_power_on()
82 reset_control_assert(imx8_phy->reset); in imx8_pcie_phy_power_on()
84 /* Tune PHY de-emphasis setting to pass PCIe compliance. */ in imx8_pcie_phy_power_on()
85 if (imx8_phy->tx_deemph_gen1) in imx8_pcie_phy_power_on()
86 writel(imx8_phy->tx_deemph_gen1, in imx8_pcie_phy_power_on()
87 imx8_phy->base + PCIE_PHY_TRSV_REG5); in imx8_pcie_phy_power_on()
[all …]
/linux/arch/mips/pci/
H A Dpcie-octeon.c2 * This file is subject to the terms and conditions of the GNU General Public
17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-pciercx-defs.h>
19 #include <asm/octeon/cvmx-pescx-defs.h>
20 #include <asm/octeon/cvmx-pexp-defs.h>
21 #include <asm/octeon/cvmx-pemx-defs.h>
22 #include <asm/octeon/cvmx-dpi-defs.h>
23 #include <asm/octeon/cvmx-sli-defs.h>
24 #include <asm/octeon/cvmx-sriox-defs.h>
25 #include <asm/octeon/cvmx-helper-errata.h>
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dsmu7.h4 * Permission is hereby granted, free of charge, to any person obtaining a
9 * Software is furnished to do so, subject to the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
44 #define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes.
99 // ------------------------------------------------------------------------------------------------…
100 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
/linux/drivers/phy/mediatek/
H A Dphy-mtk-tphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
15 #include <linux/nvmem-consumer.h>
22 #include "phy-mtk-io.h"
24 /* version V1 sub-banks offset base address */
31 /* u3/pcie/sata phy banks */
35 /* version V2/V3 sub-banks offset base address */
36 /* V3: U2FREQ is not used anymore, but reserved */
41 /* u3/pcie/sata phy banks */
218 /* CDR Charge Pump P-path current adjustment */
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/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu7.h4 * Permission is hereby granted, free of charge, to any person obtaining a
9 * Software is furnished to do so, subject to the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
44 #define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes.
86 /* VR Config info is contained in dpmTable */
118 // ------------------------------------------------------------------------------------------------…
119 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
H A Dsmu71_discrete.h4 * Permission is hereby granted, free of charge, to any person obtaining a
9 * Software is furnished to do so, subject to the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
153 uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
241 // Multi-DPM controller settings
346 // --------------------------------------------------- AC Timing Parameters -----------------------…
376 // --------------------------------------------------- Fan Table ----------------------------------…
508 // dw0-dw1
511 // dw2-dw3
514 // dw4-dw5
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H A Dsmu73_discrete.h4 * Permission is hereby granted, free of charge, to any person obtaining a
9 * Software is furnished to do so, subject to the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
125 uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
201 // Multi-DPM controller settings
360 // --------------------------------------------------- Fan Table ----------------------------------…
577 /* dw0-dw1 */
580 /* dw2-dw3 */
583 /* dw4-dw5 */
603 /* dw4-dw7 */
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H A Dsmu9_driver_if.h4 * Permission is hereby granted, free of charge, to any person obtaining a
9 * Software is furnished to do so, subject to the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
31 * any structure is changed in this file
46 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
47 #define MAX_UVD_DPM_LEVEL (NUM_UVD_DPM_LEVELS - 1)
48 #define MAX_VCE_DPM_LEVEL (NUM_VCE_DPM_LEVELS - 1)
49 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
50 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
51 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
[all …]
H A Dsmu72_discrete.h4 * Permission is hereby granted, free of charge, to any person obtaining a
9 * Software is furnished to do so, subject to the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
144 uint8_t PcieGenSpeed; /*< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
217 /* Multi-DPM controller settings */
352 /* --------------------------------------------------- AC Timing Parameters -----------------------…
379 /* --------------------------------------------------- Fan Table ----------------------------------…
601 /* dw4-dw7 */
604 /* dw8-dw9 */
610 /* dw10-dw14 */
H A Dsmu72.h4 * Permission is hereby granted, free of charge, to any person obtaining a
9 * Software is furnished to do so, subject to the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
112 #define SMU72_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lane…
345 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
369 /* -------------------------------------------------------- CAC table -----------------------------…
627 /* VR Config info is contained in dpmTable.VRConfig */
650 /* The 'settings' field is subdivided in the following way: */
/linux/drivers/irqchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
131 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support"
140 Enable support for the Broadcom BCM2712 MSI-X target peripheral
141 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on
153 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
161 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
216 This controller is present on the Microchip LAN966x PCI device and
217 maps the internal interrupts sources to PCIe interrupt.
220 will be called irq-lan966x-oic.
261 bool "J-Core integrated AIC" if COMPILE_TEST
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/linux/drivers/phy/st/
H A Dphy-miphy28lp.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <dt-bindings/phy/phy.h>
171 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
173 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
174 * Some devices have not the possibility to check if the osc is ready.
183 /* SATA / PCIe defines */
233 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
362 void __iomem *base = miphy_phy->base; in miphy28lp_set_reset()
373 /* Bringing the MIPHY-CPU registers out of reset */ in miphy28lp_set_reset()
374 if (miphy_phy->type == PHY_TYPE_PCIE) { in miphy28lp_set_reset()
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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_sienna_cichlid.h4 * Permission is hereby granted, free of charge, to any person obtaining a
9 * Software is furnished to do so, subject to the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
29 // any structure is changed in this file
53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
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