1837d542aSEvan Quan /* 2837d542aSEvan Quan * Copyright 2013 Advanced Micro Devices, Inc. 3837d542aSEvan Quan * 4837d542aSEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5837d542aSEvan Quan * copy of this software and associated documentation files (the "Software"), 6837d542aSEvan Quan * to deal in the Software without restriction, including without limitation 7837d542aSEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8837d542aSEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9837d542aSEvan Quan * Software is furnished to do so, subject to the following conditions: 10837d542aSEvan Quan * 11837d542aSEvan Quan * The above copyright notice and this permission notice shall be included in 12837d542aSEvan Quan * all copies or substantial portions of the Software. 13837d542aSEvan Quan * 14837d542aSEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15837d542aSEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16837d542aSEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17837d542aSEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18837d542aSEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19837d542aSEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20837d542aSEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21837d542aSEvan Quan * 22837d542aSEvan Quan */ 23837d542aSEvan Quan 24837d542aSEvan Quan #ifndef SMU7_H 25837d542aSEvan Quan #define SMU7_H 26837d542aSEvan Quan 27837d542aSEvan Quan #pragma pack(push, 1) 28837d542aSEvan Quan 29837d542aSEvan Quan #define SMU7_CONTEXT_ID_SMC 1 30837d542aSEvan Quan #define SMU7_CONTEXT_ID_VBIOS 2 31837d542aSEvan Quan 32837d542aSEvan Quan 33837d542aSEvan Quan #define SMU7_CONTEXT_ID_SMC 1 34837d542aSEvan Quan #define SMU7_CONTEXT_ID_VBIOS 2 35837d542aSEvan Quan 36837d542aSEvan Quan #define SMU7_MAX_LEVELS_VDDC 8 37837d542aSEvan Quan #define SMU7_MAX_LEVELS_VDDCI 4 38837d542aSEvan Quan #define SMU7_MAX_LEVELS_MVDD 4 39837d542aSEvan Quan #define SMU7_MAX_LEVELS_VDDNB 8 40837d542aSEvan Quan 41837d542aSEvan Quan #define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV 42837d542aSEvan Quan #define SMU7_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM 43837d542aSEvan Quan #define SMU7_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels 44837d542aSEvan Quan #define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes. 45837d542aSEvan Quan #define SMU7_MAX_LEVELS_UVD 8 // VCLK/DCLK levels for UVD. 46837d542aSEvan Quan #define SMU7_MAX_LEVELS_VCE 8 // ECLK levels for VCE. 47837d542aSEvan Quan #define SMU7_MAX_LEVELS_ACP 8 // ACLK levels for ACP. 48837d542aSEvan Quan #define SMU7_MAX_LEVELS_SAMU 8 // SAMCLK levels for SAMU. 49837d542aSEvan Quan #define SMU7_MAX_ENTRIES_SMIO 32 // Number of entries in SMIO table. 50837d542aSEvan Quan 51837d542aSEvan Quan #define DPM_NO_LIMIT 0 52837d542aSEvan Quan #define DPM_NO_UP 1 53837d542aSEvan Quan #define DPM_GO_DOWN 2 54837d542aSEvan Quan #define DPM_GO_UP 3 55837d542aSEvan Quan 56837d542aSEvan Quan #define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 57837d542aSEvan Quan #define SMU7_FIRST_DPM_MEMORY_LEVEL 0 58837d542aSEvan Quan 59837d542aSEvan Quan #define GPIO_CLAMP_MODE_VRHOT 1 60837d542aSEvan Quan #define GPIO_CLAMP_MODE_THERM 2 61837d542aSEvan Quan #define GPIO_CLAMP_MODE_DC 4 62837d542aSEvan Quan 63837d542aSEvan Quan #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 64837d542aSEvan Quan #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) 65837d542aSEvan Quan #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 66837d542aSEvan Quan #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) 67837d542aSEvan Quan #define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 68837d542aSEvan Quan #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) 69837d542aSEvan Quan #define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 70837d542aSEvan Quan #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) 71837d542aSEvan Quan #define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 72837d542aSEvan Quan #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) 73837d542aSEvan Quan #define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 74837d542aSEvan Quan #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) 75837d542aSEvan Quan #define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 76837d542aSEvan Quan #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) 77837d542aSEvan Quan #define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 78837d542aSEvan Quan #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) 79837d542aSEvan Quan #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 80837d542aSEvan Quan #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) 81837d542aSEvan Quan #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 82837d542aSEvan Quan #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) 83837d542aSEvan Quan 84837d542aSEvan Quan 85837d542aSEvan Quan /* Voltage Regulator Configuration */ 86837d542aSEvan Quan /* VR Config info is contained in dpmTable */ 87837d542aSEvan Quan 88837d542aSEvan Quan #define VRCONF_VDDC_MASK 0x000000FF 89837d542aSEvan Quan #define VRCONF_VDDC_SHIFT 0 90837d542aSEvan Quan #define VRCONF_VDDGFX_MASK 0x0000FF00 91837d542aSEvan Quan #define VRCONF_VDDGFX_SHIFT 8 92837d542aSEvan Quan #define VRCONF_VDDCI_MASK 0x00FF0000 93837d542aSEvan Quan #define VRCONF_VDDCI_SHIFT 16 94837d542aSEvan Quan #define VRCONF_MVDD_MASK 0xFF000000 95837d542aSEvan Quan #define VRCONF_MVDD_SHIFT 24 96837d542aSEvan Quan 97837d542aSEvan Quan #define VR_MERGED_WITH_VDDC 0 98837d542aSEvan Quan #define VR_SVI2_PLANE_1 1 99837d542aSEvan Quan #define VR_SVI2_PLANE_2 2 100837d542aSEvan Quan #define VR_SMIO_PATTERN_1 3 101837d542aSEvan Quan #define VR_SMIO_PATTERN_2 4 102837d542aSEvan Quan #define VR_STATIC_VOLTAGE 5 103837d542aSEvan Quan 104*e761d50dSRan Sun struct SMU7_PIDController { 105837d542aSEvan Quan uint32_t Ki; 106837d542aSEvan Quan int32_t LFWindupUL; 107837d542aSEvan Quan int32_t LFWindupLL; 108837d542aSEvan Quan uint32_t StatePrecision; 109837d542aSEvan Quan uint32_t LfPrecision; 110837d542aSEvan Quan uint32_t LfOffset; 111837d542aSEvan Quan uint32_t MaxState; 112837d542aSEvan Quan uint32_t MaxLfFraction; 113837d542aSEvan Quan uint32_t StateShift; 114837d542aSEvan Quan }; 115837d542aSEvan Quan 116837d542aSEvan Quan typedef struct SMU7_PIDController SMU7_PIDController; 117837d542aSEvan Quan 118837d542aSEvan Quan // ------------------------------------------------------------------------------------------------------------------------- 119837d542aSEvan Quan #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ 120837d542aSEvan Quan 121837d542aSEvan Quan #define SMU7_SCLK_DPM_CONFIG_MASK 0x01 122837d542aSEvan Quan #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 123837d542aSEvan Quan #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 124837d542aSEvan Quan #define SMU7_MCLK_DPM_CONFIG_MASK 0x08 125837d542aSEvan Quan #define SMU7_UVD_DPM_CONFIG_MASK 0x10 126837d542aSEvan Quan #define SMU7_VCE_DPM_CONFIG_MASK 0x20 127837d542aSEvan Quan #define SMU7_ACP_DPM_CONFIG_MASK 0x40 128837d542aSEvan Quan #define SMU7_SAMU_DPM_CONFIG_MASK 0x80 129837d542aSEvan Quan #define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 130837d542aSEvan Quan 131837d542aSEvan Quan #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 132837d542aSEvan Quan #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 133837d542aSEvan Quan #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 134837d542aSEvan Quan #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 135837d542aSEvan Quan #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 136837d542aSEvan Quan #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 137837d542aSEvan Quan 138*e761d50dSRan Sun struct SMU7_Firmware_Header { 139837d542aSEvan Quan uint32_t Digest[5]; 140837d542aSEvan Quan uint32_t Version; 141837d542aSEvan Quan uint32_t HeaderSize; 142837d542aSEvan Quan uint32_t Flags; 143837d542aSEvan Quan uint32_t EntryPoint; 144837d542aSEvan Quan uint32_t CodeSize; 145837d542aSEvan Quan uint32_t ImageSize; 146837d542aSEvan Quan 147837d542aSEvan Quan uint32_t Rtos; 148837d542aSEvan Quan uint32_t SoftRegisters; 149837d542aSEvan Quan uint32_t DpmTable; 150837d542aSEvan Quan uint32_t FanTable; 151837d542aSEvan Quan uint32_t CacConfigTable; 152837d542aSEvan Quan uint32_t CacStatusTable; 153837d542aSEvan Quan 154837d542aSEvan Quan uint32_t mcRegisterTable; 155837d542aSEvan Quan 156837d542aSEvan Quan uint32_t mcArbDramTimingTable; 157837d542aSEvan Quan 158837d542aSEvan Quan uint32_t PmFuseTable; 159837d542aSEvan Quan uint32_t Globals; 160837d542aSEvan Quan uint32_t Reserved[42]; 161837d542aSEvan Quan uint32_t Signature; 162837d542aSEvan Quan }; 163837d542aSEvan Quan 164837d542aSEvan Quan typedef struct SMU7_Firmware_Header SMU7_Firmware_Header; 165837d542aSEvan Quan 166837d542aSEvan Quan #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000 167837d542aSEvan Quan 168837d542aSEvan Quan enum DisplayConfig { 169837d542aSEvan Quan PowerDown = 1, 170837d542aSEvan Quan DP54x4, 171837d542aSEvan Quan DP54x2, 172837d542aSEvan Quan DP54x1, 173837d542aSEvan Quan DP27x4, 174837d542aSEvan Quan DP27x2, 175837d542aSEvan Quan DP27x1, 176837d542aSEvan Quan HDMI297, 177837d542aSEvan Quan HDMI162, 178837d542aSEvan Quan LVDS, 179837d542aSEvan Quan DP324x4, 180837d542aSEvan Quan DP324x2, 181837d542aSEvan Quan DP324x1 182837d542aSEvan Quan }; 183837d542aSEvan Quan 184837d542aSEvan Quan #pragma pack(pop) 185837d542aSEvan Quan 186837d542aSEvan Quan #endif 187837d542aSEvan Quan 188