16e0832faSShawn Lin // SPDX-License-Identifier: GPL-2.0 26e0832faSShawn Lin /* 36e0832faSShawn Lin * PCIe host controller driver for Freescale i.MX6 SoCs 46e0832faSShawn Lin * 56e0832faSShawn Lin * Copyright (C) 2013 Kosagi 67ecd4a81SAlexander A. Klimov * https://www.kosagi.com 76e0832faSShawn Lin * 86e0832faSShawn Lin * Author: Sean Cross <xobs@kosagi.com> 96e0832faSShawn Lin */ 106e0832faSShawn Lin 112d8ed461SAndrey Smirnov #include <linux/bitfield.h> 126e0832faSShawn Lin #include <linux/clk.h> 136e0832faSShawn Lin #include <linux/delay.h> 142e81122dSAndy Shevchenko #include <linux/gpio/consumer.h> 156e0832faSShawn Lin #include <linux/kernel.h> 166e0832faSShawn Lin #include <linux/mfd/syscon.h> 176e0832faSShawn Lin #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 186e0832faSShawn Lin #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> 196e0832faSShawn Lin #include <linux/module.h> 20c925cfafSRob Herring #include <linux/of.h> 211df82ec4STrent Piepho #include <linux/of_address.h> 226e0832faSShawn Lin #include <linux/pci.h> 236e0832faSShawn Lin #include <linux/platform_device.h> 246e0832faSShawn Lin #include <linux/regmap.h> 256e0832faSShawn Lin #include <linux/regulator/consumer.h> 266e0832faSShawn Lin #include <linux/resource.h> 276e0832faSShawn Lin #include <linux/signal.h> 286e0832faSShawn Lin #include <linux/types.h> 296e0832faSShawn Lin #include <linux/interrupt.h> 306e0832faSShawn Lin #include <linux/reset.h> 31178e244cSRichard Zhu #include <linux/phy/phy.h> 323f7cceeaSLeonard Crestez #include <linux/pm_domain.h> 333f7cceeaSLeonard Crestez #include <linux/pm_runtime.h> 346e0832faSShawn Lin 356e0832faSShawn Lin #include "pcie-designware.h" 366e0832faSShawn Lin 372d8ed461SAndrey Smirnov #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) 382d8ed461SAndrey Smirnov #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10) 392d8ed461SAndrey Smirnov #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) 40d2ce69caSRichard Zhu #define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12) 412d8ed461SAndrey Smirnov #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) 422d8ed461SAndrey Smirnov #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 432d8ed461SAndrey Smirnov 44f5c04da3SFrank Li #define IMX95_PCIE_PHY_GEN_CTRL 0x0 45f5c04da3SFrank Li #define IMX95_PCIE_REF_USE_PAD BIT(17) 46f5c04da3SFrank Li 47f5c04da3SFrank Li #define IMX95_PCIE_SS_RW_REG_0 0xf0 48f5c04da3SFrank Li #define IMX95_PCIE_REF_CLKEN BIT(23) 49f5c04da3SFrank Li #define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9) 50f5c04da3SFrank Li 51f5c04da3SFrank Li #define IMX95_PE0_GEN_CTRL_1 0x1050 52f5c04da3SFrank Li #define IMX95_PCIE_DEVICE_TYPE GENMASK(3, 0) 53f5c04da3SFrank Li 54f5c04da3SFrank Li #define IMX95_PE0_GEN_CTRL_3 0x1058 55f5c04da3SFrank Li #define IMX95_PCIE_LTSSM_EN BIT(0) 56f5c04da3SFrank Li 576e0832faSShawn Lin #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) 586e0832faSShawn Lin 596e0832faSShawn Lin enum imx6_pcie_variants { 606e0832faSShawn Lin IMX6Q, 616e0832faSShawn Lin IMX6SX, 626e0832faSShawn Lin IMX6QP, 636e0832faSShawn Lin IMX7D, 642d8ed461SAndrey Smirnov IMX8MQ, 65178e244cSRichard Zhu IMX8MM, 663db1e531SRichard Zhu IMX8MP, 67f5c04da3SFrank Li IMX95, 68530ba412SRichard Zhu IMX8MQ_EP, 69fb3217e2SRichard Zhu IMX8MM_EP, 70c435669aSRichard Zhu IMX8MP_EP, 71b7d67c61SFrank Li IMX95_EP, 726e0832faSShawn Lin }; 736e0832faSShawn Lin 742f532d07SAndrey Smirnov #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) 754c458bb3SAndrey Smirnov #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) 7676d6dc26SAndrey Smirnov #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) 774e37c2f4SFrank Li #define IMX6_PCIE_FLAG_HAS_PHYDRV BIT(3) 780c9651c2SFrank Li #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) 790c9651c2SFrank Li #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) 80f5c04da3SFrank Li #define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) 81b7d67c61SFrank Li #define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7) 824e37c2f4SFrank Li 834e37c2f4SFrank Li #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) 842f532d07SAndrey Smirnov 856a401858SFrank Li #define IMX6_PCIE_MAX_CLKS 6 866a401858SFrank Li 87f99b121cSFrank Li #define IMX6_PCIE_MAX_INSTANCES 2 8821ad80b0SFrank Li 8921ad80b0SFrank Li struct imx6_pcie; 9021ad80b0SFrank Li 91e8e4d4e9SAndrey Smirnov struct imx6_pcie_drvdata { 92e8e4d4e9SAndrey Smirnov enum imx6_pcie_variants variant; 9375c2f26dSRichard Zhu enum dw_pcie_device_mode mode; 942f532d07SAndrey Smirnov u32 flags; 95075af61cSStefan Agner int dbi_length; 963db1e531SRichard Zhu const char *gpr; 976a401858SFrank Li const char * const *clk_names; 986a401858SFrank Li const u32 clks_cnt; 99d99aa8d3SFrank Li const u32 ltssm_off; 100d99aa8d3SFrank Li const u32 ltssm_mask; 101f99b121cSFrank Li const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; 102f99b121cSFrank Li const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; 1030044966cSFrank Li const struct pci_epc_features *epc_features; 10421ad80b0SFrank Li int (*init_phy)(struct imx6_pcie *pcie); 1056e0832faSShawn Lin }; 1066e0832faSShawn Lin 1076e0832faSShawn Lin struct imx6_pcie { 1086e0832faSShawn Lin struct dw_pcie *pci; 1092e81122dSAndy Shevchenko struct gpio_desc *reset_gpiod; 110af48f822SRichard Zhu bool link_is_up; 1116a401858SFrank Li struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS]; 1126e0832faSShawn Lin struct regmap *iomuxc_gpr; 1133bbc3c72SRichard Zhu u16 msi_ctrl; 1142d8ed461SAndrey Smirnov u32 controller_id; 1156e0832faSShawn Lin struct reset_control *pciephy_reset; 1166e0832faSShawn Lin struct reset_control *apps_reset; 117f4e833baSLeonard Crestez struct reset_control *turnoff_reset; 1186e0832faSShawn Lin u32 tx_deemph_gen1; 1196e0832faSShawn Lin u32 tx_deemph_gen2_3p5db; 1206e0832faSShawn Lin u32 tx_deemph_gen2_6db; 1216e0832faSShawn Lin u32 tx_swing_full; 1226e0832faSShawn Lin u32 tx_swing_low; 1236e0832faSShawn Lin struct regulator *vpcie; 124d2ce69caSRichard Zhu struct regulator *vph; 1251df82ec4STrent Piepho void __iomem *phy_base; 1263f7cceeaSLeonard Crestez 1273f7cceeaSLeonard Crestez /* power domain for pcie */ 1283f7cceeaSLeonard Crestez struct device *pd_pcie; 1293f7cceeaSLeonard Crestez /* power domain for pcie phy */ 1303f7cceeaSLeonard Crestez struct device *pd_pcie_phy; 131178e244cSRichard Zhu struct phy *phy; 132e8e4d4e9SAndrey Smirnov const struct imx6_pcie_drvdata *drvdata; 1336e0832faSShawn Lin }; 1346e0832faSShawn Lin 1356e0832faSShawn Lin /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ 1366e0832faSShawn Lin #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200 1379e303be2SAndrey Smirnov #define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX) 1386e0832faSShawn Lin 1396e0832faSShawn Lin /* PCIe Port Logic registers (memory-mapped) */ 1406e0832faSShawn Lin #define PL_OFFSET 0x700 1416e0832faSShawn Lin 1426e0832faSShawn Lin #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) 1433ca41332SAndrey Smirnov #define PCIE_PHY_CTRL_DATA(x) FIELD_PREP(GENMASK(15, 0), (x)) 1443ca41332SAndrey Smirnov #define PCIE_PHY_CTRL_CAP_ADR BIT(16) 1453ca41332SAndrey Smirnov #define PCIE_PHY_CTRL_CAP_DAT BIT(17) 1463ca41332SAndrey Smirnov #define PCIE_PHY_CTRL_WR BIT(18) 1473ca41332SAndrey Smirnov #define PCIE_PHY_CTRL_RD BIT(19) 1486e0832faSShawn Lin 1496e0832faSShawn Lin #define PCIE_PHY_STAT (PL_OFFSET + 0x110) 150c2c708bcSAndrey Smirnov #define PCIE_PHY_STAT_ACK BIT(16) 1516e0832faSShawn Lin 1526e0832faSShawn Lin /* PHY registers (not memory-mapped) */ 153f18f42d7SLucas Stach #define PCIE_PHY_ATEOVRD 0x10 154276c76d7SAndrey Smirnov #define PCIE_PHY_ATEOVRD_EN BIT(2) 155f18f42d7SLucas Stach #define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0 156f18f42d7SLucas Stach #define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1 157f18f42d7SLucas Stach 158f18f42d7SLucas Stach #define PCIE_PHY_MPLL_OVRD_IN_LO 0x11 159f18f42d7SLucas Stach #define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2 160f18f42d7SLucas Stach #define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f 161276c76d7SAndrey Smirnov #define PCIE_PHY_MPLL_MULTIPLIER_OVRD BIT(9) 162f18f42d7SLucas Stach 1636e0832faSShawn Lin #define PCIE_PHY_RX_ASIC_OUT 0x100D 1646e0832faSShawn Lin #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0) 1656e0832faSShawn Lin 1661df82ec4STrent Piepho /* iMX7 PCIe PHY registers */ 1671df82ec4STrent Piepho #define PCIE_PHY_CMN_REG4 0x14 1681df82ec4STrent Piepho /* These are probably the bits that *aren't* DCC_FB_EN */ 1691df82ec4STrent Piepho #define PCIE_PHY_CMN_REG4_DCC_FB_EN 0x29 1701df82ec4STrent Piepho 1711df82ec4STrent Piepho #define PCIE_PHY_CMN_REG15 0x54 1721df82ec4STrent Piepho #define PCIE_PHY_CMN_REG15_DLY_4 BIT(2) 1731df82ec4STrent Piepho #define PCIE_PHY_CMN_REG15_PLL_PD BIT(5) 1741df82ec4STrent Piepho #define PCIE_PHY_CMN_REG15_OVRD_PLL_PD BIT(7) 1751df82ec4STrent Piepho 1761df82ec4STrent Piepho #define PCIE_PHY_CMN_REG24 0x90 1771df82ec4STrent Piepho #define PCIE_PHY_CMN_REG24_RX_EQ BIT(6) 1781df82ec4STrent Piepho #define PCIE_PHY_CMN_REG24_RX_EQ_SEL BIT(3) 1791df82ec4STrent Piepho 1801df82ec4STrent Piepho #define PCIE_PHY_CMN_REG26 0x98 1811df82ec4STrent Piepho #define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC 1821df82ec4STrent Piepho 1836e0832faSShawn Lin #define PHY_RX_OVRD_IN_LO 0x1005 184276c76d7SAndrey Smirnov #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) 185276c76d7SAndrey Smirnov #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) 1866e0832faSShawn Lin 18779f14b6fSBjorn Helgaas static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) 18879f14b6fSBjorn Helgaas { 18979f14b6fSBjorn Helgaas WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ && 190530ba412SRichard Zhu imx6_pcie->drvdata->variant != IMX8MQ_EP && 1913db1e531SRichard Zhu imx6_pcie->drvdata->variant != IMX8MM && 192fb3217e2SRichard Zhu imx6_pcie->drvdata->variant != IMX8MM_EP && 193c435669aSRichard Zhu imx6_pcie->drvdata->variant != IMX8MP && 194c435669aSRichard Zhu imx6_pcie->drvdata->variant != IMX8MP_EP); 19579f14b6fSBjorn Helgaas return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; 19679f14b6fSBjorn Helgaas } 19779f14b6fSBjorn Helgaas 198f5c04da3SFrank Li static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie) 199f5c04da3SFrank Li { 200f5c04da3SFrank Li regmap_update_bits(imx6_pcie->iomuxc_gpr, 201f5c04da3SFrank Li IMX95_PCIE_SS_RW_REG_0, 202f5c04da3SFrank Li IMX95_PCIE_PHY_CR_PARA_SEL, 203f5c04da3SFrank Li IMX95_PCIE_PHY_CR_PARA_SEL); 204f5c04da3SFrank Li 205f5c04da3SFrank Li regmap_update_bits(imx6_pcie->iomuxc_gpr, 206f5c04da3SFrank Li IMX95_PCIE_PHY_GEN_CTRL, 207f5c04da3SFrank Li IMX95_PCIE_REF_USE_PAD, 0); 208f5c04da3SFrank Li regmap_update_bits(imx6_pcie->iomuxc_gpr, 209f5c04da3SFrank Li IMX95_PCIE_SS_RW_REG_0, 210f5c04da3SFrank Li IMX95_PCIE_REF_CLKEN, 211f5c04da3SFrank Li IMX95_PCIE_REF_CLKEN); 212f5c04da3SFrank Li 213f5c04da3SFrank Li return 0; 214f5c04da3SFrank Li } 215f5c04da3SFrank Li 21679f14b6fSBjorn Helgaas static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) 21779f14b6fSBjorn Helgaas { 218f99b121cSFrank Li const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; 219f99b121cSFrank Li unsigned int mask, val, mode, id; 22075c2f26dSRichard Zhu 221f99b121cSFrank Li if (drvdata->mode == DW_PCIE_EP_TYPE) 22275c2f26dSRichard Zhu mode = PCI_EXP_TYPE_ENDPOINT; 22375c2f26dSRichard Zhu else 22475c2f26dSRichard Zhu mode = PCI_EXP_TYPE_ROOT_PORT; 22579f14b6fSBjorn Helgaas 226f99b121cSFrank Li id = imx6_pcie->controller_id; 22779f14b6fSBjorn Helgaas 228f99b121cSFrank Li /* If mode_mask[id] is zero, means each controller have its individual gpr */ 229f99b121cSFrank Li if (!drvdata->mode_mask[id]) 230f99b121cSFrank Li id = 0; 231f99b121cSFrank Li 232f99b121cSFrank Li mask = drvdata->mode_mask[id]; 233f99b121cSFrank Li val = mode << (ffs(mask) - 1); 234f99b121cSFrank Li 235f99b121cSFrank Li regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); 23679f14b6fSBjorn Helgaas } 23779f14b6fSBjorn Helgaas 238c2c708bcSAndrey Smirnov static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) 2396e0832faSShawn Lin { 2406e0832faSShawn Lin struct dw_pcie *pci = imx6_pcie->pci; 241c2c708bcSAndrey Smirnov bool val; 2426e0832faSShawn Lin u32 max_iterations = 10; 2436e0832faSShawn Lin u32 wait_counter = 0; 2446e0832faSShawn Lin 2456e0832faSShawn Lin do { 246c2c708bcSAndrey Smirnov val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) & 247c2c708bcSAndrey Smirnov PCIE_PHY_STAT_ACK; 2486e0832faSShawn Lin wait_counter++; 2496e0832faSShawn Lin 2506e0832faSShawn Lin if (val == exp_val) 2516e0832faSShawn Lin return 0; 2526e0832faSShawn Lin 2536e0832faSShawn Lin udelay(1); 2546e0832faSShawn Lin } while (wait_counter < max_iterations); 2556e0832faSShawn Lin 2566e0832faSShawn Lin return -ETIMEDOUT; 2576e0832faSShawn Lin } 2586e0832faSShawn Lin 2596e0832faSShawn Lin static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) 2606e0832faSShawn Lin { 2616e0832faSShawn Lin struct dw_pcie *pci = imx6_pcie->pci; 2626e0832faSShawn Lin u32 val; 2636e0832faSShawn Lin int ret; 2646e0832faSShawn Lin 2653ca41332SAndrey Smirnov val = PCIE_PHY_CTRL_DATA(addr); 2666e0832faSShawn Lin dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 2676e0832faSShawn Lin 2683ca41332SAndrey Smirnov val |= PCIE_PHY_CTRL_CAP_ADR; 2696e0832faSShawn Lin dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 2706e0832faSShawn Lin 271c2c708bcSAndrey Smirnov ret = pcie_phy_poll_ack(imx6_pcie, true); 2726e0832faSShawn Lin if (ret) 2736e0832faSShawn Lin return ret; 2746e0832faSShawn Lin 2753ca41332SAndrey Smirnov val = PCIE_PHY_CTRL_DATA(addr); 2766e0832faSShawn Lin dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 2776e0832faSShawn Lin 278c2c708bcSAndrey Smirnov return pcie_phy_poll_ack(imx6_pcie, false); 2796e0832faSShawn Lin } 2806e0832faSShawn Lin 2816e0832faSShawn Lin /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ 28237d5d32aSAndrey Smirnov static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) 2836e0832faSShawn Lin { 2846e0832faSShawn Lin struct dw_pcie *pci = imx6_pcie->pci; 28537d5d32aSAndrey Smirnov u32 phy_ctl; 2866e0832faSShawn Lin int ret; 2876e0832faSShawn Lin 2886e0832faSShawn Lin ret = pcie_phy_wait_ack(imx6_pcie, addr); 2896e0832faSShawn Lin if (ret) 2906e0832faSShawn Lin return ret; 2916e0832faSShawn Lin 2926e0832faSShawn Lin /* assert Read signal */ 2933ca41332SAndrey Smirnov phy_ctl = PCIE_PHY_CTRL_RD; 2946e0832faSShawn Lin dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); 2956e0832faSShawn Lin 296c2c708bcSAndrey Smirnov ret = pcie_phy_poll_ack(imx6_pcie, true); 2976e0832faSShawn Lin if (ret) 2986e0832faSShawn Lin return ret; 2996e0832faSShawn Lin 30037d5d32aSAndrey Smirnov *data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); 3016e0832faSShawn Lin 3026e0832faSShawn Lin /* deassert Read signal */ 3036e0832faSShawn Lin dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); 3046e0832faSShawn Lin 305c2c708bcSAndrey Smirnov return pcie_phy_poll_ack(imx6_pcie, false); 3066e0832faSShawn Lin } 3076e0832faSShawn Lin 30837d5d32aSAndrey Smirnov static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) 3096e0832faSShawn Lin { 3106e0832faSShawn Lin struct dw_pcie *pci = imx6_pcie->pci; 3116e0832faSShawn Lin u32 var; 3126e0832faSShawn Lin int ret; 3136e0832faSShawn Lin 3146e0832faSShawn Lin /* write addr */ 3156e0832faSShawn Lin /* cap addr */ 3166e0832faSShawn Lin ret = pcie_phy_wait_ack(imx6_pcie, addr); 3176e0832faSShawn Lin if (ret) 3186e0832faSShawn Lin return ret; 3196e0832faSShawn Lin 3203ca41332SAndrey Smirnov var = PCIE_PHY_CTRL_DATA(data); 3216e0832faSShawn Lin dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 3226e0832faSShawn Lin 3236e0832faSShawn Lin /* capture data */ 3243ca41332SAndrey Smirnov var |= PCIE_PHY_CTRL_CAP_DAT; 3256e0832faSShawn Lin dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 3266e0832faSShawn Lin 327c2c708bcSAndrey Smirnov ret = pcie_phy_poll_ack(imx6_pcie, true); 3286e0832faSShawn Lin if (ret) 3296e0832faSShawn Lin return ret; 3306e0832faSShawn Lin 3316e0832faSShawn Lin /* deassert cap data */ 3323ca41332SAndrey Smirnov var = PCIE_PHY_CTRL_DATA(data); 3336e0832faSShawn Lin dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 3346e0832faSShawn Lin 3356e0832faSShawn Lin /* wait for ack de-assertion */ 336c2c708bcSAndrey Smirnov ret = pcie_phy_poll_ack(imx6_pcie, false); 3376e0832faSShawn Lin if (ret) 3386e0832faSShawn Lin return ret; 3396e0832faSShawn Lin 3406e0832faSShawn Lin /* assert wr signal */ 3413ca41332SAndrey Smirnov var = PCIE_PHY_CTRL_WR; 3426e0832faSShawn Lin dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 3436e0832faSShawn Lin 3446e0832faSShawn Lin /* wait for ack */ 345c2c708bcSAndrey Smirnov ret = pcie_phy_poll_ack(imx6_pcie, true); 3466e0832faSShawn Lin if (ret) 3476e0832faSShawn Lin return ret; 3486e0832faSShawn Lin 3496e0832faSShawn Lin /* deassert wr signal */ 3503ca41332SAndrey Smirnov var = PCIE_PHY_CTRL_DATA(data); 3516e0832faSShawn Lin dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 3526e0832faSShawn Lin 3536e0832faSShawn Lin /* wait for ack de-assertion */ 354c2c708bcSAndrey Smirnov ret = pcie_phy_poll_ack(imx6_pcie, false); 3556e0832faSShawn Lin if (ret) 3566e0832faSShawn Lin return ret; 3576e0832faSShawn Lin 3586e0832faSShawn Lin dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0); 3596e0832faSShawn Lin 3606e0832faSShawn Lin return 0; 3616e0832faSShawn Lin } 3626e0832faSShawn Lin 36321ad80b0SFrank Li static int imx8mq_pcie_init_phy(struct imx6_pcie *imx6_pcie) 3646b1e989eSBjorn Helgaas { 36521ad80b0SFrank Li /* TODO: Currently this code assumes external oscillator is being used */ 3666b1e989eSBjorn Helgaas regmap_update_bits(imx6_pcie->iomuxc_gpr, 3676b1e989eSBjorn Helgaas imx6_pcie_grp_offset(imx6_pcie), 3686b1e989eSBjorn Helgaas IMX8MQ_GPR_PCIE_REF_USE_PAD, 3696b1e989eSBjorn Helgaas IMX8MQ_GPR_PCIE_REF_USE_PAD); 3706b1e989eSBjorn Helgaas /* 37121ad80b0SFrank Li * Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is 37221ad80b0SFrank Li * supplied by 3.3V, the VREG_BYPASS should be cleared to zero. 3736b1e989eSBjorn Helgaas */ 37421ad80b0SFrank Li if (imx6_pcie->vph && regulator_get_voltage(imx6_pcie->vph) > 3000000) 3756b1e989eSBjorn Helgaas regmap_update_bits(imx6_pcie->iomuxc_gpr, 3766b1e989eSBjorn Helgaas imx6_pcie_grp_offset(imx6_pcie), 3776b1e989eSBjorn Helgaas IMX8MQ_GPR_PCIE_VREG_BYPASS, 3786b1e989eSBjorn Helgaas 0); 37921ad80b0SFrank Li 38021ad80b0SFrank Li return 0; 38121ad80b0SFrank Li } 38221ad80b0SFrank Li 38321ad80b0SFrank Li static int imx7d_pcie_init_phy(struct imx6_pcie *imx6_pcie) 38421ad80b0SFrank Li { 38521ad80b0SFrank Li regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); 38621ad80b0SFrank Li 38721ad80b0SFrank Li return 0; 38821ad80b0SFrank Li } 38921ad80b0SFrank Li 39021ad80b0SFrank Li static int imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) 39121ad80b0SFrank Li { 3926b1e989eSBjorn Helgaas regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 3936b1e989eSBjorn Helgaas IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); 3946b1e989eSBjorn Helgaas 3956b1e989eSBjorn Helgaas /* configure constant input signal to the pcie ctrl and phy */ 3966b1e989eSBjorn Helgaas regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 3976b1e989eSBjorn Helgaas IMX6Q_GPR12_LOS_LEVEL, 9 << 4); 3986b1e989eSBjorn Helgaas 3996b1e989eSBjorn Helgaas regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 4006b1e989eSBjorn Helgaas IMX6Q_GPR8_TX_DEEMPH_GEN1, 4016b1e989eSBjorn Helgaas imx6_pcie->tx_deemph_gen1 << 0); 4026b1e989eSBjorn Helgaas regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 4036b1e989eSBjorn Helgaas IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 4046b1e989eSBjorn Helgaas imx6_pcie->tx_deemph_gen2_3p5db << 6); 4056b1e989eSBjorn Helgaas regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 4066b1e989eSBjorn Helgaas IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 4076b1e989eSBjorn Helgaas imx6_pcie->tx_deemph_gen2_6db << 12); 4086b1e989eSBjorn Helgaas regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 4096b1e989eSBjorn Helgaas IMX6Q_GPR8_TX_SWING_FULL, 4106b1e989eSBjorn Helgaas imx6_pcie->tx_swing_full << 18); 4116b1e989eSBjorn Helgaas regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 4126b1e989eSBjorn Helgaas IMX6Q_GPR8_TX_SWING_LOW, 4136b1e989eSBjorn Helgaas imx6_pcie->tx_swing_low << 25); 41421ad80b0SFrank Li return 0; 4156b1e989eSBjorn Helgaas } 4166b1e989eSBjorn Helgaas 41721ad80b0SFrank Li static int imx6sx_pcie_init_phy(struct imx6_pcie *imx6_pcie) 41821ad80b0SFrank Li { 41921ad80b0SFrank Li regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 42021ad80b0SFrank Li IMX6SX_GPR12_PCIE_RX_EQ_MASK, IMX6SX_GPR12_PCIE_RX_EQ_2); 42121ad80b0SFrank Li 42221ad80b0SFrank Li return imx6_pcie_init_phy(imx6_pcie); 4236b1e989eSBjorn Helgaas } 4246b1e989eSBjorn Helgaas 4256b1e989eSBjorn Helgaas static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) 4266b1e989eSBjorn Helgaas { 4276b1e989eSBjorn Helgaas u32 val; 4286b1e989eSBjorn Helgaas struct device *dev = imx6_pcie->pci->dev; 4296b1e989eSBjorn Helgaas 4306b1e989eSBjorn Helgaas if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, 4316b1e989eSBjorn Helgaas IOMUXC_GPR22, val, 4326b1e989eSBjorn Helgaas val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED, 4336b1e989eSBjorn Helgaas PHY_PLL_LOCK_WAIT_USLEEP_MAX, 4346b1e989eSBjorn Helgaas PHY_PLL_LOCK_WAIT_TIMEOUT)) 4356b1e989eSBjorn Helgaas dev_err(dev, "PCIe PLL lock timeout\n"); 4366b1e989eSBjorn Helgaas } 4376b1e989eSBjorn Helgaas 4386b1e989eSBjorn Helgaas static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) 4396b1e989eSBjorn Helgaas { 4406a401858SFrank Li unsigned long phy_rate = 0; 4416b1e989eSBjorn Helgaas int mult, div; 4426b1e989eSBjorn Helgaas u16 val; 4436a401858SFrank Li int i; 4446b1e989eSBjorn Helgaas 4456b1e989eSBjorn Helgaas if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 4466b1e989eSBjorn Helgaas return 0; 4476b1e989eSBjorn Helgaas 4486a401858SFrank Li for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++) 4496a401858SFrank Li if (strncmp(imx6_pcie->clks[i].id, "pcie_phy", 8) == 0) 4506a401858SFrank Li phy_rate = clk_get_rate(imx6_pcie->clks[i].clk); 4516a401858SFrank Li 4526b1e989eSBjorn Helgaas switch (phy_rate) { 4536b1e989eSBjorn Helgaas case 125000000: 4546b1e989eSBjorn Helgaas /* 4556b1e989eSBjorn Helgaas * The default settings of the MPLL are for a 125MHz input 4566b1e989eSBjorn Helgaas * clock, so no need to reconfigure anything in that case. 4576b1e989eSBjorn Helgaas */ 4586b1e989eSBjorn Helgaas return 0; 4596b1e989eSBjorn Helgaas case 100000000: 4606b1e989eSBjorn Helgaas mult = 25; 4616b1e989eSBjorn Helgaas div = 0; 4626b1e989eSBjorn Helgaas break; 4636b1e989eSBjorn Helgaas case 200000000: 4646b1e989eSBjorn Helgaas mult = 25; 4656b1e989eSBjorn Helgaas div = 1; 4666b1e989eSBjorn Helgaas break; 4676b1e989eSBjorn Helgaas default: 4686b1e989eSBjorn Helgaas dev_err(imx6_pcie->pci->dev, 4696b1e989eSBjorn Helgaas "Unsupported PHY reference clock rate %lu\n", phy_rate); 4706b1e989eSBjorn Helgaas return -EINVAL; 4716b1e989eSBjorn Helgaas } 4726b1e989eSBjorn Helgaas 4736b1e989eSBjorn Helgaas pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); 4746b1e989eSBjorn Helgaas val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK << 4756b1e989eSBjorn Helgaas PCIE_PHY_MPLL_MULTIPLIER_SHIFT); 4766b1e989eSBjorn Helgaas val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT; 4776b1e989eSBjorn Helgaas val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD; 4786b1e989eSBjorn Helgaas pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); 4796b1e989eSBjorn Helgaas 4806b1e989eSBjorn Helgaas pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val); 4816b1e989eSBjorn Helgaas val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK << 4826b1e989eSBjorn Helgaas PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT); 4836b1e989eSBjorn Helgaas val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT; 4846b1e989eSBjorn Helgaas val |= PCIE_PHY_ATEOVRD_EN; 4856b1e989eSBjorn Helgaas pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val); 4866b1e989eSBjorn Helgaas 4876b1e989eSBjorn Helgaas return 0; 4886b1e989eSBjorn Helgaas } 4896b1e989eSBjorn Helgaas 4906e0832faSShawn Lin static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) 4916e0832faSShawn Lin { 49237d5d32aSAndrey Smirnov u16 tmp; 4936e0832faSShawn Lin 4942f532d07SAndrey Smirnov if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 4952f532d07SAndrey Smirnov return; 4962f532d07SAndrey Smirnov 4976e0832faSShawn Lin pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 4986e0832faSShawn Lin tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | 4996e0832faSShawn Lin PHY_RX_OVRD_IN_LO_RX_PLL_EN); 5006e0832faSShawn Lin pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 5016e0832faSShawn Lin 5026e0832faSShawn Lin usleep_range(2000, 3000); 5036e0832faSShawn Lin 5046e0832faSShawn Lin pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 5056e0832faSShawn Lin tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | 5066e0832faSShawn Lin PHY_RX_OVRD_IN_LO_RX_PLL_EN); 5076e0832faSShawn Lin pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 5086e0832faSShawn Lin } 5096e0832faSShawn Lin 5102d8ed461SAndrey Smirnov #ifdef CONFIG_ARM 5116e0832faSShawn Lin /* Added for PCI abort handling */ 5126e0832faSShawn Lin static int imx6q_pcie_abort_handler(unsigned long addr, 5136e0832faSShawn Lin unsigned int fsr, struct pt_regs *regs) 5146e0832faSShawn Lin { 5156e0832faSShawn Lin unsigned long pc = instruction_pointer(regs); 5166e0832faSShawn Lin unsigned long instr = *(unsigned long *)pc; 5176e0832faSShawn Lin int reg = (instr >> 12) & 15; 5186e0832faSShawn Lin 5196e0832faSShawn Lin /* 5206e0832faSShawn Lin * If the instruction being executed was a read, 5216e0832faSShawn Lin * make it look like it read all-ones. 5226e0832faSShawn Lin */ 5236e0832faSShawn Lin if ((instr & 0x0c100000) == 0x04100000) { 5246e0832faSShawn Lin unsigned long val; 5256e0832faSShawn Lin 5266e0832faSShawn Lin if (instr & 0x00400000) 5276e0832faSShawn Lin val = 255; 5286e0832faSShawn Lin else 5296e0832faSShawn Lin val = -1; 5306e0832faSShawn Lin 5316e0832faSShawn Lin regs->uregs[reg] = val; 5326e0832faSShawn Lin regs->ARM_pc += 4; 5336e0832faSShawn Lin return 0; 5346e0832faSShawn Lin } 5356e0832faSShawn Lin 5366e0832faSShawn Lin if ((instr & 0x0e100090) == 0x00100090) { 5376e0832faSShawn Lin regs->uregs[reg] = -1; 5386e0832faSShawn Lin regs->ARM_pc += 4; 5396e0832faSShawn Lin return 0; 5406e0832faSShawn Lin } 5416e0832faSShawn Lin 5426e0832faSShawn Lin return 1; 5436e0832faSShawn Lin } 5442d8ed461SAndrey Smirnov #endif 5456e0832faSShawn Lin 5463f7cceeaSLeonard Crestez static int imx6_pcie_attach_pd(struct device *dev) 5473f7cceeaSLeonard Crestez { 5483f7cceeaSLeonard Crestez struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 5493f7cceeaSLeonard Crestez struct device_link *link; 5503f7cceeaSLeonard Crestez 5513f7cceeaSLeonard Crestez /* Do nothing when in a single power domain */ 5523f7cceeaSLeonard Crestez if (dev->pm_domain) 5533f7cceeaSLeonard Crestez return 0; 5543f7cceeaSLeonard Crestez 5553f7cceeaSLeonard Crestez imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); 5563f7cceeaSLeonard Crestez if (IS_ERR(imx6_pcie->pd_pcie)) 5573f7cceeaSLeonard Crestez return PTR_ERR(imx6_pcie->pd_pcie); 558a6093ad7SLeonard Crestez /* Do nothing when power domain missing */ 559a6093ad7SLeonard Crestez if (!imx6_pcie->pd_pcie) 560a6093ad7SLeonard Crestez return 0; 5613f7cceeaSLeonard Crestez link = device_link_add(dev, imx6_pcie->pd_pcie, 5623f7cceeaSLeonard Crestez DL_FLAG_STATELESS | 5633f7cceeaSLeonard Crestez DL_FLAG_PM_RUNTIME | 5643f7cceeaSLeonard Crestez DL_FLAG_RPM_ACTIVE); 5653f7cceeaSLeonard Crestez if (!link) { 5663f7cceeaSLeonard Crestez dev_err(dev, "Failed to add device_link to pcie pd.\n"); 5673f7cceeaSLeonard Crestez return -EINVAL; 5683f7cceeaSLeonard Crestez } 5693f7cceeaSLeonard Crestez 5703f7cceeaSLeonard Crestez imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); 5713f7cceeaSLeonard Crestez if (IS_ERR(imx6_pcie->pd_pcie_phy)) 5723f7cceeaSLeonard Crestez return PTR_ERR(imx6_pcie->pd_pcie_phy); 5733f7cceeaSLeonard Crestez 574a4ace4faSLeonard Crestez link = device_link_add(dev, imx6_pcie->pd_pcie_phy, 5753f7cceeaSLeonard Crestez DL_FLAG_STATELESS | 5763f7cceeaSLeonard Crestez DL_FLAG_PM_RUNTIME | 5773f7cceeaSLeonard Crestez DL_FLAG_RPM_ACTIVE); 578a4ace4faSLeonard Crestez if (!link) { 579a4ace4faSLeonard Crestez dev_err(dev, "Failed to add device_link to pcie_phy pd.\n"); 580a4ace4faSLeonard Crestez return -EINVAL; 5813f7cceeaSLeonard Crestez } 5823f7cceeaSLeonard Crestez 5833f7cceeaSLeonard Crestez return 0; 5843f7cceeaSLeonard Crestez } 5853f7cceeaSLeonard Crestez 5866e0832faSShawn Lin static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) 5876e0832faSShawn Lin { 5882d8ed461SAndrey Smirnov unsigned int offset; 5896e0832faSShawn Lin int ret = 0; 5906e0832faSShawn Lin 591e8e4d4e9SAndrey Smirnov switch (imx6_pcie->drvdata->variant) { 5926e0832faSShawn Lin case IMX6SX: 5936e0832faSShawn Lin regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 5946e0832faSShawn Lin IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); 5956e0832faSShawn Lin break; 59673abd0bfSGustavo A. R. Silva case IMX6QP: 5976e0832faSShawn Lin case IMX6Q: 5986e0832faSShawn Lin /* power up core phy and enable ref clock */ 5996e0832faSShawn Lin regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 6006e0832faSShawn Lin IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); 6016e0832faSShawn Lin /* 6026e0832faSShawn Lin * the async reset input need ref clock to sync internally, 6036e0832faSShawn Lin * when the ref clock comes after reset, internal synced 6046e0832faSShawn Lin * reset time is too short, cannot meet the requirement. 6056e0832faSShawn Lin * add one ~10us delay here. 6066e0832faSShawn Lin */ 60787cb3127SAndrey Smirnov usleep_range(10, 100); 6086e0832faSShawn Lin regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 6096e0832faSShawn Lin IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); 6106e0832faSShawn Lin break; 6116e0832faSShawn Lin case IMX7D: 612f5c04da3SFrank Li case IMX95: 613b7d67c61SFrank Li case IMX95_EP: 6146e0832faSShawn Lin break; 615178e244cSRichard Zhu case IMX8MM: 616fb3217e2SRichard Zhu case IMX8MM_EP: 6172d8ed461SAndrey Smirnov case IMX8MQ: 618530ba412SRichard Zhu case IMX8MQ_EP: 6193db1e531SRichard Zhu case IMX8MP: 620c435669aSRichard Zhu case IMX8MP_EP: 6212d8ed461SAndrey Smirnov offset = imx6_pcie_grp_offset(imx6_pcie); 6222d8ed461SAndrey Smirnov /* 6232d8ed461SAndrey Smirnov * Set the over ride low and enabled 6242d8ed461SAndrey Smirnov * make sure that REF_CLK is turned on. 6252d8ed461SAndrey Smirnov */ 6262d8ed461SAndrey Smirnov regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 6272d8ed461SAndrey Smirnov IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, 6282d8ed461SAndrey Smirnov 0); 6292d8ed461SAndrey Smirnov regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 6302d8ed461SAndrey Smirnov IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, 6312d8ed461SAndrey Smirnov IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); 6322d8ed461SAndrey Smirnov break; 6336e0832faSShawn Lin } 6346e0832faSShawn Lin 6356e0832faSShawn Lin return ret; 6366e0832faSShawn Lin } 6376e0832faSShawn Lin 638d0a75c79SBjorn Helgaas static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) 63934b1b902SRichard Zhu { 64034b1b902SRichard Zhu switch (imx6_pcie->drvdata->variant) { 641fea446ebSRichard Zhu case IMX6QP: 642fea446ebSRichard Zhu case IMX6Q: 643fea446ebSRichard Zhu regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 644fea446ebSRichard Zhu IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); 645fea446ebSRichard Zhu regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 646fea446ebSRichard Zhu IMX6Q_GPR1_PCIE_TEST_PD, 647fea446ebSRichard Zhu IMX6Q_GPR1_PCIE_TEST_PD); 648fea446ebSRichard Zhu break; 64934b1b902SRichard Zhu case IMX7D: 65034b1b902SRichard Zhu regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 65134b1b902SRichard Zhu IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 65234b1b902SRichard Zhu IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); 65334b1b902SRichard Zhu break; 65434b1b902SRichard Zhu default: 65534b1b902SRichard Zhu break; 65634b1b902SRichard Zhu } 65734b1b902SRichard Zhu } 65834b1b902SRichard Zhu 659835fe229SRichard Zhu static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) 660835fe229SRichard Zhu { 661835fe229SRichard Zhu struct dw_pcie *pci = imx6_pcie->pci; 662835fe229SRichard Zhu struct device *dev = pci->dev; 663835fe229SRichard Zhu int ret; 664835fe229SRichard Zhu 6656a401858SFrank Li ret = clk_bulk_prepare_enable(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); 6666a401858SFrank Li if (ret) 667835fe229SRichard Zhu return ret; 668835fe229SRichard Zhu 669835fe229SRichard Zhu ret = imx6_pcie_enable_ref_clk(imx6_pcie); 670835fe229SRichard Zhu if (ret) { 671835fe229SRichard Zhu dev_err(dev, "unable to enable pcie ref clock\n"); 672835fe229SRichard Zhu goto err_ref_clk; 673835fe229SRichard Zhu } 674835fe229SRichard Zhu 675835fe229SRichard Zhu /* allow the clocks to stabilize */ 676835fe229SRichard Zhu usleep_range(200, 500); 677835fe229SRichard Zhu return 0; 678835fe229SRichard Zhu 679835fe229SRichard Zhu err_ref_clk: 6806a401858SFrank Li clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); 681835fe229SRichard Zhu 682835fe229SRichard Zhu return ret; 683835fe229SRichard Zhu } 684835fe229SRichard Zhu 685d0a75c79SBjorn Helgaas static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) 686d0a75c79SBjorn Helgaas { 687d0a75c79SBjorn Helgaas imx6_pcie_disable_ref_clk(imx6_pcie); 6886a401858SFrank Li clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); 689d0a75c79SBjorn Helgaas } 690d0a75c79SBjorn Helgaas 69127650969SBjorn Helgaas static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) 69227650969SBjorn Helgaas { 69327650969SBjorn Helgaas reset_control_assert(imx6_pcie->pciephy_reset); 69427650969SBjorn Helgaas reset_control_assert(imx6_pcie->apps_reset); 6950c9651c2SFrank Li 6960c9651c2SFrank Li switch (imx6_pcie->drvdata->variant) { 69727650969SBjorn Helgaas case IMX6SX: 69827650969SBjorn Helgaas regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 69927650969SBjorn Helgaas IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 70027650969SBjorn Helgaas IMX6SX_GPR12_PCIE_TEST_POWERDOWN); 70127650969SBjorn Helgaas /* Force PCIe PHY reset */ 70227650969SBjorn Helgaas regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 70327650969SBjorn Helgaas IMX6SX_GPR5_PCIE_BTNRST_RESET, 70427650969SBjorn Helgaas IMX6SX_GPR5_PCIE_BTNRST_RESET); 70527650969SBjorn Helgaas break; 70627650969SBjorn Helgaas case IMX6QP: 70727650969SBjorn Helgaas regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 70827650969SBjorn Helgaas IMX6Q_GPR1_PCIE_SW_RST, 70927650969SBjorn Helgaas IMX6Q_GPR1_PCIE_SW_RST); 71027650969SBjorn Helgaas break; 71127650969SBjorn Helgaas case IMX6Q: 71227650969SBjorn Helgaas regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 71327650969SBjorn Helgaas IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); 71427650969SBjorn Helgaas regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 71527650969SBjorn Helgaas IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); 71627650969SBjorn Helgaas break; 7170c9651c2SFrank Li default: 7180c9651c2SFrank Li break; 71927650969SBjorn Helgaas } 72027650969SBjorn Helgaas 72127650969SBjorn Helgaas /* Some boards don't have PCIe reset GPIO. */ 7222e81122dSAndy Shevchenko gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 1); 72327650969SBjorn Helgaas } 72427650969SBjorn Helgaas 7259751f65dSRichard Zhu static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) 7266e0832faSShawn Lin { 7276e0832faSShawn Lin struct dw_pcie *pci = imx6_pcie->pci; 7286e0832faSShawn Lin struct device *dev = pci->dev; 7296e0832faSShawn Lin 7306e0832faSShawn Lin reset_control_deassert(imx6_pcie->pciephy_reset); 7311df82ec4STrent Piepho 7320c9651c2SFrank Li switch (imx6_pcie->drvdata->variant) { 7330c9651c2SFrank Li case IMX7D: 7341df82ec4STrent Piepho /* Workaround for ERR010728, failure of PCI-e PLL VCO to 7351df82ec4STrent Piepho * oscillate, especially when cold. This turns off "Duty-cycle 7361df82ec4STrent Piepho * Corrector" and other mysterious undocumented things. 7371df82ec4STrent Piepho */ 7381df82ec4STrent Piepho if (likely(imx6_pcie->phy_base)) { 7391df82ec4STrent Piepho /* De-assert DCC_FB_EN */ 7401df82ec4STrent Piepho writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, 7411df82ec4STrent Piepho imx6_pcie->phy_base + PCIE_PHY_CMN_REG4); 7421df82ec4STrent Piepho /* Assert RX_EQS and RX_EQS_SEL */ 7431df82ec4STrent Piepho writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL 7441df82ec4STrent Piepho | PCIE_PHY_CMN_REG24_RX_EQ, 7451df82ec4STrent Piepho imx6_pcie->phy_base + PCIE_PHY_CMN_REG24); 7461df82ec4STrent Piepho /* Assert ATT_MODE */ 7471df82ec4STrent Piepho writel(PCIE_PHY_CMN_REG26_ATT_MODE, 7481df82ec4STrent Piepho imx6_pcie->phy_base + PCIE_PHY_CMN_REG26); 7491df82ec4STrent Piepho } else { 7501df82ec4STrent Piepho dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); 7511df82ec4STrent Piepho } 7521df82ec4STrent Piepho 7536e0832faSShawn Lin imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); 7546e0832faSShawn Lin break; 7556e0832faSShawn Lin case IMX6SX: 7566e0832faSShawn Lin regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 7576e0832faSShawn Lin IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); 7586e0832faSShawn Lin break; 7596e0832faSShawn Lin case IMX6QP: 7606e0832faSShawn Lin regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 7616e0832faSShawn Lin IMX6Q_GPR1_PCIE_SW_RST, 0); 7626e0832faSShawn Lin 7636e0832faSShawn Lin usleep_range(200, 500); 7646e0832faSShawn Lin break; 7650c9651c2SFrank Li default: 7666e0832faSShawn Lin break; 7676e0832faSShawn Lin } 7686e0832faSShawn Lin 769a6809941SFrancesco Dolcini /* Some boards don't have PCIe reset GPIO. */ 7702e81122dSAndy Shevchenko if (imx6_pcie->reset_gpiod) { 771a6809941SFrancesco Dolcini msleep(100); 7722e81122dSAndy Shevchenko gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 0); 773a6809941SFrancesco Dolcini /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ 774a6809941SFrancesco Dolcini msleep(100); 775a6809941SFrancesco Dolcini } 776a6809941SFrancesco Dolcini 7779751f65dSRichard Zhu return 0; 7786e0832faSShawn Lin } 7796e0832faSShawn Lin 7806e0832faSShawn Lin static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) 7816e0832faSShawn Lin { 7826e0832faSShawn Lin struct dw_pcie *pci = imx6_pcie->pci; 7836e0832faSShawn Lin struct device *dev = pci->dev; 7846e0832faSShawn Lin u32 tmp; 7856e0832faSShawn Lin unsigned int retries; 7866e0832faSShawn Lin 7876e0832faSShawn Lin for (retries = 0; retries < 200; retries++) { 7886e0832faSShawn Lin tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 7896e0832faSShawn Lin /* Test if the speed change finished. */ 7906e0832faSShawn Lin if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) 7916e0832faSShawn Lin return 0; 7926e0832faSShawn Lin usleep_range(100, 1000); 7936e0832faSShawn Lin } 7946e0832faSShawn Lin 7956e0832faSShawn Lin dev_err(dev, "Speed change timeout\n"); 796c377690cSAndrey Smirnov return -ETIMEDOUT; 7976e0832faSShawn Lin } 7986e0832faSShawn Lin 7990ee2c1f2SLeonard Crestez static void imx6_pcie_ltssm_enable(struct device *dev) 8000ee2c1f2SLeonard Crestez { 8010ee2c1f2SLeonard Crestez struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 802d99aa8d3SFrank Li const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; 8030ee2c1f2SLeonard Crestez 804d99aa8d3SFrank Li if (drvdata->ltssm_mask) 805d99aa8d3SFrank Li regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, 806d99aa8d3SFrank Li drvdata->ltssm_mask); 8070c9651c2SFrank Li 8080c9651c2SFrank Li reset_control_deassert(imx6_pcie->apps_reset); 8090ee2c1f2SLeonard Crestez } 8100ee2c1f2SLeonard Crestez 8111c5e7615SRichard Zhu static void imx6_pcie_ltssm_disable(struct device *dev) 8121c5e7615SRichard Zhu { 8131c5e7615SRichard Zhu struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 814d99aa8d3SFrank Li const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; 8151c5e7615SRichard Zhu 816d99aa8d3SFrank Li if (drvdata->ltssm_mask) 817d99aa8d3SFrank Li regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, 818d99aa8d3SFrank Li drvdata->ltssm_mask, 0); 8190c9651c2SFrank Li 8200c9651c2SFrank Li reset_control_assert(imx6_pcie->apps_reset); 8211c5e7615SRichard Zhu } 8221c5e7615SRichard Zhu 823886a9c13SRob Herring static int imx6_pcie_start_link(struct dw_pcie *pci) 8246e0832faSShawn Lin { 825886a9c13SRob Herring struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 8266e0832faSShawn Lin struct device *dev = pci->dev; 827201a8df8SRob Herring u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 8286e0832faSShawn Lin u32 tmp; 8296e0832faSShawn Lin int ret; 8306e0832faSShawn Lin 8316e0832faSShawn Lin /* 8326e0832faSShawn Lin * Force Gen1 operation when starting the link. In case the link is 8336e0832faSShawn Lin * started in Gen2 mode, there is a possibility the devices on the 8346e0832faSShawn Lin * bus will not be detected at all. This happens with PCIe switches. 8356e0832faSShawn Lin */ 83613f8f3d1SRichard Zhu dw_pcie_dbi_ro_wr_en(pci); 837201a8df8SRob Herring tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 838201a8df8SRob Herring tmp &= ~PCI_EXP_LNKCAP_SLS; 839201a8df8SRob Herring tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; 840201a8df8SRob Herring dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); 84113f8f3d1SRichard Zhu dw_pcie_dbi_ro_wr_dis(pci); 8426e0832faSShawn Lin 8436e0832faSShawn Lin /* Start LTSSM. */ 8440ee2c1f2SLeonard Crestez imx6_pcie_ltssm_enable(dev); 8456e0832faSShawn Lin 846508919d0SRichard Zhu ret = dw_pcie_wait_for_link(pci); 847508919d0SRichard Zhu if (ret) 848508919d0SRichard Zhu goto err_reset_phy; 8496e0832faSShawn Lin 8506213c6c5SRichard Zhu if (pci->link_gen > 1) { 8516213c6c5SRichard Zhu /* Allow faster modes after the link is up */ 85213f8f3d1SRichard Zhu dw_pcie_dbi_ro_wr_en(pci); 853201a8df8SRob Herring tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 854201a8df8SRob Herring tmp &= ~PCI_EXP_LNKCAP_SLS; 8556213c6c5SRichard Zhu tmp |= pci->link_gen; 856201a8df8SRob Herring dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); 8576e0832faSShawn Lin 8586e0832faSShawn Lin /* 8596e0832faSShawn Lin * Start Directed Speed Change so the best possible 8606e0832faSShawn Lin * speed both link partners support can be negotiated. 8616e0832faSShawn Lin */ 8626e0832faSShawn Lin tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 8636e0832faSShawn Lin tmp |= PORT_LOGIC_SPEED_CHANGE; 8646e0832faSShawn Lin dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); 86513f8f3d1SRichard Zhu dw_pcie_dbi_ro_wr_dis(pci); 8666e0832faSShawn Lin 8674c458bb3SAndrey Smirnov if (imx6_pcie->drvdata->flags & 8684c458bb3SAndrey Smirnov IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) { 8696e0832faSShawn Lin /* 8706e0832faSShawn Lin * On i.MX7, DIRECT_SPEED_CHANGE behaves differently 8716e0832faSShawn Lin * from i.MX6 family when no link speed transition 8726e0832faSShawn Lin * occurs and we go Gen1 -> yep, Gen1. The difference 8736e0832faSShawn Lin * is that, in such case, it will not be cleared by HW 8746e0832faSShawn Lin * which will cause the following code to report false 8756e0832faSShawn Lin * failure. 8766e0832faSShawn Lin */ 8776e0832faSShawn Lin 8786e0832faSShawn Lin ret = imx6_pcie_wait_for_speed_change(imx6_pcie); 8796e0832faSShawn Lin if (ret) { 8806e0832faSShawn Lin dev_err(dev, "Failed to bring link up!\n"); 8816e0832faSShawn Lin goto err_reset_phy; 8826e0832faSShawn Lin } 8836e0832faSShawn Lin } 8846e0832faSShawn Lin 8856e0832faSShawn Lin /* Make sure link training is finished as well! */ 886508919d0SRichard Zhu ret = dw_pcie_wait_for_link(pci); 887508919d0SRichard Zhu if (ret) 888508919d0SRichard Zhu goto err_reset_phy; 8896e0832faSShawn Lin } else { 8906213c6c5SRichard Zhu dev_info(dev, "Link: Only Gen1 is enabled\n"); 8916e0832faSShawn Lin } 8926e0832faSShawn Lin 893af48f822SRichard Zhu imx6_pcie->link_is_up = true; 894201a8df8SRob Herring tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); 895201a8df8SRob Herring dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); 8966e0832faSShawn Lin return 0; 8976e0832faSShawn Lin 8986e0832faSShawn Lin err_reset_phy: 899af48f822SRichard Zhu imx6_pcie->link_is_up = false; 9006e0832faSShawn Lin dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", 90160ef4b07SAndrey Smirnov dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), 90260ef4b07SAndrey Smirnov dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); 9036e0832faSShawn Lin imx6_pcie_reset_phy(imx6_pcie); 904508919d0SRichard Zhu return 0; 9056e0832faSShawn Lin } 9066e0832faSShawn Lin 907835a345bSRichard Zhu static void imx6_pcie_stop_link(struct dw_pcie *pci) 908835a345bSRichard Zhu { 909835a345bSRichard Zhu struct device *dev = pci->dev; 910835a345bSRichard Zhu 911835a345bSRichard Zhu /* Turn off PCIe LTSSM */ 912835a345bSRichard Zhu imx6_pcie_ltssm_disable(dev); 913835a345bSRichard Zhu } 914835a345bSRichard Zhu 91560b3c27fSSerge Semin static int imx6_pcie_host_init(struct dw_pcie_rp *pp) 9166e0832faSShawn Lin { 9176e0832faSShawn Lin struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 9189751f65dSRichard Zhu struct device *dev = pci->dev; 9196e0832faSShawn Lin struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 9209751f65dSRichard Zhu int ret; 9216e0832faSShawn Lin 922f0691e32SRichard Zhu if (imx6_pcie->vpcie) { 923f0691e32SRichard Zhu ret = regulator_enable(imx6_pcie->vpcie); 924f0691e32SRichard Zhu if (ret) { 925f0691e32SRichard Zhu dev_err(dev, "failed to enable vpcie regulator: %d\n", 926f0691e32SRichard Zhu ret); 927f0691e32SRichard Zhu return ret; 928f0691e32SRichard Zhu } 929f0691e32SRichard Zhu } 930f0691e32SRichard Zhu 9316e0832faSShawn Lin imx6_pcie_assert_core_reset(imx6_pcie); 93221ad80b0SFrank Li 93321ad80b0SFrank Li if (imx6_pcie->drvdata->init_phy) 93421ad80b0SFrank Li imx6_pcie->drvdata->init_phy(imx6_pcie); 93521ad80b0SFrank Li 93621ad80b0SFrank Li imx6_pcie_configure_type(imx6_pcie); 937cf236e0cSRichard Zhu 938835a345bSRichard Zhu ret = imx6_pcie_clk_enable(imx6_pcie); 939835a345bSRichard Zhu if (ret) { 940835a345bSRichard Zhu dev_err(dev, "unable to enable pcie clocks: %d\n", ret); 941835a345bSRichard Zhu goto err_reg_disable; 942835a345bSRichard Zhu } 943835a345bSRichard Zhu 944cf236e0cSRichard Zhu if (imx6_pcie->phy) { 945cbcf8722SRichard Zhu ret = phy_init(imx6_pcie->phy); 946cf236e0cSRichard Zhu if (ret) { 947cf236e0cSRichard Zhu dev_err(dev, "pcie PHY power up failed\n"); 948835a345bSRichard Zhu goto err_clk_disable; 949cf236e0cSRichard Zhu } 950cf236e0cSRichard Zhu } 951cf236e0cSRichard Zhu 952cf236e0cSRichard Zhu if (imx6_pcie->phy) { 953cbcf8722SRichard Zhu ret = phy_power_on(imx6_pcie->phy); 954cf236e0cSRichard Zhu if (ret) { 955cf236e0cSRichard Zhu dev_err(dev, "waiting for PHY ready timeout!\n"); 956835a345bSRichard Zhu goto err_phy_off; 957cf236e0cSRichard Zhu } 958cf236e0cSRichard Zhu } 959ae6b9a65SSascha Hauer 960ae6b9a65SSascha Hauer ret = imx6_pcie_deassert_core_reset(imx6_pcie); 961ae6b9a65SSascha Hauer if (ret < 0) { 962ae6b9a65SSascha Hauer dev_err(dev, "pcie deassert core reset failed: %d\n", ret); 963ae6b9a65SSascha Hauer goto err_phy_off; 964ae6b9a65SSascha Hauer } 965ae6b9a65SSascha Hauer 966f18f42d7SLucas Stach imx6_setup_phy_mpll(imx6_pcie); 9676e0832faSShawn Lin 9686e0832faSShawn Lin return 0; 969f0691e32SRichard Zhu 970cf236e0cSRichard Zhu err_phy_off: 971cf236e0cSRichard Zhu if (imx6_pcie->phy) 972cbcf8722SRichard Zhu phy_exit(imx6_pcie->phy); 973835a345bSRichard Zhu err_clk_disable: 974835a345bSRichard Zhu imx6_pcie_clk_disable(imx6_pcie); 975f0691e32SRichard Zhu err_reg_disable: 976f0691e32SRichard Zhu if (imx6_pcie->vpcie) 977f0691e32SRichard Zhu regulator_disable(imx6_pcie->vpcie); 978f0691e32SRichard Zhu return ret; 9796e0832faSShawn Lin } 9806e0832faSShawn Lin 981835a345bSRichard Zhu static void imx6_pcie_host_exit(struct dw_pcie_rp *pp) 982835a345bSRichard Zhu { 983835a345bSRichard Zhu struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 984835a345bSRichard Zhu struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 985835a345bSRichard Zhu 986835a345bSRichard Zhu if (imx6_pcie->phy) { 987835a345bSRichard Zhu if (phy_power_off(imx6_pcie->phy)) 988835a345bSRichard Zhu dev_err(pci->dev, "unable to power off PHY\n"); 989835a345bSRichard Zhu phy_exit(imx6_pcie->phy); 990835a345bSRichard Zhu } 991835a345bSRichard Zhu imx6_pcie_clk_disable(imx6_pcie); 992835a345bSRichard Zhu 993835a345bSRichard Zhu if (imx6_pcie->vpcie) 994835a345bSRichard Zhu regulator_disable(imx6_pcie->vpcie); 995835a345bSRichard Zhu } 996835a345bSRichard Zhu 9976e0832faSShawn Lin static const struct dw_pcie_host_ops imx6_pcie_host_ops = { 998aea370b2SYoshihiro Shimoda .init = imx6_pcie_host_init, 999aea370b2SYoshihiro Shimoda .deinit = imx6_pcie_host_exit, 10006e0832faSShawn Lin }; 10016e0832faSShawn Lin 10026e0832faSShawn Lin static const struct dw_pcie_ops dw_pcie_ops = { 1003886a9c13SRob Herring .start_link = imx6_pcie_start_link, 100475c2f26dSRichard Zhu .stop_link = imx6_pcie_stop_link, 10056e0832faSShawn Lin }; 10066e0832faSShawn Lin 100775c2f26dSRichard Zhu static void imx6_pcie_ep_init(struct dw_pcie_ep *ep) 100875c2f26dSRichard Zhu { 100975c2f26dSRichard Zhu enum pci_barno bar; 101075c2f26dSRichard Zhu struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 101175c2f26dSRichard Zhu 101275c2f26dSRichard Zhu for (bar = BAR_0; bar <= BAR_5; bar++) 101375c2f26dSRichard Zhu dw_pcie_ep_reset_bar(pci, bar); 101475c2f26dSRichard Zhu } 101575c2f26dSRichard Zhu 101675c2f26dSRichard Zhu static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 101774955cb8SDamien Le Moal unsigned int type, u16 interrupt_num) 101875c2f26dSRichard Zhu { 101975c2f26dSRichard Zhu struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 102075c2f26dSRichard Zhu 102175c2f26dSRichard Zhu switch (type) { 102274955cb8SDamien Le Moal case PCI_IRQ_INTX: 1023e9af4800SDamien Le Moal return dw_pcie_ep_raise_intx_irq(ep, func_no); 102474955cb8SDamien Le Moal case PCI_IRQ_MSI: 102575c2f26dSRichard Zhu return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 102674955cb8SDamien Le Moal case PCI_IRQ_MSIX: 102775c2f26dSRichard Zhu return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); 102875c2f26dSRichard Zhu default: 102975c2f26dSRichard Zhu dev_err(pci->dev, "UNKNOWN IRQ type\n"); 103075c2f26dSRichard Zhu return -EINVAL; 103175c2f26dSRichard Zhu } 103275c2f26dSRichard Zhu 103375c2f26dSRichard Zhu return 0; 103475c2f26dSRichard Zhu } 103575c2f26dSRichard Zhu 103675c2f26dSRichard Zhu static const struct pci_epc_features imx8m_pcie_epc_features = { 103775c2f26dSRichard Zhu .linkup_notifier = false, 103875c2f26dSRichard Zhu .msi_capable = true, 103975c2f26dSRichard Zhu .msix_capable = false, 1040e01c9797SNiklas Cassel .bar[BAR_1] = { .type = BAR_RESERVED, }, 1041e01c9797SNiklas Cassel .bar[BAR_3] = { .type = BAR_RESERVED, }, 104275c2f26dSRichard Zhu .align = SZ_64K, 104375c2f26dSRichard Zhu }; 104475c2f26dSRichard Zhu 1045b7d67c61SFrank Li /* 1046b7d67c61SFrank Li * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme 1047b7d67c61SFrank Li * ================================================================================================ 1048b7d67c61SFrank Li * BAR0 | Enable | 64-bit | 1 MB | Programmable Size 1049b7d67c61SFrank Li * BAR1 | Disable | 32-bit | 64 KB | Fixed Size 1050b7d67c61SFrank Li * BAR1 should be disabled if BAR0 is 64bit. 1051b7d67c61SFrank Li * BAR2 | Enable | 32-bit | 1 MB | Programmable Size 1052b7d67c61SFrank Li * BAR3 | Enable | 32-bit | 64 KB | Programmable Size 1053b7d67c61SFrank Li * BAR4 | Enable | 32-bit | 1M | Programmable Size 1054b7d67c61SFrank Li * BAR5 | Enable | 32-bit | 64 KB | Programmable Size 1055b7d67c61SFrank Li */ 1056b7d67c61SFrank Li static const struct pci_epc_features imx95_pcie_epc_features = { 1057b7d67c61SFrank Li .msi_capable = true, 1058b7d67c61SFrank Li .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_64K, }, 1059b7d67c61SFrank Li .align = SZ_4K, 1060b7d67c61SFrank Li }; 1061b7d67c61SFrank Li 106275c2f26dSRichard Zhu static const struct pci_epc_features* 106375c2f26dSRichard Zhu imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) 106475c2f26dSRichard Zhu { 10650044966cSFrank Li struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 10660044966cSFrank Li struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 10670044966cSFrank Li 10680044966cSFrank Li return imx6_pcie->drvdata->epc_features; 106975c2f26dSRichard Zhu } 107075c2f26dSRichard Zhu 107175c2f26dSRichard Zhu static const struct dw_pcie_ep_ops pcie_ep_ops = { 1072756dcb5aSYoshihiro Shimoda .init = imx6_pcie_ep_init, 107375c2f26dSRichard Zhu .raise_irq = imx6_pcie_ep_raise_irq, 107475c2f26dSRichard Zhu .get_features = imx6_pcie_ep_get_features, 107575c2f26dSRichard Zhu }; 107675c2f26dSRichard Zhu 107775c2f26dSRichard Zhu static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, 107875c2f26dSRichard Zhu struct platform_device *pdev) 107975c2f26dSRichard Zhu { 108075c2f26dSRichard Zhu int ret; 108175c2f26dSRichard Zhu unsigned int pcie_dbi2_offset; 108275c2f26dSRichard Zhu struct dw_pcie_ep *ep; 108375c2f26dSRichard Zhu struct dw_pcie *pci = imx6_pcie->pci; 108475c2f26dSRichard Zhu struct dw_pcie_rp *pp = &pci->pp; 108575c2f26dSRichard Zhu struct device *dev = pci->dev; 108675c2f26dSRichard Zhu 108775c2f26dSRichard Zhu imx6_pcie_host_init(pp); 108875c2f26dSRichard Zhu ep = &pci->ep; 108975c2f26dSRichard Zhu ep->ops = &pcie_ep_ops; 109075c2f26dSRichard Zhu 109175c2f26dSRichard Zhu switch (imx6_pcie->drvdata->variant) { 1092530ba412SRichard Zhu case IMX8MQ_EP: 1093fb3217e2SRichard Zhu case IMX8MM_EP: 1094c435669aSRichard Zhu case IMX8MP_EP: 1095530ba412SRichard Zhu pcie_dbi2_offset = SZ_1M; 1096530ba412SRichard Zhu break; 109775c2f26dSRichard Zhu default: 109875c2f26dSRichard Zhu pcie_dbi2_offset = SZ_4K; 109975c2f26dSRichard Zhu break; 110075c2f26dSRichard Zhu } 110175c2f26dSRichard Zhu 11021bd0d43dSFrank Li pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; 110375c2f26dSRichard Zhu 1104b7d67c61SFrank Li /* 1105b7d67c61SFrank Li * FIXME: Ideally, dbi2 base address should come from DT. But since only IMX95 is defining 1106b7d67c61SFrank Li * "dbi2" in DT, "dbi_base2" is set to NULL here for that platform alone so that the DWC 1107b7d67c61SFrank Li * core code can fetch that from DT. But once all platform DTs were fixed, this and the 1108b7d67c61SFrank Li * above "dbi_base2" setting should be removed. 1109b7d67c61SFrank Li */ 1110b7d67c61SFrank Li if (device_property_match_string(dev, "reg-names", "dbi2") >= 0) 1111b7d67c61SFrank Li pci->dbi_base2 = NULL; 1112b7d67c61SFrank Li 1113b7d67c61SFrank Li if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) 1114b7d67c61SFrank Li dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 1115b7d67c61SFrank Li 111675c2f26dSRichard Zhu ret = dw_pcie_ep_init(ep); 111775c2f26dSRichard Zhu if (ret) { 111875c2f26dSRichard Zhu dev_err(dev, "failed to initialize endpoint\n"); 111975c2f26dSRichard Zhu return ret; 112075c2f26dSRichard Zhu } 1121df69e17cSManivannan Sadhasivam 1122df69e17cSManivannan Sadhasivam ret = dw_pcie_ep_init_registers(ep); 1123df69e17cSManivannan Sadhasivam if (ret) { 1124df69e17cSManivannan Sadhasivam dev_err(dev, "Failed to initialize DWC endpoint registers\n"); 1125df69e17cSManivannan Sadhasivam dw_pcie_ep_deinit(ep); 1126df69e17cSManivannan Sadhasivam return ret; 1127df69e17cSManivannan Sadhasivam } 1128df69e17cSManivannan Sadhasivam 1129*245b9ebfSManivannan Sadhasivam pci_epc_init_notify(ep->epc); 1130a01e7214SManivannan Sadhasivam 113175c2f26dSRichard Zhu /* Start LTSSM. */ 113275c2f26dSRichard Zhu imx6_pcie_ltssm_enable(dev); 113375c2f26dSRichard Zhu 113475c2f26dSRichard Zhu return 0; 113575c2f26dSRichard Zhu } 113675c2f26dSRichard Zhu 1137f4e833baSLeonard Crestez static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) 1138f4e833baSLeonard Crestez { 11399e56f0dfSLeonard Crestez struct device *dev = imx6_pcie->pci->dev; 11409e56f0dfSLeonard Crestez 11419e56f0dfSLeonard Crestez /* Some variants have a turnoff reset in DT */ 11429e56f0dfSLeonard Crestez if (imx6_pcie->turnoff_reset) { 1143f4e833baSLeonard Crestez reset_control_assert(imx6_pcie->turnoff_reset); 1144f4e833baSLeonard Crestez reset_control_deassert(imx6_pcie->turnoff_reset); 11459e56f0dfSLeonard Crestez goto pm_turnoff_sleep; 11469e56f0dfSLeonard Crestez } 11479e56f0dfSLeonard Crestez 11489e56f0dfSLeonard Crestez /* Others poke directly at IOMUXC registers */ 1149e8e4d4e9SAndrey Smirnov switch (imx6_pcie->drvdata->variant) { 11509e56f0dfSLeonard Crestez case IMX6SX: 1151f81dd043SRichard Zhu case IMX6QP: 11529e56f0dfSLeonard Crestez regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 11539e56f0dfSLeonard Crestez IMX6SX_GPR12_PCIE_PM_TURN_OFF, 11549e56f0dfSLeonard Crestez IMX6SX_GPR12_PCIE_PM_TURN_OFF); 11559e56f0dfSLeonard Crestez regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 11569e56f0dfSLeonard Crestez IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); 11579e56f0dfSLeonard Crestez break; 11589e56f0dfSLeonard Crestez default: 11599e56f0dfSLeonard Crestez dev_err(dev, "PME_Turn_Off not implemented\n"); 11609e56f0dfSLeonard Crestez return; 11619e56f0dfSLeonard Crestez } 1162f4e833baSLeonard Crestez 1163f4e833baSLeonard Crestez /* 1164f4e833baSLeonard Crestez * Components with an upstream port must respond to 1165f4e833baSLeonard Crestez * PME_Turn_Off with PME_TO_Ack but we can't check. 1166f4e833baSLeonard Crestez * 1167f4e833baSLeonard Crestez * The standard recommends a 1-10ms timeout after which to 1168f4e833baSLeonard Crestez * proceed anyway as if acks were received. 1169f4e833baSLeonard Crestez */ 11709e56f0dfSLeonard Crestez pm_turnoff_sleep: 1171f4e833baSLeonard Crestez usleep_range(1000, 10000); 1172f4e833baSLeonard Crestez } 1173f4e833baSLeonard Crestez 11743bbc3c72SRichard Zhu static void imx6_pcie_msi_save_restore(struct imx6_pcie *imx6_pcie, bool save) 11753bbc3c72SRichard Zhu { 11763bbc3c72SRichard Zhu u8 offset; 11773bbc3c72SRichard Zhu u16 val; 11783bbc3c72SRichard Zhu struct dw_pcie *pci = imx6_pcie->pci; 11793bbc3c72SRichard Zhu 11803bbc3c72SRichard Zhu if (pci_msi_enabled()) { 11813bbc3c72SRichard Zhu offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); 11823bbc3c72SRichard Zhu if (save) { 11833bbc3c72SRichard Zhu val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); 11843bbc3c72SRichard Zhu imx6_pcie->msi_ctrl = val; 11853bbc3c72SRichard Zhu } else { 11863bbc3c72SRichard Zhu dw_pcie_dbi_ro_wr_en(pci); 11873bbc3c72SRichard Zhu val = imx6_pcie->msi_ctrl; 11883bbc3c72SRichard Zhu dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); 11893bbc3c72SRichard Zhu dw_pcie_dbi_ro_wr_dis(pci); 11903bbc3c72SRichard Zhu } 11913bbc3c72SRichard Zhu } 11923bbc3c72SRichard Zhu } 11933bbc3c72SRichard Zhu 11940ee2c1f2SLeonard Crestez static int imx6_pcie_suspend_noirq(struct device *dev) 11950ee2c1f2SLeonard Crestez { 11960ee2c1f2SLeonard Crestez struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 1197835a345bSRichard Zhu struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; 11980ee2c1f2SLeonard Crestez 119976d6dc26SAndrey Smirnov if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) 12000ee2c1f2SLeonard Crestez return 0; 12010ee2c1f2SLeonard Crestez 12023bbc3c72SRichard Zhu imx6_pcie_msi_save_restore(imx6_pcie, true); 1203f4e833baSLeonard Crestez imx6_pcie_pm_turnoff(imx6_pcie); 1204835a345bSRichard Zhu imx6_pcie_stop_link(imx6_pcie->pci); 1205835a345bSRichard Zhu imx6_pcie_host_exit(pp); 1206a4bb720eSRichard Zhu 12070ee2c1f2SLeonard Crestez return 0; 12080ee2c1f2SLeonard Crestez } 12090ee2c1f2SLeonard Crestez 12100ee2c1f2SLeonard Crestez static int imx6_pcie_resume_noirq(struct device *dev) 12110ee2c1f2SLeonard Crestez { 12120ee2c1f2SLeonard Crestez int ret; 12130ee2c1f2SLeonard Crestez struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 121460b3c27fSSerge Semin struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; 12150ee2c1f2SLeonard Crestez 121676d6dc26SAndrey Smirnov if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) 12170ee2c1f2SLeonard Crestez return 0; 12180ee2c1f2SLeonard Crestez 1219cfacf22eSRichard Zhu ret = imx6_pcie_host_init(pp); 1220cfacf22eSRichard Zhu if (ret) 1221cfacf22eSRichard Zhu return ret; 12223bbc3c72SRichard Zhu imx6_pcie_msi_save_restore(imx6_pcie, false); 12230ee2c1f2SLeonard Crestez dw_pcie_setup_rc(pp); 12240ee2c1f2SLeonard Crestez 1225af48f822SRichard Zhu if (imx6_pcie->link_is_up) 1226508919d0SRichard Zhu imx6_pcie_start_link(imx6_pcie->pci); 1227af48f822SRichard Zhu 12280ee2c1f2SLeonard Crestez return 0; 12290ee2c1f2SLeonard Crestez } 12300ee2c1f2SLeonard Crestez 12310ee2c1f2SLeonard Crestez static const struct dev_pm_ops imx6_pcie_pm_ops = { 12329d14ad61SBjorn Helgaas NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq, 12330ee2c1f2SLeonard Crestez imx6_pcie_resume_noirq) 12340ee2c1f2SLeonard Crestez }; 12350ee2c1f2SLeonard Crestez 12366e0832faSShawn Lin static int imx6_pcie_probe(struct platform_device *pdev) 12376e0832faSShawn Lin { 12386e0832faSShawn Lin struct device *dev = &pdev->dev; 12396e0832faSShawn Lin struct dw_pcie *pci; 12406e0832faSShawn Lin struct imx6_pcie *imx6_pcie; 12411df82ec4STrent Piepho struct device_node *np; 12426e0832faSShawn Lin struct resource *dbi_base; 12436e0832faSShawn Lin struct device_node *node = dev->of_node; 12446e0832faSShawn Lin int ret; 124575cb8d20SRichard Zhu u16 val; 12466a401858SFrank Li int i; 12476e0832faSShawn Lin 12486e0832faSShawn Lin imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); 12496e0832faSShawn Lin if (!imx6_pcie) 12506e0832faSShawn Lin return -ENOMEM; 12516e0832faSShawn Lin 12526e0832faSShawn Lin pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 12536e0832faSShawn Lin if (!pci) 12546e0832faSShawn Lin return -ENOMEM; 12556e0832faSShawn Lin 12566e0832faSShawn Lin pci->dev = dev; 12576e0832faSShawn Lin pci->ops = &dw_pcie_ops; 125860f5b73fSRob Herring pci->pp.ops = &imx6_pcie_host_ops; 12596e0832faSShawn Lin 12606e0832faSShawn Lin imx6_pcie->pci = pci; 1261e8e4d4e9SAndrey Smirnov imx6_pcie->drvdata = of_device_get_match_data(dev); 12626e0832faSShawn Lin 12631df82ec4STrent Piepho /* Find the PHY if one is defined, only imx7d uses it */ 12641df82ec4STrent Piepho np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); 12651df82ec4STrent Piepho if (np) { 12661df82ec4STrent Piepho struct resource res; 12671df82ec4STrent Piepho 12681df82ec4STrent Piepho ret = of_address_to_resource(np, 0, &res); 12691df82ec4STrent Piepho if (ret) { 12701df82ec4STrent Piepho dev_err(dev, "Unable to map PCIe PHY\n"); 12711df82ec4STrent Piepho return ret; 12721df82ec4STrent Piepho } 12731df82ec4STrent Piepho imx6_pcie->phy_base = devm_ioremap_resource(dev, &res); 1274fd640375SZhen Lei if (IS_ERR(imx6_pcie->phy_base)) 12751df82ec4STrent Piepho return PTR_ERR(imx6_pcie->phy_base); 12761df82ec4STrent Piepho } 12776e0832faSShawn Lin 1278188f46caSYang Li pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base); 12796e0832faSShawn Lin if (IS_ERR(pci->dbi_base)) 12806e0832faSShawn Lin return PTR_ERR(pci->dbi_base); 12816e0832faSShawn Lin 12826e0832faSShawn Lin /* Fetch GPIOs */ 12832e81122dSAndy Shevchenko imx6_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 12842e81122dSAndy Shevchenko if (IS_ERR(imx6_pcie->reset_gpiod)) 12852e81122dSAndy Shevchenko return dev_err_probe(dev, PTR_ERR(imx6_pcie->reset_gpiod), 12862e81122dSAndy Shevchenko "unable to get reset gpio\n"); 12872e81122dSAndy Shevchenko gpiod_set_consumer_name(imx6_pcie->reset_gpiod, "PCIe reset"); 12886e0832faSShawn Lin 12896a401858SFrank Li if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS) 12906a401858SFrank Li return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n"); 12916e0832faSShawn Lin 12926a401858SFrank Li for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++) 12936a401858SFrank Li imx6_pcie->clks[i].id = imx6_pcie->drvdata->clk_names[i]; 12946a401858SFrank Li 12956a401858SFrank Li /* Fetch clocks */ 12966a401858SFrank Li ret = devm_clk_bulk_get(dev, imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); 12976a401858SFrank Li if (ret) 12986a401858SFrank Li return ret; 12996e0832faSShawn Lin 13004e37c2f4SFrank Li if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHYDRV)) { 13014e37c2f4SFrank Li imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); 13024e37c2f4SFrank Li if (IS_ERR(imx6_pcie->phy)) 13034e37c2f4SFrank Li return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), 13044e37c2f4SFrank Li "failed to get pcie phy\n"); 13054e37c2f4SFrank Li } 13064e37c2f4SFrank Li 13070c9651c2SFrank Li if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) { 13080c9651c2SFrank Li imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); 13090c9651c2SFrank Li if (IS_ERR(imx6_pcie->apps_reset)) 13100c9651c2SFrank Li return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), 13110c9651c2SFrank Li "failed to get pcie apps reset control\n"); 13120c9651c2SFrank Li } 13130c9651c2SFrank Li 13140c9651c2SFrank Li if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) { 13150c9651c2SFrank Li imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); 13160c9651c2SFrank Li if (IS_ERR(imx6_pcie->pciephy_reset)) 13170c9651c2SFrank Li return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset), 13180c9651c2SFrank Li "Failed to get PCIEPHY reset control\n"); 13190c9651c2SFrank Li } 13200c9651c2SFrank Li 1321e8e4d4e9SAndrey Smirnov switch (imx6_pcie->drvdata->variant) { 13222d8ed461SAndrey Smirnov case IMX8MQ: 1323530ba412SRichard Zhu case IMX8MQ_EP: 13246e0832faSShawn Lin case IMX7D: 13252d8ed461SAndrey Smirnov if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) 13262d8ed461SAndrey Smirnov imx6_pcie->controller_id = 1; 1327178e244cSRichard Zhu break; 13286e0832faSShawn Lin default: 13296e0832faSShawn Lin break; 13306e0832faSShawn Lin } 13316e0832faSShawn Lin 1332f4e833baSLeonard Crestez /* Grab turnoff reset */ 1333f4e833baSLeonard Crestez imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); 1334f4e833baSLeonard Crestez if (IS_ERR(imx6_pcie->turnoff_reset)) { 1335f4e833baSLeonard Crestez dev_err(dev, "Failed to get TURNOFF reset control\n"); 1336f4e833baSLeonard Crestez return PTR_ERR(imx6_pcie->turnoff_reset); 1337f4e833baSLeonard Crestez } 1338f4e833baSLeonard Crestez 1339f5c04da3SFrank Li if (imx6_pcie->drvdata->gpr) { 13406e0832faSShawn Lin /* Grab GPR config register range */ 13416e0832faSShawn Lin imx6_pcie->iomuxc_gpr = 13423db1e531SRichard Zhu syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); 1343f5c04da3SFrank Li if (IS_ERR(imx6_pcie->iomuxc_gpr)) 1344f5c04da3SFrank Li return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), 1345f5c04da3SFrank Li "unable to find iomuxc registers\n"); 1346f5c04da3SFrank Li } 1347f5c04da3SFrank Li 1348f5c04da3SFrank Li if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) { 1349f5c04da3SFrank Li void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app"); 1350f5c04da3SFrank Li 1351f5c04da3SFrank Li if (IS_ERR(off)) 1352f5c04da3SFrank Li return dev_err_probe(dev, PTR_ERR(off), 1353f5c04da3SFrank Li "unable to find serdes registers\n"); 1354f5c04da3SFrank Li 1355f5c04da3SFrank Li static const struct regmap_config regmap_config = { 1356f5c04da3SFrank Li .reg_bits = 32, 1357f5c04da3SFrank Li .val_bits = 32, 1358f5c04da3SFrank Li .reg_stride = 4, 1359f5c04da3SFrank Li }; 1360f5c04da3SFrank Li 1361f5c04da3SFrank Li imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config); 1362f5c04da3SFrank Li if (IS_ERR(imx6_pcie->iomuxc_gpr)) 1363f5c04da3SFrank Li return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), 1364f5c04da3SFrank Li "unable to find iomuxc registers\n"); 13656e0832faSShawn Lin } 13666e0832faSShawn Lin 13676e0832faSShawn Lin /* Grab PCIe PHY Tx Settings */ 13686e0832faSShawn Lin if (of_property_read_u32(node, "fsl,tx-deemph-gen1", 13696e0832faSShawn Lin &imx6_pcie->tx_deemph_gen1)) 13706e0832faSShawn Lin imx6_pcie->tx_deemph_gen1 = 0; 13716e0832faSShawn Lin 13726e0832faSShawn Lin if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", 13736e0832faSShawn Lin &imx6_pcie->tx_deemph_gen2_3p5db)) 13746e0832faSShawn Lin imx6_pcie->tx_deemph_gen2_3p5db = 0; 13756e0832faSShawn Lin 13766e0832faSShawn Lin if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", 13776e0832faSShawn Lin &imx6_pcie->tx_deemph_gen2_6db)) 13786e0832faSShawn Lin imx6_pcie->tx_deemph_gen2_6db = 20; 13796e0832faSShawn Lin 13806e0832faSShawn Lin if (of_property_read_u32(node, "fsl,tx-swing-full", 13816e0832faSShawn Lin &imx6_pcie->tx_swing_full)) 13826e0832faSShawn Lin imx6_pcie->tx_swing_full = 127; 13836e0832faSShawn Lin 13846e0832faSShawn Lin if (of_property_read_u32(node, "fsl,tx-swing-low", 13856e0832faSShawn Lin &imx6_pcie->tx_swing_low)) 13866e0832faSShawn Lin imx6_pcie->tx_swing_low = 127; 13876e0832faSShawn Lin 13886e0832faSShawn Lin /* Limit link speed */ 138939bc5006SRob Herring pci->link_gen = 1; 139065315ec5SKrzysztof Wilczyński of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen); 13916e0832faSShawn Lin 13926e0832faSShawn Lin imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); 13936e0832faSShawn Lin if (IS_ERR(imx6_pcie->vpcie)) { 13942170a09fSThierry Reding if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV) 13952170a09fSThierry Reding return PTR_ERR(imx6_pcie->vpcie); 13966e0832faSShawn Lin imx6_pcie->vpcie = NULL; 13976e0832faSShawn Lin } 13986e0832faSShawn Lin 1399d2ce69caSRichard Zhu imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); 1400d2ce69caSRichard Zhu if (IS_ERR(imx6_pcie->vph)) { 1401d2ce69caSRichard Zhu if (PTR_ERR(imx6_pcie->vph) != -ENODEV) 1402d2ce69caSRichard Zhu return PTR_ERR(imx6_pcie->vph); 1403d2ce69caSRichard Zhu imx6_pcie->vph = NULL; 1404d2ce69caSRichard Zhu } 1405d2ce69caSRichard Zhu 14066e0832faSShawn Lin platform_set_drvdata(pdev, imx6_pcie); 14076e0832faSShawn Lin 14083f7cceeaSLeonard Crestez ret = imx6_pcie_attach_pd(dev); 14093f7cceeaSLeonard Crestez if (ret) 14103f7cceeaSLeonard Crestez return ret; 14113f7cceeaSLeonard Crestez 141275c2f26dSRichard Zhu if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { 141375c2f26dSRichard Zhu ret = imx6_add_pcie_ep(imx6_pcie, pdev); 141475c2f26dSRichard Zhu if (ret < 0) 141575c2f26dSRichard Zhu return ret; 141675c2f26dSRichard Zhu } else { 141760f5b73fSRob Herring ret = dw_pcie_host_init(&pci->pp); 14186e0832faSShawn Lin if (ret < 0) 14196e0832faSShawn Lin return ret; 14206e0832faSShawn Lin 142175cb8d20SRichard Zhu if (pci_msi_enabled()) { 1422201a8df8SRob Herring u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); 142375c2f26dSRichard Zhu 1424201a8df8SRob Herring val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); 142575cb8d20SRichard Zhu val |= PCI_MSI_FLAGS_ENABLE; 1426201a8df8SRob Herring dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); 142775cb8d20SRichard Zhu } 142875c2f26dSRichard Zhu } 142975cb8d20SRichard Zhu 14306e0832faSShawn Lin return 0; 14316e0832faSShawn Lin } 14326e0832faSShawn Lin 14336e0832faSShawn Lin static void imx6_pcie_shutdown(struct platform_device *pdev) 14346e0832faSShawn Lin { 14356e0832faSShawn Lin struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); 14366e0832faSShawn Lin 14376e0832faSShawn Lin /* bring down link, so bootloader gets clean state in case of reboot */ 14386e0832faSShawn Lin imx6_pcie_assert_core_reset(imx6_pcie); 14396e0832faSShawn Lin } 14406e0832faSShawn Lin 14416a401858SFrank Li static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"}; 14426a401858SFrank Li static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"}; 14436a401858SFrank Li static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}; 14446a401858SFrank Li static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"}; 14456a401858SFrank Li 1446e8e4d4e9SAndrey Smirnov static const struct imx6_pcie_drvdata drvdata[] = { 1447e8e4d4e9SAndrey Smirnov [IMX6Q] = { 1448e8e4d4e9SAndrey Smirnov .variant = IMX6Q, 14494c458bb3SAndrey Smirnov .flags = IMX6_PCIE_FLAG_IMX6_PHY | 14504c458bb3SAndrey Smirnov IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, 1451075af61cSStefan Agner .dbi_length = 0x200, 14523db1e531SRichard Zhu .gpr = "fsl,imx6q-iomuxc-gpr", 14536a401858SFrank Li .clk_names = imx6q_clks, 14546a401858SFrank Li .clks_cnt = ARRAY_SIZE(imx6q_clks), 1455d99aa8d3SFrank Li .ltssm_off = IOMUXC_GPR12, 1456d99aa8d3SFrank Li .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, 1457f99b121cSFrank Li .mode_off[0] = IOMUXC_GPR12, 1458f99b121cSFrank Li .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 145921ad80b0SFrank Li .init_phy = imx6_pcie_init_phy, 1460e8e4d4e9SAndrey Smirnov }, 1461e8e4d4e9SAndrey Smirnov [IMX6SX] = { 1462e8e4d4e9SAndrey Smirnov .variant = IMX6SX, 14634c458bb3SAndrey Smirnov .flags = IMX6_PCIE_FLAG_IMX6_PHY | 146476d6dc26SAndrey Smirnov IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | 146576d6dc26SAndrey Smirnov IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 14663db1e531SRichard Zhu .gpr = "fsl,imx6q-iomuxc-gpr", 14676a401858SFrank Li .clk_names = imx6sx_clks, 14686a401858SFrank Li .clks_cnt = ARRAY_SIZE(imx6sx_clks), 1469d99aa8d3SFrank Li .ltssm_off = IOMUXC_GPR12, 1470d99aa8d3SFrank Li .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, 1471f99b121cSFrank Li .mode_off[0] = IOMUXC_GPR12, 1472f99b121cSFrank Li .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 147321ad80b0SFrank Li .init_phy = imx6sx_pcie_init_phy, 1474e8e4d4e9SAndrey Smirnov }, 1475e8e4d4e9SAndrey Smirnov [IMX6QP] = { 1476e8e4d4e9SAndrey Smirnov .variant = IMX6QP, 14774c458bb3SAndrey Smirnov .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1478f81dd043SRichard Zhu IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | 1479f81dd043SRichard Zhu IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 14807a289a16SRichard Zhu .dbi_length = 0x200, 14813db1e531SRichard Zhu .gpr = "fsl,imx6q-iomuxc-gpr", 14826a401858SFrank Li .clk_names = imx6q_clks, 14836a401858SFrank Li .clks_cnt = ARRAY_SIZE(imx6q_clks), 1484d99aa8d3SFrank Li .ltssm_off = IOMUXC_GPR12, 1485d99aa8d3SFrank Li .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, 1486f99b121cSFrank Li .mode_off[0] = IOMUXC_GPR12, 1487f99b121cSFrank Li .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 148821ad80b0SFrank Li .init_phy = imx6_pcie_init_phy, 1489e8e4d4e9SAndrey Smirnov }, 1490e8e4d4e9SAndrey Smirnov [IMX7D] = { 1491e8e4d4e9SAndrey Smirnov .variant = IMX7D, 14920c9651c2SFrank Li .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | 14930c9651c2SFrank Li IMX6_PCIE_FLAG_HAS_APP_RESET | 14940c9651c2SFrank Li IMX6_PCIE_FLAG_HAS_PHY_RESET, 14953db1e531SRichard Zhu .gpr = "fsl,imx7d-iomuxc-gpr", 14966a401858SFrank Li .clk_names = imx6q_clks, 14976a401858SFrank Li .clks_cnt = ARRAY_SIZE(imx6q_clks), 1498f99b121cSFrank Li .mode_off[0] = IOMUXC_GPR12, 1499f99b121cSFrank Li .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 150021ad80b0SFrank Li .init_phy = imx7d_pcie_init_phy, 1501e8e4d4e9SAndrey Smirnov }, 15022d8ed461SAndrey Smirnov [IMX8MQ] = { 15032d8ed461SAndrey Smirnov .variant = IMX8MQ, 15040c9651c2SFrank Li .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | 15050c9651c2SFrank Li IMX6_PCIE_FLAG_HAS_PHY_RESET, 15063db1e531SRichard Zhu .gpr = "fsl,imx8mq-iomuxc-gpr", 15076a401858SFrank Li .clk_names = imx8mq_clks, 15086a401858SFrank Li .clks_cnt = ARRAY_SIZE(imx8mq_clks), 1509f99b121cSFrank Li .mode_off[0] = IOMUXC_GPR12, 1510f99b121cSFrank Li .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1511f99b121cSFrank Li .mode_off[1] = IOMUXC_GPR12, 1512f99b121cSFrank Li .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, 151321ad80b0SFrank Li .init_phy = imx8mq_pcie_init_phy, 15142d8ed461SAndrey Smirnov }, 1515178e244cSRichard Zhu [IMX8MM] = { 1516178e244cSRichard Zhu .variant = IMX8MM, 15174e37c2f4SFrank Li .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | 15184e37c2f4SFrank Li IMX6_PCIE_FLAG_HAS_PHYDRV | 15194e37c2f4SFrank Li IMX6_PCIE_FLAG_HAS_APP_RESET, 15203db1e531SRichard Zhu .gpr = "fsl,imx8mm-iomuxc-gpr", 15216a401858SFrank Li .clk_names = imx8mm_clks, 15226a401858SFrank Li .clks_cnt = ARRAY_SIZE(imx8mm_clks), 1523f99b121cSFrank Li .mode_off[0] = IOMUXC_GPR12, 1524f99b121cSFrank Li .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 15253db1e531SRichard Zhu }, 15263db1e531SRichard Zhu [IMX8MP] = { 15273db1e531SRichard Zhu .variant = IMX8MP, 15284e37c2f4SFrank Li .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | 15290c9651c2SFrank Li IMX6_PCIE_FLAG_HAS_PHYDRV | 15300c9651c2SFrank Li IMX6_PCIE_FLAG_HAS_APP_RESET, 15313db1e531SRichard Zhu .gpr = "fsl,imx8mp-iomuxc-gpr", 15326a401858SFrank Li .clk_names = imx8mm_clks, 15336a401858SFrank Li .clks_cnt = ARRAY_SIZE(imx8mm_clks), 1534f99b121cSFrank Li .mode_off[0] = IOMUXC_GPR12, 1535f99b121cSFrank Li .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1536178e244cSRichard Zhu }, 1537f5c04da3SFrank Li [IMX95] = { 1538f5c04da3SFrank Li .variant = IMX95, 1539f5c04da3SFrank Li .flags = IMX6_PCIE_FLAG_HAS_SERDES, 1540f5c04da3SFrank Li .clk_names = imx8mq_clks, 1541f5c04da3SFrank Li .clks_cnt = ARRAY_SIZE(imx8mq_clks), 1542f5c04da3SFrank Li .ltssm_off = IMX95_PE0_GEN_CTRL_3, 1543f5c04da3SFrank Li .ltssm_mask = IMX95_PCIE_LTSSM_EN, 1544f5c04da3SFrank Li .mode_off[0] = IMX95_PE0_GEN_CTRL_1, 1545f5c04da3SFrank Li .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, 1546f5c04da3SFrank Li .init_phy = imx95_pcie_init_phy, 1547f5c04da3SFrank Li }, 1548530ba412SRichard Zhu [IMX8MQ_EP] = { 1549530ba412SRichard Zhu .variant = IMX8MQ_EP, 15500c9651c2SFrank Li .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | 15510c9651c2SFrank Li IMX6_PCIE_FLAG_HAS_PHY_RESET, 1552530ba412SRichard Zhu .mode = DW_PCIE_EP_TYPE, 1553530ba412SRichard Zhu .gpr = "fsl,imx8mq-iomuxc-gpr", 15546a401858SFrank Li .clk_names = imx8mq_clks, 15556a401858SFrank Li .clks_cnt = ARRAY_SIZE(imx8mq_clks), 1556f99b121cSFrank Li .mode_off[0] = IOMUXC_GPR12, 1557f99b121cSFrank Li .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1558f99b121cSFrank Li .mode_off[1] = IOMUXC_GPR12, 1559f99b121cSFrank Li .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, 15600044966cSFrank Li .epc_features = &imx8m_pcie_epc_features, 156121ad80b0SFrank Li .init_phy = imx8mq_pcie_init_phy, 1562530ba412SRichard Zhu }, 1563fb3217e2SRichard Zhu [IMX8MM_EP] = { 1564fb3217e2SRichard Zhu .variant = IMX8MM_EP, 15654e37c2f4SFrank Li .flags = IMX6_PCIE_FLAG_HAS_PHYDRV, 1566fb3217e2SRichard Zhu .mode = DW_PCIE_EP_TYPE, 1567fb3217e2SRichard Zhu .gpr = "fsl,imx8mm-iomuxc-gpr", 15686a401858SFrank Li .clk_names = imx8mm_clks, 15696a401858SFrank Li .clks_cnt = ARRAY_SIZE(imx8mm_clks), 1570f99b121cSFrank Li .mode_off[0] = IOMUXC_GPR12, 1571f99b121cSFrank Li .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 15720044966cSFrank Li .epc_features = &imx8m_pcie_epc_features, 1573fb3217e2SRichard Zhu }, 1574c435669aSRichard Zhu [IMX8MP_EP] = { 1575c435669aSRichard Zhu .variant = IMX8MP_EP, 15764e37c2f4SFrank Li .flags = IMX6_PCIE_FLAG_HAS_PHYDRV, 1577c435669aSRichard Zhu .mode = DW_PCIE_EP_TYPE, 1578c435669aSRichard Zhu .gpr = "fsl,imx8mp-iomuxc-gpr", 15796a401858SFrank Li .clk_names = imx8mm_clks, 15806a401858SFrank Li .clks_cnt = ARRAY_SIZE(imx8mm_clks), 1581f99b121cSFrank Li .mode_off[0] = IOMUXC_GPR12, 1582f99b121cSFrank Li .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 15830044966cSFrank Li .epc_features = &imx8m_pcie_epc_features, 1584c435669aSRichard Zhu }, 1585b7d67c61SFrank Li [IMX95_EP] = { 1586b7d67c61SFrank Li .variant = IMX95_EP, 1587b7d67c61SFrank Li .flags = IMX6_PCIE_FLAG_HAS_SERDES | 1588b7d67c61SFrank Li IMX6_PCIE_FLAG_SUPPORT_64BIT, 1589b7d67c61SFrank Li .clk_names = imx8mq_clks, 1590b7d67c61SFrank Li .clks_cnt = ARRAY_SIZE(imx8mq_clks), 1591b7d67c61SFrank Li .ltssm_off = IMX95_PE0_GEN_CTRL_3, 1592b7d67c61SFrank Li .ltssm_mask = IMX95_PCIE_LTSSM_EN, 1593b7d67c61SFrank Li .mode_off[0] = IMX95_PE0_GEN_CTRL_1, 1594b7d67c61SFrank Li .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, 1595b7d67c61SFrank Li .init_phy = imx95_pcie_init_phy, 1596b7d67c61SFrank Li .epc_features = &imx95_pcie_epc_features, 1597b7d67c61SFrank Li .mode = DW_PCIE_EP_TYPE, 1598b7d67c61SFrank Li }, 1599e8e4d4e9SAndrey Smirnov }; 1600e8e4d4e9SAndrey Smirnov 16016e0832faSShawn Lin static const struct of_device_id imx6_pcie_of_match[] = { 1602e8e4d4e9SAndrey Smirnov { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], }, 1603e8e4d4e9SAndrey Smirnov { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], }, 1604e8e4d4e9SAndrey Smirnov { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, 1605e8e4d4e9SAndrey Smirnov { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], }, 16062d8ed461SAndrey Smirnov { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], }, 1607178e244cSRichard Zhu { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], }, 16083db1e531SRichard Zhu { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], }, 1609f5c04da3SFrank Li { .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], }, 1610530ba412SRichard Zhu { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, 1611fb3217e2SRichard Zhu { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, 1612c435669aSRichard Zhu { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, 1613b7d67c61SFrank Li { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, 16146e0832faSShawn Lin {}, 16156e0832faSShawn Lin }; 16166e0832faSShawn Lin 16176e0832faSShawn Lin static struct platform_driver imx6_pcie_driver = { 16186e0832faSShawn Lin .driver = { 16196e0832faSShawn Lin .name = "imx6q-pcie", 16206e0832faSShawn Lin .of_match_table = imx6_pcie_of_match, 16216e0832faSShawn Lin .suppress_bind_attrs = true, 16220ee2c1f2SLeonard Crestez .pm = &imx6_pcie_pm_ops, 16231b8df7aaSLucas Stach .probe_type = PROBE_PREFER_ASYNCHRONOUS, 16246e0832faSShawn Lin }, 16256e0832faSShawn Lin .probe = imx6_pcie_probe, 16266e0832faSShawn Lin .shutdown = imx6_pcie_shutdown, 16276e0832faSShawn Lin }; 16286e0832faSShawn Lin 1629075af61cSStefan Agner static void imx6_pcie_quirk(struct pci_dev *dev) 1630075af61cSStefan Agner { 1631075af61cSStefan Agner struct pci_bus *bus = dev->bus; 163260b3c27fSSerge Semin struct dw_pcie_rp *pp = bus->sysdata; 1633075af61cSStefan Agner 1634075af61cSStefan Agner /* Bus parent is the PCI bridge, its parent is this platform driver */ 1635075af61cSStefan Agner if (!bus->dev.parent || !bus->dev.parent->parent) 1636075af61cSStefan Agner return; 1637075af61cSStefan Agner 1638075af61cSStefan Agner /* Make sure we only quirk devices associated with this driver */ 1639075af61cSStefan Agner if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver) 1640075af61cSStefan Agner return; 1641075af61cSStefan Agner 164255254938SRob Herring if (pci_is_root_bus(bus)) { 1643075af61cSStefan Agner struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1644075af61cSStefan Agner struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 1645075af61cSStefan Agner 1646075af61cSStefan Agner /* 1647075af61cSStefan Agner * Limit config length to avoid the kernel reading beyond 1648075af61cSStefan Agner * the register set and causing an abort on i.MX 6Quad 1649075af61cSStefan Agner */ 1650075af61cSStefan Agner if (imx6_pcie->drvdata->dbi_length) { 1651075af61cSStefan Agner dev->cfg_size = imx6_pcie->drvdata->dbi_length; 1652075af61cSStefan Agner dev_info(&dev->dev, "Limiting cfg_size to %d\n", 1653075af61cSStefan Agner dev->cfg_size); 1654075af61cSStefan Agner } 1655075af61cSStefan Agner } 1656075af61cSStefan Agner } 1657075af61cSStefan Agner DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd, 1658075af61cSStefan Agner PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk); 1659075af61cSStefan Agner 16606e0832faSShawn Lin static int __init imx6_pcie_init(void) 16616e0832faSShawn Lin { 16622d8ed461SAndrey Smirnov #ifdef CONFIG_ARM 16635f5ac460SH. Nikolaus Schaller struct device_node *np; 16645f5ac460SH. Nikolaus Schaller 16655f5ac460SH. Nikolaus Schaller np = of_find_matching_node(NULL, imx6_pcie_of_match); 16665f5ac460SH. Nikolaus Schaller if (!np) 16675f5ac460SH. Nikolaus Schaller return -ENODEV; 16685f5ac460SH. Nikolaus Schaller of_node_put(np); 16695f5ac460SH. Nikolaus Schaller 16706e0832faSShawn Lin /* 16716e0832faSShawn Lin * Since probe() can be deferred we need to make sure that 16726e0832faSShawn Lin * hook_fault_code is not called after __init memory is freed 16736e0832faSShawn Lin * by kernel and since imx6q_pcie_abort_handler() is a no-op, 16746e0832faSShawn Lin * we can install the handler here without risking it 16756e0832faSShawn Lin * accessing some uninitialized driver state. 16766e0832faSShawn Lin */ 16776e0832faSShawn Lin hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0, 16786e0832faSShawn Lin "external abort on non-linefetch"); 16792d8ed461SAndrey Smirnov #endif 16806e0832faSShawn Lin 16816e0832faSShawn Lin return platform_driver_register(&imx6_pcie_driver); 16826e0832faSShawn Lin } 16836e0832faSShawn Lin device_initcall(imx6_pcie_init); 1684