1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2c94fb639SRandy Dunlapmenu "IRQ chip support" 3c94fb639SRandy Dunlap 4f6e916b8SThomas Petazzoniconfig IRQCHIP 5f6e916b8SThomas Petazzoni def_bool y 6612d5494SHuacai Chen depends on (OF_IRQ || ACPI_GENERIC_GSI) 7f6e916b8SThomas Petazzoni 881243e44SRob Herringconfig ARM_GIC 981243e44SRob Herring bool 10dee23403SMarc Zyngier depends on OF 119a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 120e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1381243e44SRob Herring 149c8edddfSJon Hunterconfig ARM_GIC_PM 159c8edddfSJon Hunter bool 169c8edddfSJon Hunter depends on PM 179c8edddfSJon Hunter select ARM_GIC 189c8edddfSJon Hunter 19a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 20a27d21e0SLinus Walleij int 2170265523SJiangfeng Xiao depends on ARM_GIC 22a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 23a27d21e0SLinus Walleij default 1 24a27d21e0SLinus Walleij 25853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 26853a33ceSSuravee Suthikulpanit bool 273ee80364SArnd Bergmann depends on PCI 283ee80364SArnd Bergmann select ARM_GIC 2974e44454SThomas Gleixner select IRQ_MSI_LIB 303ee80364SArnd Bergmann select PCI_MSI 3196093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 32853a33ceSSuravee Suthikulpanit 3381243e44SRob Herringconfig GIC_NON_BANKED 3481243e44SRob Herring bool 3581243e44SRob Herring 36021f6537SMarc Zyngierconfig ARM_GIC_V3 37021f6537SMarc Zyngier bool 38443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 39e3825ba1SMarc Zyngier select PARTITION_PERCPU 400e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 4135727af2SShanker Donthineni select HAVE_ARM_SMCCC_DISCOVERY 4296093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 43021f6537SMarc Zyngier 4419812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4519812729SMarc Zyngier bool 4613e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4748f71d56SThomas Gleixner select IRQ_MSI_LIB 4829f41139SMarc Zyngier default ARM_GIC_V3 4996093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 5029f41139SMarc Zyngier 517afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 527afe031cSBogdan Purcareata bool 537afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 547afe031cSBogdan Purcareata depends on FSL_MC_BUS 557afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 567afe031cSBogdan Purcareata 57292ec080SUwe Kleine-Königconfig ARM_NVIC 58292ec080SUwe Kleine-König bool 592d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 60292ec080SUwe Kleine-König select GENERIC_IRQ_CHIP 61292ec080SUwe Kleine-König 6244430ec0SRob Herringconfig ARM_VIC 6344430ec0SRob Herring bool 6444430ec0SRob Herring select IRQ_DOMAIN 6544430ec0SRob Herring 6644430ec0SRob Herringconfig ARM_VIC_NR 6744430ec0SRob Herring int 6844430ec0SRob Herring default 4 if ARCH_S5PV210 6944430ec0SRob Herring default 2 7044430ec0SRob Herring depends on ARM_VIC 7144430ec0SRob Herring help 7244430ec0SRob Herring The maximum number of VICs available in the system, for 7344430ec0SRob Herring power management. 7444430ec0SRob Herring 7572e257c6SThomas Gleixnerconfig IRQ_MSI_LIB 7672e257c6SThomas Gleixner bool 7772e257c6SThomas Gleixner 78fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 79fed6d336SThomas Petazzoni bool 80fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 813ee80364SArnd Bergmann select PCI_MSI if PCI 820e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 83fed6d336SThomas Petazzoni 84e6b78f2cSAntoine Tenartconfig ALPINE_MSI 85e6b78f2cSAntoine Tenart bool 863ee80364SArnd Bergmann depends on PCI 873ee80364SArnd Bergmann select PCI_MSI 88e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 89e6b78f2cSAntoine Tenart 901eb77c3bSTalel Shenharconfig AL_FIC 911eb77c3bSTalel Shenhar bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 929869f37aSJean Delvare depends on OF 9335e0cd77SBaoquan He depends on HAS_IOMEM 941eb77c3bSTalel Shenhar select GENERIC_IRQ_CHIP 951eb77c3bSTalel Shenhar select IRQ_DOMAIN 961eb77c3bSTalel Shenhar help 971eb77c3bSTalel Shenhar Support Amazon's Annapurna Labs Fabric Interrupt Controller. 981eb77c3bSTalel Shenhar 99b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 100b1479ebbSBoris BREZILLON bool 101b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 102b1479ebbSBoris BREZILLON select IRQ_DOMAIN 103b1479ebbSBoris BREZILLON select SPARSE_IRQ 104b1479ebbSBoris BREZILLON 105b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 106b1479ebbSBoris BREZILLON bool 107b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 108b1479ebbSBoris BREZILLON select IRQ_DOMAIN 109b1479ebbSBoris BREZILLON select SPARSE_IRQ 110b1479ebbSBoris BREZILLON 1110509cfdeSRalf Baechleconfig I8259 1120509cfdeSRalf Baechle bool 1130509cfdeSRalf Baechle select IRQ_DOMAIN 1140509cfdeSRalf Baechle 11532c6c054SStanimir Varbanovconfig BCM2712_MIP 11632c6c054SStanimir Varbanov tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 1179b3ae50cSPeter Robinson depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 1189b3ae50cSPeter Robinson default m if ARCH_BRCMSTB || ARCH_BCM2835 11932c6c054SStanimir Varbanov depends on ARM_GIC 12032c6c054SStanimir Varbanov select GENERIC_IRQ_CHIP 12132c6c054SStanimir Varbanov select IRQ_DOMAIN_HIERARCHY 12232c6c054SStanimir Varbanov select GENERIC_MSI_IRQ 12332c6c054SStanimir Varbanov select IRQ_MSI_LIB 12432c6c054SStanimir Varbanov help 12532c6c054SStanimir Varbanov Enable support for the Broadcom BCM2712 MSI-X target peripheral 12632c6c054SStanimir Varbanov (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 12732c6c054SStanimir Varbanov Raspberry Pi 5. 12832c6c054SStanimir Varbanov 12932c6c054SStanimir Varbanov If unsure say n. 13032c6c054SStanimir Varbanov 131c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 132c7c42ec2SSimon Arlott bool 133c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 134c7c42ec2SSimon Arlott select IRQ_DOMAIN 1350e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 136c7c42ec2SSimon Arlott 1375f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 138c057c799SFlorian Fainelli tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 139c057c799SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 140c057c799SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 1415f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1425f7f0317SKevin Cernekee select IRQ_DOMAIN 1430e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1445f7f0317SKevin Cernekee 145a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 1463ac268d5SFlorian Fainelli tristate "Broadcom STB 7120-style L2 interrupt controller driver" 1473ac268d5SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 1483ac268d5SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 149a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 150a4fcbb86SKevin Cernekee select IRQ_DOMAIN 151a4fcbb86SKevin Cernekee 1527f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 15351d9db5cSFlorian Fainelli tristate "Broadcom STB generic L2 interrupt controller driver" 15451d9db5cSFlorian Fainelli depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 15551d9db5cSFlorian Fainelli default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 1567f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1577f646e92SFlorian Fainelli select IRQ_DOMAIN 1587f646e92SFlorian Fainelli 1590fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1600fc3d74cSBartosz Golaszewski bool 1610fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1620fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1630fc3d74cSBartosz Golaszewski 164350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 165be5e5f3aSThomas Gleixner bool 166e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 16754a38440SZhen Lei select IRQ_DOMAIN_HIERARCHY 168350d71b9SSebastian Hesselbarth 169*1902a59cSCaleb James DeLisleconfig ECONET_EN751221_INTC 170*1902a59cSCaleb James DeLisle bool 171*1902a59cSCaleb James DeLisle select GENERIC_IRQ_CHIP 172*1902a59cSCaleb James DeLisle select IRQ_DOMAIN 173*1902a59cSCaleb James DeLisle 1746ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1756ee532e2SLinus Walleij bool 1766ee532e2SLinus Walleij select IRQ_DOMAIN 1776ee532e2SLinus Walleij select SPARSE_IRQ 1786ee532e2SLinus Walleij 1799a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1809a7c4abdSMaJun bool 1819a7c4abdSMaJun select ARM_GIC_V3 1829a7c4abdSMaJun select ARM_GIC_V3_ITS 1839a7c4abdSMaJun 184b6ef9161SJames Hoganconfig IMGPDC_IRQ 185b6ef9161SJames Hogan bool 186b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 187b6ef9161SJames Hogan select IRQ_DOMAIN 188b6ef9161SJames Hogan 1895b978c10SLinus Walleijconfig IXP4XX_IRQ 1905b978c10SLinus Walleij bool 1915b978c10SLinus Walleij select IRQ_DOMAIN 1925b978c10SLinus Walleij select SPARSE_IRQ 1935b978c10SLinus Walleij 1943e3a7b35SHerve Codinaconfig LAN966X_OIC 1953e3a7b35SHerve Codina tristate "Microchip LAN966x OIC Support" 196e06c9e36SGeert Uytterhoeven depends on MCHP_LAN966X_PCI || COMPILE_TEST 1973e3a7b35SHerve Codina select GENERIC_IRQ_CHIP 1983e3a7b35SHerve Codina select IRQ_DOMAIN 1993e3a7b35SHerve Codina help 2003e3a7b35SHerve Codina Enable support for the LAN966x Outbound Interrupt Controller. 2013e3a7b35SHerve Codina This controller is present on the Microchip LAN966x PCI device and 2023e3a7b35SHerve Codina maps the internal interrupts sources to PCIe interrupt. 2033e3a7b35SHerve Codina 2043e3a7b35SHerve Codina To compile this driver as a module, choose M here: the module 2053e3a7b35SHerve Codina will be called irq-lan966x-oic. 2063e3a7b35SHerve Codina 207da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 208da0abe1aSRichard Fitzgerald tristate 209da0abe1aSRichard Fitzgerald 21067e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 21167e38cf2SRalf Baechle bool 21267e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 2130f5209feSSamuel Holland select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 21467e38cf2SRalf Baechle select IRQ_DOMAIN 2150e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 21667e38cf2SRalf Baechle 217afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 218afc98d90SAlexander Shiyan bool 219afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 220afc98d90SAlexander Shiyan select IRQ_DOMAIN 221afc98d90SAlexander Shiyan select SPARSE_IRQ 222afc98d90SAlexander Shiyan default y 223afc98d90SAlexander Shiyan 2249b54470aSStafford Horneconfig OMPIC 2259b54470aSStafford Horne bool 2269b54470aSStafford Horne 2274db8e6d2SStefan Kristianssonconfig OR1K_PIC 2284db8e6d2SStefan Kristiansson bool 2294db8e6d2SStefan Kristiansson select IRQ_DOMAIN 2304db8e6d2SStefan Kristiansson 2318598066cSFelipe Balbiconfig OMAP_IRQCHIP 2328598066cSFelipe Balbi bool 2338598066cSFelipe Balbi select GENERIC_IRQ_CHIP 2348598066cSFelipe Balbi select IRQ_DOMAIN 2358598066cSFelipe Balbi 2369dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 2379dbd90f1SSebastian Hesselbarth bool 2389dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 2399dbd90f1SSebastian Hesselbarth 240aaa8666aSCristian Birsanconfig PIC32_EVIC 241aaa8666aSCristian Birsan bool 242aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 243aaa8666aSCristian Birsan select IRQ_DOMAIN 244aaa8666aSCristian Birsan 245981b58f6SRich Felkerconfig JCORE_AIC 2463602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2473602ffdeSRich Felker depends on OF 248981b58f6SRich Felker select IRQ_DOMAIN 249981b58f6SRich Felker help 250981b58f6SRich Felker Support for the J-Core integrated AIC. 251981b58f6SRich Felker 252d852e62aSManivannan Sadhasivamconfig RDA_INTC 253d852e62aSManivannan Sadhasivam bool 254d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 255d852e62aSManivannan Sadhasivam 25644358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 25702d7e041SGeert Uytterhoeven bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 25844358048SMagnus Damm select IRQ_DOMAIN 25902d7e041SGeert Uytterhoeven help 26002d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 26102d7e041SGeert Uytterhoeven interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 26244358048SMagnus Damm 263fbc83b7fSMagnus Dammconfig RENESAS_IRQC 26472d44c0cSLad Prabhakar bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 26599c221dfSMagnus Damm select GENERIC_IRQ_CHIP 266fbc83b7fSMagnus Damm select IRQ_DOMAIN 26702d7e041SGeert Uytterhoeven help 26802d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 26972d44c0cSLad Prabhakar devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 270fbc83b7fSMagnus Damm 271a644ccb8SGeert Uytterhoevenconfig RENESAS_RZA1_IRQC 27202d7e041SGeert Uytterhoeven bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 273a644ccb8SGeert Uytterhoeven select IRQ_DOMAIN_HIERARCHY 27402d7e041SGeert Uytterhoeven help 27502d7e041SGeert Uytterhoeven Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 27602d7e041SGeert Uytterhoeven to 8 external interrupts with configurable sense select. 277a644ccb8SGeert Uytterhoeven 2783fed0955SLad Prabhakarconfig RENESAS_RZG2L_IRQC 2793fed0955SLad Prabhakar bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 2803fed0955SLad Prabhakar select GENERIC_IRQ_CHIP 2813fed0955SLad Prabhakar select IRQ_DOMAIN_HIERARCHY 2823fed0955SLad Prabhakar help 2833fed0955SLad Prabhakar Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 2843fed0955SLad Prabhakar for external devices. 2853fed0955SLad Prabhakar 2860d7605e7SFabrizio Castroconfig RENESAS_RZV2H_ICU 2870d7605e7SFabrizio Castro bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 2880d7605e7SFabrizio Castro select GENERIC_IRQ_CHIP 2890d7605e7SFabrizio Castro select IRQ_DOMAIN_HIERARCHY 2900d7605e7SFabrizio Castro help 2910d7605e7SFabrizio Castro Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 2920d7605e7SFabrizio Castro 29303ac990eSMichael Walleconfig SL28CPLD_INTC 29403ac990eSMichael Walle bool "Kontron sl28cpld IRQ controller" 29503ac990eSMichael Walle depends on MFD_SL28CPLD=y || COMPILE_TEST 29603ac990eSMichael Walle select REGMAP_IRQ 29703ac990eSMichael Walle help 29803ac990eSMichael Walle Interrupt controller driver for the board management controller 29903ac990eSMichael Walle found on the Kontron sl28 CPLD. 30003ac990eSMichael Walle 30107088484SLee Jonesconfig ST_IRQCHIP 30207088484SLee Jones bool 30307088484SLee Jones select REGMAP 30407088484SLee Jones select MFD_SYSCON 30507088484SLee Jones help 30607088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 30707088484SLee Jones 308d421fd6dSSamuel Hollandconfig SUN4I_INTC 309d421fd6dSSamuel Holland bool 310d421fd6dSSamuel Holland 311d421fd6dSSamuel Hollandconfig SUN6I_R_INTC 312d421fd6dSSamuel Holland bool 313d421fd6dSSamuel Holland select IRQ_DOMAIN_HIERARCHY 314d421fd6dSSamuel Holland select IRQ_FASTEOI_HIERARCHY_HANDLERS 315d421fd6dSSamuel Holland 316d421fd6dSSamuel Hollandconfig SUNXI_NMI_INTC 317d421fd6dSSamuel Holland bool 318d421fd6dSSamuel Holland select GENERIC_IRQ_CHIP 319d421fd6dSSamuel Holland 320b06eb017SChristian Ruppertconfig TB10X_IRQC 321b06eb017SChristian Ruppert bool 322b06eb017SChristian Ruppert select IRQ_DOMAIN 323b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 324b06eb017SChristian Ruppert 325d01f8633SDamien Riegelconfig TS4800_IRQ 326d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 327d01f8633SDamien Riegel select IRQ_DOMAIN 3280df337cfSRichard Weinberger depends on HAS_IOMEM 329d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 330d01f8633SDamien Riegel help 331d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 332d01f8633SDamien Riegel 3332389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 3342389d501SLinus Walleij bool 3352389d501SLinus Walleij select IRQ_DOMAIN 3362389d501SLinus Walleij 3372389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 3382389d501SLinus Walleij int 3392389d501SLinus Walleij default 4 3402389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 34126a8e96aSMax Filippov 34226a8e96aSMax Filippovconfig XTENSA_MX 34326a8e96aSMax Filippov bool 34426a8e96aSMax Filippov select IRQ_DOMAIN 3450e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 34696ca848eSSricharan R 3470547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 348debf69cfSRobert Hancock bool "Xilinx Interrupt Controller IP" 349fd31000dSJamie Iles depends on OF_ADDRESS 3500547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 351debf69cfSRobert Hancock help 352debf69cfSRobert Hancock Support for the Xilinx Interrupt Controller IP core. 353debf69cfSRobert Hancock This is used as a primary controller with MicroBlaze and can also 354debf69cfSRobert Hancock be used as a secondary chained controller on other platforms. 3550547dc78SZubair Lutfullah Kakakhel 35696ca848eSSricharan Rconfig IRQ_CROSSBAR 35796ca848eSSricharan R bool 35896ca848eSSricharan R help 359f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 36096ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 36196ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 36296ca848eSSricharan R routed to one of the free irqchip interrupt lines. 36389323f8cSGrygorii Strashko 36489323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 36589323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 36689323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 36789323f8cSGrygorii Strashko help 36889323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 36989323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 3708a19b8f1SAndrew Bresticker 3718a19b8f1SAndrew Brestickerconfig MIPS_GIC 3728a19b8f1SAndrew Bresticker bool 3730053892fSNathan Chancellor select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 3748190cc57SSamuel Holland select GENERIC_IRQ_IPI if SMP 3758190cc57SSamuel Holland select IRQ_DOMAIN_HIERARCHY 3768a19b8f1SAndrew Bresticker select MIPS_CM 3778a764482SYoshinori Sato 37844e08e70SPaul Burtonconfig INGENIC_IRQ 37944e08e70SPaul Burton bool 38044e08e70SPaul Burton depends on MACH_INGENIC 38144e08e70SPaul Burton default y 38278c10e55SLinus Torvalds 3839536eba0SPaul Cercueilconfig INGENIC_TCU_IRQ 3849536eba0SPaul Cercueil bool "Ingenic JZ47xx TCU interrupt controller" 3859536eba0SPaul Cercueil default MACH_INGENIC 3869536eba0SPaul Cercueil depends on MIPS || COMPILE_TEST 3879536eba0SPaul Cercueil select MFD_SYSCON 3888084499bSYueHaibing select GENERIC_IRQ_CHIP 3899536eba0SPaul Cercueil help 3909536eba0SPaul Cercueil Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 3919536eba0SPaul Cercueil JZ47xx SoCs. 3929536eba0SPaul Cercueil 3939536eba0SPaul Cercueil If unsure, say N. 3949536eba0SPaul Cercueil 395e324c4dcSShenwei Wangconfig IMX_GPCV2 396e324c4dcSShenwei Wang bool 397e324c4dcSShenwei Wang select IRQ_DOMAIN 398e324c4dcSShenwei Wang help 399e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 4007e4ac676SOleksij Rempel 4017e4ac676SOleksij Rempelconfig IRQ_MXS 4027e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 4037e4ac676SOleksij Rempel select IRQ_DOMAIN 4047e4ac676SOleksij Rempel select STMP_DEVICE 405c27f29bbSThomas Petazzoni 40619d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 40719d99164SAlexandre Belloni bool 40819d99164SAlexandre Belloni select IRQ_DOMAIN 40919d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 41019d99164SAlexandre Belloni 411a68a63cbSThomas Petazzoniconfig MVEBU_GICP 412cdb23872SThomas Gleixner select IRQ_MSI_LIB 413a68a63cbSThomas Petazzoni bool 414a68a63cbSThomas Petazzoni 415e0de91a9SThomas Petazzoniconfig MVEBU_ICU 416e0de91a9SThomas Petazzoni bool 417e0de91a9SThomas Petazzoni 418c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 419c27f29bbSThomas Petazzoni bool 420e0b99c4cSThomas Gleixner select IRQ_MSI_LIB 42113e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4229e2c986cSMarc Zyngier 423a109893bSThomas Petazzoniconfig MVEBU_PIC 424a109893bSThomas Petazzoni bool 425a109893bSThomas Petazzoni 42661ce8d8dSMiquel Raynalconfig MVEBU_SEI 42761ce8d8dSMiquel Raynal bool 42861ce8d8dSMiquel Raynal 4290dcd9f87SRasmus Villemoesconfig LS_EXTIRQ 4300dcd9f87SRasmus Villemoes def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 4310dcd9f87SRasmus Villemoes select MFD_SYSCON 4320dcd9f87SRasmus Villemoes 433b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 434b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 43596093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 4369c1a7bfcSLukas Bulwahn depends on PCI_MSI 437b8f3ebe6SMinghuan Lian 4389e2c986cSMarc Zyngierconfig PARTITION_PERCPU 4399e2c986cSMarc Zyngier bool 4400efacbbaSLinus Torvalds 441b20cf2dcSAntonio Borneoconfig STM32MP_EXTI 4420be58e05SAntonio Borneo tristate "STM32MP extended interrupts and event controller" 4430be58e05SAntonio Borneo depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 4449151299eSGeert Uytterhoeven default ARCH_STM32 && !ARM_SINGLE_ARMV7M 4450be58e05SAntonio Borneo select IRQ_DOMAIN_HIERARCHY 446350755e2SAntonio Borneo select GENERIC_IRQ_CHIP 4470be58e05SAntonio Borneo help 4480be58e05SAntonio Borneo Support STM32MP EXTI (extended interrupts and event) controller. 449b20cf2dcSAntonio Borneo 450e0720416SAlexandre TORGUEconfig STM32_EXTI 451e0720416SAlexandre TORGUE bool 452e0720416SAlexandre TORGUE select IRQ_DOMAIN 4530e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 454f20cc9b0SAgustin Vega-Frias 455f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 456f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 457f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 458f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 459f20cc9b0SAgustin Vega-Frias help 460f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 461f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 4625ed34d3aSMasahiro Yamada 4635ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 4645ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 4655ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 4665ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 4675ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 4685ed34d3aSMasahiro Yamada help 4695ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 470c94fb639SRandy Dunlap 471215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 472a947aa00SNeil Armstrong tristate "Meson GPIO Interrupt Multiplexer" 473a947aa00SNeil Armstrong depends on ARCH_MESON || COMPILE_TEST 474a947aa00SNeil Armstrong default ARCH_MESON 475215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 476215f4cc0SJerome Brunet help 477215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 478215f4cc0SJerome Brunet 4794235ff50SMiodrag Dinicconfig GOLDFISH_PIC 4804235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 4814235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 482969ac78dSRandy Dunlap select GENERIC_IRQ_CHIP 4834235ff50SMiodrag Dinic select IRQ_DOMAIN 4844235ff50SMiodrag Dinic help 4854235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 4864235ff50SMiodrag Dinic for Goldfish based virtual platforms. 4874235ff50SMiodrag Dinic 488f55c73aeSArchana Sathyakumarconfig QCOM_PDC 4894acd8a4bSSaravana Kannan tristate "QCOM PDC" 490f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 491f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 492f55c73aeSArchana Sathyakumar help 493f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 494f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 495f55c73aeSArchana Sathyakumar 496a6199bb5SShawn Guoconfig QCOM_MPM 497a6199bb5SShawn Guo tristate "QCOM MPM" 498a6199bb5SShawn Guo depends on ARCH_QCOM 499fa4dcc88SYueHaibing depends on MAILBOX 500a6199bb5SShawn Guo select IRQ_DOMAIN_HIERARCHY 501a6199bb5SShawn Guo help 502a6199bb5SShawn Guo MSM Power Manager driver to manage and configure wakeup 503a6199bb5SShawn Guo IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 504a6199bb5SShawn Guo 505d8a5f5f7SGuo Renconfig CSKY_MPINTC 506be1abc5bSGuo Ren bool 507d8a5f5f7SGuo Ren depends on CSKY 508d8a5f5f7SGuo Ren help 509d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 510d8a5f5f7SGuo Ren for C-SKY SMP system. 511656b42deSRandy Dunlap In fact it's not mmio map in hardware and it uses ld/st to visit the 512d8a5f5f7SGuo Ren controller's register inside CPU. 513d8a5f5f7SGuo Ren 514edff1b48SGuo Renconfig CSKY_APB_INTC 515edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 516edff1b48SGuo Ren depends on CSKY 517edff1b48SGuo Ren help 518edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 519656b42deSRandy Dunlap by C-SKY single core SOC system. It uses mmio map apb-bus to visit 520edff1b48SGuo Ren the controller's register. 521edff1b48SGuo Ren 5220136afa0SLucas Stachconfig IMX_IRQSTEER 5230136afa0SLucas Stach bool "i.MX IRQSTEER support" 5240136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 5250136afa0SLucas Stach default ARCH_MXC 5260136afa0SLucas Stach select IRQ_DOMAIN 5270136afa0SLucas Stach help 5280136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 5290136afa0SLucas Stach 5302fbb1396SJoakim Zhangconfig IMX_INTMUX 531a890caebSGeert Uytterhoeven bool "i.MX INTMUX support" if COMPILE_TEST 532a890caebSGeert Uytterhoeven default y if ARCH_MXC 5332fbb1396SJoakim Zhang select IRQ_DOMAIN 5342fbb1396SJoakim Zhang help 5352fbb1396SJoakim Zhang Support for the i.MX INTMUX interrupt multiplexer. 5362fbb1396SJoakim Zhang 53770afdab9SFrank Liconfig IMX_MU_MSI 53870afdab9SFrank Li tristate "i.MX MU used as MSI controller" 53970afdab9SFrank Li depends on OF && HAS_IOMEM 5406c9f7434SGeert Uytterhoeven depends on ARCH_MXC || COMPILE_TEST 54170afdab9SFrank Li default m if ARCH_MXC 54270afdab9SFrank Li select IRQ_DOMAIN 54370afdab9SFrank Li select IRQ_DOMAIN_HIERARCHY 54413e7accbSThomas Gleixner select GENERIC_MSI_IRQ 5457b2f8aa0SThomas Gleixner select IRQ_MSI_LIB 54670afdab9SFrank Li help 5476c9f7434SGeert Uytterhoeven Provide a driver for the i.MX Messaging Unit block used as a 5486c9f7434SGeert Uytterhoeven CPU-to-CPU MSI controller. This requires a specially crafted DT 5496c9f7434SGeert Uytterhoeven to make use of this driver. 55070afdab9SFrank Li 55170afdab9SFrank Li If unsure, say N 55270afdab9SFrank Li 5539e543e22SJiaxun Yangconfig LS1X_IRQ 5549e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 5559e543e22SJiaxun Yang depends on MACH_LOONGSON32 5569e543e22SJiaxun Yang default y 5579e543e22SJiaxun Yang select IRQ_DOMAIN 5589e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 5599e543e22SJiaxun Yang help 5609e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 5619e543e22SJiaxun Yang 562cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 5632d95ffaeSNicolas Frayer tristate "TI SCI INTR Interrupt Controller" 564cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 5652d95ffaeSNicolas Frayer depends on ARCH_K3 || COMPILE_TEST 566cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 567cd844b07SLokesh Vutla help 568cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 569cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 570cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 571cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 572cd844b07SLokesh Vutla 5739f1463b8SLokesh Vutlaconfig TI_SCI_INTA_IRQCHIP 574b8b26ae3SNicolas Frayer tristate "TI SCI INTA Interrupt Controller" 5759f1463b8SLokesh Vutla depends on TI_SCI_PROTOCOL 576b8b26ae3SNicolas Frayer depends on ARCH_K3 || (COMPILE_TEST && ARM64) 5779f1463b8SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 578f011df61SLokesh Vutla select TI_SCI_INTA_MSI_DOMAIN 5799f1463b8SLokesh Vutla help 5809f1463b8SLokesh Vutla This enables the irqchip driver support for K3 Interrupt aggregator 5819f1463b8SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 5829f1463b8SLokesh Vutla If you wish to use interrupt aggregator irq resources managed by the 5839f1463b8SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 5849f1463b8SLokesh Vutla 58504e2d1e0SGrzegorz Jaszczykconfig TI_PRUSS_INTC 586b8e594faSSuman Anna tristate 587b8e594faSSuman Anna depends on TI_PRUSS 588b8e594faSSuman Anna default TI_PRUSS 58904e2d1e0SGrzegorz Jaszczyk select IRQ_DOMAIN 59004e2d1e0SGrzegorz Jaszczyk help 59104e2d1e0SGrzegorz Jaszczyk This enables support for the PRU-ICSS Local Interrupt Controller 59204e2d1e0SGrzegorz Jaszczyk present within a PRU-ICSS subsystem present on various TI SoCs. 59304e2d1e0SGrzegorz Jaszczyk The PRUSS INTC enables various interrupts to be routed to multiple 59404e2d1e0SGrzegorz Jaszczyk different processors within the SoC. 59504e2d1e0SGrzegorz Jaszczyk 5966b7ce892SAnup Patelconfig RISCV_INTC 597d8fb1307SConor Dooley bool 5986b7ce892SAnup Patel depends on RISCV 599832f15f4SAnup Patel select IRQ_DOMAIN_HIERARCHY 6006b7ce892SAnup Patel 6012333df5aSAnup Patelconfig RISCV_APLIC 6022333df5aSAnup Patel bool 6032333df5aSAnup Patel depends on RISCV 6042333df5aSAnup Patel select IRQ_DOMAIN_HIERARCHY 6052333df5aSAnup Patel 606ca8df97fSAnup Patelconfig RISCV_APLIC_MSI 607ca8df97fSAnup Patel bool 608ca8df97fSAnup Patel depends on RISCV_APLIC 609ca8df97fSAnup Patel select GENERIC_MSI_IRQ 610ca8df97fSAnup Patel default RISCV_APLIC 611ca8df97fSAnup Patel 61221a8f8a0SAnup Patelconfig RISCV_IMSIC 61321a8f8a0SAnup Patel bool 61421a8f8a0SAnup Patel depends on RISCV 61521a8f8a0SAnup Patel select IRQ_DOMAIN_HIERARCHY 61621a8f8a0SAnup Patel select GENERIC_IRQ_MATRIX_ALLOCATOR 61721a8f8a0SAnup Patel select GENERIC_MSI_IRQ 618fe35eceeSThomas Gleixner select IRQ_MSI_LIB 6195c5a71d0SAnup Patel 6208237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 621fdb1742aSConor Dooley bool 6228237f8bcSChristoph Hellwig depends on RISCV 623466008f9SYash Shah select IRQ_DOMAIN_HIERARCHY 624de078949SSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 62501493855SJonathan Neuschäfer 626e4e53503SChanghuang Liangconfig STARFIVE_JH8100_INTC 627e4e53503SChanghuang Liang bool "StarFive JH8100 External Interrupt Controller" 628e4e53503SChanghuang Liang depends on ARCH_STARFIVE || COMPILE_TEST 629e4e53503SChanghuang Liang default ARCH_STARFIVE 630e4e53503SChanghuang Liang select IRQ_DOMAIN_HIERARCHY 631e4e53503SChanghuang Liang help 632e4e53503SChanghuang Liang This enables support for the INTC chip found in StarFive JH8100 633e4e53503SChanghuang Liang SoC. 634e4e53503SChanghuang Liang 635e4e53503SChanghuang Liang If you don't know what to do here, say Y. 636e4e53503SChanghuang Liang 63725caea95SInochi Amaotoconfig THEAD_C900_ACLINT_SSWI 63825caea95SInochi Amaoto bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller" 63925caea95SInochi Amaoto depends on RISCV 64025caea95SInochi Amaoto depends on SMP 64125caea95SInochi Amaoto select IRQ_DOMAIN_HIERARCHY 64225caea95SInochi Amaoto select GENERIC_IRQ_IPI_MUX 64325caea95SInochi Amaoto help 64425caea95SInochi Amaoto This enables support for T-HEAD specific ACLINT SSWI device 64525caea95SInochi Amaoto support. 64625caea95SInochi Amaoto 64725caea95SInochi Amaoto If you don't know what to do here, say Y. 64825caea95SInochi Amaoto 649b74416dbSHyunki Kooconfig EXYNOS_IRQ_COMBINER 650b74416dbSHyunki Koo bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 651b74416dbSHyunki Koo depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 652b74416dbSHyunki Koo help 653b74416dbSHyunki Koo Say yes here to add support for the IRQ combiner devices embedded 654b74416dbSHyunki Koo in Samsung Exynos chips. 655b74416dbSHyunki Koo 656b2d3e335SHuacai Chenconfig IRQ_LOONGARCH_CPU 657b2d3e335SHuacai Chen bool 658b2d3e335SHuacai Chen select GENERIC_IRQ_CHIP 659b2d3e335SHuacai Chen select IRQ_DOMAIN 66042a7d887STiezhu Yang select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 66170f7b6c0SHuacai Chen select LOONGSON_HTVEC 6628d5356f9SHuacai Chen select LOONGSON_LIOINTC 6638d5356f9SHuacai Chen select LOONGSON_EIOINTC 6648d5356f9SHuacai Chen select LOONGSON_PCH_PIC 6658d5356f9SHuacai Chen select LOONGSON_PCH_MSI 6668d5356f9SHuacai Chen select LOONGSON_PCH_LPC 667b2d3e335SHuacai Chen help 668b2d3e335SHuacai Chen Support for the LoongArch CPU Interrupt Controller. For details of 669b2d3e335SHuacai Chen irq chip hierarchy on LoongArch platforms please read the document 67051712e49SCosta Shulyupin Documentation/arch/loongarch/irq-chip-model.rst. 671b2d3e335SHuacai Chen 672dbb15226SJiaxun Yangconfig LOONGSON_LIOINTC 673dbb15226SJiaxun Yang bool "Loongson Local I/O Interrupt Controller" 674dbb15226SJiaxun Yang depends on MACH_LOONGSON64 675dbb15226SJiaxun Yang default y 676dbb15226SJiaxun Yang select IRQ_DOMAIN 677dbb15226SJiaxun Yang select GENERIC_IRQ_CHIP 678dbb15226SJiaxun Yang help 679dbb15226SJiaxun Yang Support for the Loongson Local I/O Interrupt Controller. 680dbb15226SJiaxun Yang 681dd281e1aSHuacai Chenconfig LOONGSON_EIOINTC 682dd281e1aSHuacai Chen bool "Loongson Extend I/O Interrupt Controller" 683dd281e1aSHuacai Chen depends on LOONGARCH 684dd281e1aSHuacai Chen depends on MACH_LOONGSON64 685dd281e1aSHuacai Chen default MACH_LOONGSON64 686dd281e1aSHuacai Chen select IRQ_DOMAIN_HIERARCHY 687dd281e1aSHuacai Chen select GENERIC_IRQ_CHIP 688dd281e1aSHuacai Chen help 689dd281e1aSHuacai Chen Support for the Loongson3 Extend I/O Interrupt Vector Controller. 690dd281e1aSHuacai Chen 691a93f1d90SJiaxun Yangconfig LOONGSON_HTPIC 692a93f1d90SJiaxun Yang bool "Loongson3 HyperTransport PIC Controller" 693987a3e03SHuacai Chen depends on MACH_LOONGSON64 && MIPS 694a93f1d90SJiaxun Yang default y 695a93f1d90SJiaxun Yang select IRQ_DOMAIN 696a93f1d90SJiaxun Yang select GENERIC_IRQ_CHIP 697a93f1d90SJiaxun Yang help 698a93f1d90SJiaxun Yang Support for the Loongson-3 HyperTransport PIC Controller. 699a93f1d90SJiaxun Yang 700818e915fSJiaxun Yangconfig LOONGSON_HTVEC 701987a3e03SHuacai Chen bool "Loongson HyperTransport Interrupt Vector Controller" 702d77aeb5dSIngo Molnar depends on MACH_LOONGSON64 703818e915fSJiaxun Yang default MACH_LOONGSON64 704818e915fSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 705818e915fSJiaxun Yang help 706987a3e03SHuacai Chen Support for the Loongson HyperTransport Interrupt Vector Controller. 707818e915fSJiaxun Yang 708ef8c01ebSJiaxun Yangconfig LOONGSON_PCH_PIC 709ef8c01ebSJiaxun Yang bool "Loongson PCH PIC Controller" 710bcdd75c5SHuacai Chen depends on MACH_LOONGSON64 711ef8c01ebSJiaxun Yang default MACH_LOONGSON64 712ef8c01ebSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 713ef8c01ebSJiaxun Yang select IRQ_FASTEOI_HIERARCHY_HANDLERS 714ef8c01ebSJiaxun Yang help 715ef8c01ebSJiaxun Yang Support for the Loongson PCH PIC Controller. 716ef8c01ebSJiaxun Yang 717632dcc2cSJiaxun Yangconfig LOONGSON_PCH_MSI 718a23df9a4SJiaxun Yang bool "Loongson PCH MSI Controller" 71902308732SHuacai Chen depends on MACH_LOONGSON64 720632dcc2cSJiaxun Yang depends on PCI 721632dcc2cSJiaxun Yang default MACH_LOONGSON64 722632dcc2cSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 7230b3af759SHuacai Chen select IRQ_MSI_LIB 724632dcc2cSJiaxun Yang select PCI_MSI 725632dcc2cSJiaxun Yang help 726632dcc2cSJiaxun Yang Support for the Loongson PCH MSI Controller. 727632dcc2cSJiaxun Yang 728ee73f14eSHuacai Chenconfig LOONGSON_PCH_LPC 729ee73f14eSHuacai Chen bool "Loongson PCH LPC Controller" 730e7ccba77SJianmin Lv depends on LOONGARCH 731ee73f14eSHuacai Chen depends on MACH_LOONGSON64 732e7ccba77SJianmin Lv default MACH_LOONGSON64 733ee73f14eSHuacai Chen select IRQ_DOMAIN_HIERARCHY 734ee73f14eSHuacai Chen help 735ee73f14eSHuacai Chen Support for the Loongson PCH LPC Controller. 736ee73f14eSHuacai Chen 737ad4c938cSMark-PK Tsaiconfig MST_IRQ 738ad4c938cSMark-PK Tsai bool "MStar Interrupt Controller" 73961b0648dSGeert Uytterhoeven depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 740ad4c938cSMark-PK Tsai default ARCH_MEDIATEK 741ad4c938cSMark-PK Tsai select IRQ_DOMAIN 742ad4c938cSMark-PK Tsai select IRQ_DOMAIN_HIERARCHY 743ad4c938cSMark-PK Tsai help 744ad4c938cSMark-PK Tsai Support MStar Interrupt Controller. 745ad4c938cSMark-PK Tsai 746fead4dd4SJonathan Neuschäferconfig WPCM450_AIC 747fead4dd4SJonathan Neuschäfer bool "Nuvoton WPCM450 Advanced Interrupt Controller" 74894bc9420SMarc Zyngier depends on ARCH_WPCM450 749fead4dd4SJonathan Neuschäfer help 750fead4dd4SJonathan Neuschäfer Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 751fead4dd4SJonathan Neuschäfer 752529ea368SThomas Bogendoerferconfig IRQ_IDT3243X 753529ea368SThomas Bogendoerfer bool 754529ea368SThomas Bogendoerfer select GENERIC_IRQ_CHIP 755529ea368SThomas Bogendoerfer select IRQ_DOMAIN 756529ea368SThomas Bogendoerfer 75776cde263SHector Martinconfig APPLE_AIC 75876cde263SHector Martin bool "Apple Interrupt Controller (AIC)" 75976cde263SHector Martin depends on ARM64 7605b44955dSGeert Uytterhoeven depends on ARCH_APPLE || COMPILE_TEST 761c19f8971SMarc Zyngier select GENERIC_IRQ_IPI_MUX 76276cde263SHector Martin help 76376cde263SHector Martin Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 76476cde263SHector Martin such as the M1. 76576cde263SHector Martin 76600fa3461SClaudiu Bezneaconfig MCHP_EIC 76700fa3461SClaudiu Beznea bool "Microchip External Interrupt Controller" 76800fa3461SClaudiu Beznea depends on ARCH_AT91 || COMPILE_TEST 76900fa3461SClaudiu Beznea select IRQ_DOMAIN 77000fa3461SClaudiu Beznea select IRQ_DOMAIN_HIERARCHY 77100fa3461SClaudiu Beznea help 77200fa3461SClaudiu Beznea Support for Microchip External Interrupt Controller. 77300fa3461SClaudiu Beznea 774c6674154SChen Wangconfig SOPHGO_SG2042_MSI 775c6674154SChen Wang bool "Sophgo SG2042 MSI Controller" 776c6674154SChen Wang depends on ARCH_SOPHGO || COMPILE_TEST 777c6674154SChen Wang depends on PCI 778c6674154SChen Wang select IRQ_DOMAIN_HIERARCHY 779c6674154SChen Wang select IRQ_MSI_LIB 780c6674154SChen Wang select PCI_MSI 781c6674154SChen Wang help 782c6674154SChen Wang Support for the Sophgo SG2042 MSI Controller. 783c6674154SChen Wang This on-chip interrupt controller enables MSI sources to be 784c6674154SChen Wang routed to the primary PLIC controller on SoC. 785c6674154SChen Wang 786f7189d93SQin Jianconfig SUNPLUS_SP7021_INTC 787f7189d93SQin Jian bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 788f7189d93SQin Jian default SOC_SP7021 789f7189d93SQin Jian help 790f7189d93SQin Jian Support for the Sunplus SP7021 Interrupt Controller IP core. 791f7189d93SQin Jian SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 792f7189d93SQin Jian chained controller, routing all interrupt source in P-Chip to 793f7189d93SQin Jian the primary controller on C-Chip. 794f7189d93SQin Jian 79501493855SJonathan Neuschäferendmenu 796