1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2c94fb639SRandy Dunlapmenu "IRQ chip support" 3c94fb639SRandy Dunlap 4f6e916b8SThomas Petazzoniconfig IRQCHIP 5f6e916b8SThomas Petazzoni def_bool y 6612d5494SHuacai Chen depends on (OF_IRQ || ACPI_GENERIC_GSI) 7f6e916b8SThomas Petazzoni 881243e44SRob Herringconfig ARM_GIC 981243e44SRob Herring bool 10dee23403SMarc Zyngier depends on OF 119a1091efSYingjoe Chen select IRQ_DOMAIN_HIERARCHY 120e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1381243e44SRob Herring 149c8edddfSJon Hunterconfig ARM_GIC_PM 159c8edddfSJon Hunter bool 169c8edddfSJon Hunter depends on PM 179c8edddfSJon Hunter select ARM_GIC 189c8edddfSJon Hunter 19a27d21e0SLinus Walleijconfig ARM_GIC_MAX_NR 20a27d21e0SLinus Walleij int 2170265523SJiangfeng Xiao depends on ARM_GIC 22a27d21e0SLinus Walleij default 2 if ARCH_REALVIEW 23a27d21e0SLinus Walleij default 1 24a27d21e0SLinus Walleij 25853a33ceSSuravee Suthikulpanitconfig ARM_GIC_V2M 26853a33ceSSuravee Suthikulpanit bool 273ee80364SArnd Bergmann depends on PCI 283ee80364SArnd Bergmann select ARM_GIC 2974e44454SThomas Gleixner select IRQ_MSI_LIB 303ee80364SArnd Bergmann select PCI_MSI 3196093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 32853a33ceSSuravee Suthikulpanit 3381243e44SRob Herringconfig GIC_NON_BANKED 3481243e44SRob Herring bool 3581243e44SRob Herring 36021f6537SMarc Zyngierconfig ARM_GIC_V3 37021f6537SMarc Zyngier bool 38443acc4fSMarc Zyngier select IRQ_DOMAIN_HIERARCHY 39e3825ba1SMarc Zyngier select PARTITION_PERCPU 400e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 4135727af2SShanker Donthineni select HAVE_ARM_SMCCC_DISCOVERY 4296093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 43021f6537SMarc Zyngier 44b4ead12dSLorenzo Pieralisiconfig ARM_GIC_ITS_PARENT 45b4ead12dSLorenzo Pieralisi bool 46b4ead12dSLorenzo Pieralisi 4719812729SMarc Zyngierconfig ARM_GIC_V3_ITS 4819812729SMarc Zyngier bool 4913e7accbSThomas Gleixner select GENERIC_MSI_IRQ 5048f71d56SThomas Gleixner select IRQ_MSI_LIB 51b4ead12dSLorenzo Pieralisi select ARM_GIC_ITS_PARENT 5229f41139SMarc Zyngier default ARM_GIC_V3 5396093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 5429f41139SMarc Zyngier 557afe031cSBogdan Purcareataconfig ARM_GIC_V3_ITS_FSL_MC 567afe031cSBogdan Purcareata bool 577afe031cSBogdan Purcareata depends on ARM_GIC_V3_ITS 587afe031cSBogdan Purcareata depends on FSL_MC_BUS 597afe031cSBogdan Purcareata default ARM_GIC_V3_ITS 607afe031cSBogdan Purcareata 617ec80fb3SLorenzo Pieralisiconfig ARM_GIC_V5 627ec80fb3SLorenzo Pieralisi bool 637ec80fb3SLorenzo Pieralisi select IRQ_DOMAIN_HIERARCHY 647ec80fb3SLorenzo Pieralisi select GENERIC_IRQ_EFFECTIVE_AFF_MASK 6557d72196SLorenzo Pieralisi select GENERIC_MSI_IRQ 6657d72196SLorenzo Pieralisi select IRQ_MSI_LIB 6757d72196SLorenzo Pieralisi select ARM_GIC_ITS_PARENT 687ec80fb3SLorenzo Pieralisi 69292ec080SUwe Kleine-Königconfig ARM_NVIC 70292ec080SUwe Kleine-König bool 712d9f59f7SStefan Agner select IRQ_DOMAIN_HIERARCHY 72292ec080SUwe Kleine-König select GENERIC_IRQ_CHIP 73292ec080SUwe Kleine-König 7444430ec0SRob Herringconfig ARM_VIC 7544430ec0SRob Herring bool 7644430ec0SRob Herring select IRQ_DOMAIN 7744430ec0SRob Herring 7844430ec0SRob Herringconfig ARM_VIC_NR 7944430ec0SRob Herring int 8044430ec0SRob Herring default 4 if ARCH_S5PV210 8144430ec0SRob Herring default 2 8244430ec0SRob Herring depends on ARM_VIC 8344430ec0SRob Herring help 8444430ec0SRob Herring The maximum number of VICs available in the system, for 8544430ec0SRob Herring power management. 8644430ec0SRob Herring 8772e257c6SThomas Gleixnerconfig IRQ_MSI_LIB 8872e257c6SThomas Gleixner bool 89eb2c93e7SNam Cao select GENERIC_MSI_IRQ 9072e257c6SThomas Gleixner 91fed6d336SThomas Petazzoniconfig ARMADA_370_XP_IRQ 92fed6d336SThomas Petazzoni bool 93fed6d336SThomas Petazzoni select GENERIC_IRQ_CHIP 943ee80364SArnd Bergmann select PCI_MSI if PCI 95bafb2901SNam Cao select IRQ_MSI_LIB if PCI 960e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 97fed6d336SThomas Petazzoni 98e6b78f2cSAntoine Tenartconfig ALPINE_MSI 99e6b78f2cSAntoine Tenart bool 1003ee80364SArnd Bergmann depends on PCI 1013ee80364SArnd Bergmann select PCI_MSI 1027a91ad7eSThomas Gleixner select IRQ_MSI_LIB 103e6b78f2cSAntoine Tenart select GENERIC_IRQ_CHIP 104e6b78f2cSAntoine Tenart 1051eb77c3bSTalel Shenharconfig AL_FIC 1061eb77c3bSTalel Shenhar bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 1079869f37aSJean Delvare depends on OF 10835e0cd77SBaoquan He depends on HAS_IOMEM 1091eb77c3bSTalel Shenhar select GENERIC_IRQ_CHIP 1101eb77c3bSTalel Shenhar select IRQ_DOMAIN 1111eb77c3bSTalel Shenhar help 1121eb77c3bSTalel Shenhar Support Amazon's Annapurna Labs Fabric Interrupt Controller. 1131eb77c3bSTalel Shenhar 114b1479ebbSBoris BREZILLONconfig ATMEL_AIC_IRQ 115b1479ebbSBoris BREZILLON bool 116b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 117b1479ebbSBoris BREZILLON select IRQ_DOMAIN 118b1479ebbSBoris BREZILLON select SPARSE_IRQ 119b1479ebbSBoris BREZILLON 120b1479ebbSBoris BREZILLONconfig ATMEL_AIC5_IRQ 121b1479ebbSBoris BREZILLON bool 122b1479ebbSBoris BREZILLON select GENERIC_IRQ_CHIP 123b1479ebbSBoris BREZILLON select IRQ_DOMAIN 124b1479ebbSBoris BREZILLON select SPARSE_IRQ 125b1479ebbSBoris BREZILLON 1260509cfdeSRalf Baechleconfig I8259 1270509cfdeSRalf Baechle bool 1280509cfdeSRalf Baechle select IRQ_DOMAIN 1290509cfdeSRalf Baechle 13032c6c054SStanimir Varbanovconfig BCM2712_MIP 13132c6c054SStanimir Varbanov tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 1329b3ae50cSPeter Robinson depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 1339b3ae50cSPeter Robinson default m if ARCH_BRCMSTB || ARCH_BCM2835 13432c6c054SStanimir Varbanov depends on ARM_GIC 13532c6c054SStanimir Varbanov select GENERIC_IRQ_CHIP 13632c6c054SStanimir Varbanov select IRQ_DOMAIN_HIERARCHY 13732c6c054SStanimir Varbanov select GENERIC_MSI_IRQ 13832c6c054SStanimir Varbanov select IRQ_MSI_LIB 13932c6c054SStanimir Varbanov help 14032c6c054SStanimir Varbanov Enable support for the Broadcom BCM2712 MSI-X target peripheral 14132c6c054SStanimir Varbanov (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 14232c6c054SStanimir Varbanov Raspberry Pi 5. 14332c6c054SStanimir Varbanov 14432c6c054SStanimir Varbanov If unsure say n. 14532c6c054SStanimir Varbanov 146c7c42ec2SSimon Arlottconfig BCM6345_L1_IRQ 147c7c42ec2SSimon Arlott bool 148c7c42ec2SSimon Arlott select GENERIC_IRQ_CHIP 149c7c42ec2SSimon Arlott select IRQ_DOMAIN 1500e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 151c7c42ec2SSimon Arlott 1525f7f0317SKevin Cernekeeconfig BCM7038_L1_IRQ 153c057c799SFlorian Fainelli tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 154c057c799SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 155c057c799SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 1565f7f0317SKevin Cernekee select GENERIC_IRQ_CHIP 1575f7f0317SKevin Cernekee select IRQ_DOMAIN 1580e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 1595f7f0317SKevin Cernekee 160a4fcbb86SKevin Cernekeeconfig BCM7120_L2_IRQ 1613ac268d5SFlorian Fainelli tristate "Broadcom STB 7120-style L2 interrupt controller driver" 1623ac268d5SFlorian Fainelli depends on ARCH_BRCMSTB || BMIPS_GENERIC 1633ac268d5SFlorian Fainelli default ARCH_BRCMSTB || BMIPS_GENERIC 164a4fcbb86SKevin Cernekee select GENERIC_IRQ_CHIP 165a4fcbb86SKevin Cernekee select IRQ_DOMAIN 166a4fcbb86SKevin Cernekee 1677f646e92SFlorian Fainelliconfig BRCMSTB_L2_IRQ 16851d9db5cSFlorian Fainelli tristate "Broadcom STB generic L2 interrupt controller driver" 16951d9db5cSFlorian Fainelli depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 17051d9db5cSFlorian Fainelli default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 1717f646e92SFlorian Fainelli select GENERIC_IRQ_CHIP 1727f646e92SFlorian Fainelli select IRQ_DOMAIN 1737f646e92SFlorian Fainelli 1740fc3d74cSBartosz Golaszewskiconfig DAVINCI_CP_INTC 1750fc3d74cSBartosz Golaszewski bool 1760fc3d74cSBartosz Golaszewski select GENERIC_IRQ_CHIP 1770fc3d74cSBartosz Golaszewski select IRQ_DOMAIN 1780fc3d74cSBartosz Golaszewski 179350d71b9SSebastian Hesselbarthconfig DW_APB_ICTL 180be5e5f3aSThomas Gleixner bool 181e1588490SJisheng Zhang select GENERIC_IRQ_CHIP 18254a38440SZhen Lei select IRQ_DOMAIN_HIERARCHY 183350d71b9SSebastian Hesselbarth 1841902a59cSCaleb James DeLisleconfig ECONET_EN751221_INTC 1851902a59cSCaleb James DeLisle bool 1861902a59cSCaleb James DeLisle select GENERIC_IRQ_CHIP 1871902a59cSCaleb James DeLisle select IRQ_DOMAIN 1881902a59cSCaleb James DeLisle 1896ee532e2SLinus Walleijconfig FARADAY_FTINTC010 1906ee532e2SLinus Walleij bool 1916ee532e2SLinus Walleij select IRQ_DOMAIN 1926ee532e2SLinus Walleij select SPARSE_IRQ 1936ee532e2SLinus Walleij 1949a7c4abdSMaJunconfig HISILICON_IRQ_MBIGEN 1959a7c4abdSMaJun bool 1969a7c4abdSMaJun select ARM_GIC_V3 1979a7c4abdSMaJun select ARM_GIC_V3_ITS 1989a7c4abdSMaJun 199b6ef9161SJames Hoganconfig IMGPDC_IRQ 200b6ef9161SJames Hogan bool 201b6ef9161SJames Hogan select GENERIC_IRQ_CHIP 202b6ef9161SJames Hogan select IRQ_DOMAIN 203b6ef9161SJames Hogan 2045b978c10SLinus Walleijconfig IXP4XX_IRQ 2055b978c10SLinus Walleij bool 2065b978c10SLinus Walleij select IRQ_DOMAIN 2075b978c10SLinus Walleij select SPARSE_IRQ 2085b978c10SLinus Walleij 2093e3a7b35SHerve Codinaconfig LAN966X_OIC 2103e3a7b35SHerve Codina tristate "Microchip LAN966x OIC Support" 211e06c9e36SGeert Uytterhoeven depends on MCHP_LAN966X_PCI || COMPILE_TEST 2123e3a7b35SHerve Codina select GENERIC_IRQ_CHIP 2133e3a7b35SHerve Codina select IRQ_DOMAIN 2143e3a7b35SHerve Codina help 2153e3a7b35SHerve Codina Enable support for the LAN966x Outbound Interrupt Controller. 2163e3a7b35SHerve Codina This controller is present on the Microchip LAN966x PCI device and 2173e3a7b35SHerve Codina maps the internal interrupts sources to PCIe interrupt. 2183e3a7b35SHerve Codina 2193e3a7b35SHerve Codina To compile this driver as a module, choose M here: the module 2203e3a7b35SHerve Codina will be called irq-lan966x-oic. 2213e3a7b35SHerve Codina 222da0abe1aSRichard Fitzgeraldconfig MADERA_IRQ 223da0abe1aSRichard Fitzgerald tristate 224da0abe1aSRichard Fitzgerald 22567e38cf2SRalf Baechleconfig IRQ_MIPS_CPU 22667e38cf2SRalf Baechle bool 22767e38cf2SRalf Baechle select GENERIC_IRQ_CHIP 2280f5209feSSamuel Holland select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 22967e38cf2SRalf Baechle select IRQ_DOMAIN 2300e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 23167e38cf2SRalf Baechle 232afc98d90SAlexander Shiyanconfig CLPS711X_IRQCHIP 233afc98d90SAlexander Shiyan bool 234afc98d90SAlexander Shiyan depends on ARCH_CLPS711X 235afc98d90SAlexander Shiyan select IRQ_DOMAIN 236afc98d90SAlexander Shiyan select SPARSE_IRQ 237afc98d90SAlexander Shiyan default y 238afc98d90SAlexander Shiyan 2399b54470aSStafford Horneconfig OMPIC 2409b54470aSStafford Horne bool 2419b54470aSStafford Horne 2424db8e6d2SStefan Kristianssonconfig OR1K_PIC 2434db8e6d2SStefan Kristiansson bool 2444db8e6d2SStefan Kristiansson select IRQ_DOMAIN 2454db8e6d2SStefan Kristiansson 2468598066cSFelipe Balbiconfig OMAP_IRQCHIP 2478598066cSFelipe Balbi bool 2488598066cSFelipe Balbi select GENERIC_IRQ_CHIP 2498598066cSFelipe Balbi select IRQ_DOMAIN 2508598066cSFelipe Balbi 2519dbd90f1SSebastian Hesselbarthconfig ORION_IRQCHIP 2529dbd90f1SSebastian Hesselbarth bool 2539dbd90f1SSebastian Hesselbarth select IRQ_DOMAIN 2549dbd90f1SSebastian Hesselbarth 255aaa8666aSCristian Birsanconfig PIC32_EVIC 256aaa8666aSCristian Birsan bool 257aaa8666aSCristian Birsan select GENERIC_IRQ_CHIP 258aaa8666aSCristian Birsan select IRQ_DOMAIN 259aaa8666aSCristian Birsan 260981b58f6SRich Felkerconfig JCORE_AIC 2613602ffdeSRich Felker bool "J-Core integrated AIC" if COMPILE_TEST 2623602ffdeSRich Felker depends on OF 263981b58f6SRich Felker select IRQ_DOMAIN 264981b58f6SRich Felker help 265981b58f6SRich Felker Support for the J-Core integrated AIC. 266981b58f6SRich Felker 267d852e62aSManivannan Sadhasivamconfig RDA_INTC 268d852e62aSManivannan Sadhasivam bool 269d852e62aSManivannan Sadhasivam select IRQ_DOMAIN 270d852e62aSManivannan Sadhasivam 27144358048SMagnus Dammconfig RENESAS_INTC_IRQPIN 27202d7e041SGeert Uytterhoeven bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 27344358048SMagnus Damm select IRQ_DOMAIN 27402d7e041SGeert Uytterhoeven help 27502d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 27602d7e041SGeert Uytterhoeven interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 27744358048SMagnus Damm 278fbc83b7fSMagnus Dammconfig RENESAS_IRQC 27972d44c0cSLad Prabhakar bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 28099c221dfSMagnus Damm select GENERIC_IRQ_CHIP 281fbc83b7fSMagnus Damm select IRQ_DOMAIN 28202d7e041SGeert Uytterhoeven help 28302d7e041SGeert Uytterhoeven Enable support for the Renesas Interrupt Controller for external 28472d44c0cSLad Prabhakar devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 285fbc83b7fSMagnus Damm 286a644ccb8SGeert Uytterhoevenconfig RENESAS_RZA1_IRQC 28702d7e041SGeert Uytterhoeven bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 288a644ccb8SGeert Uytterhoeven select IRQ_DOMAIN_HIERARCHY 28902d7e041SGeert Uytterhoeven help 29002d7e041SGeert Uytterhoeven Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 29102d7e041SGeert Uytterhoeven to 8 external interrupts with configurable sense select. 292a644ccb8SGeert Uytterhoeven 2933fed0955SLad Prabhakarconfig RENESAS_RZG2L_IRQC 2943fed0955SLad Prabhakar bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 2953fed0955SLad Prabhakar select GENERIC_IRQ_CHIP 2963fed0955SLad Prabhakar select IRQ_DOMAIN_HIERARCHY 2973fed0955SLad Prabhakar help 2983fed0955SLad Prabhakar Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 2993fed0955SLad Prabhakar for external devices. 3003fed0955SLad Prabhakar 3010d7605e7SFabrizio Castroconfig RENESAS_RZV2H_ICU 3020d7605e7SFabrizio Castro bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 3030d7605e7SFabrizio Castro select GENERIC_IRQ_CHIP 3040d7605e7SFabrizio Castro select IRQ_DOMAIN_HIERARCHY 3050d7605e7SFabrizio Castro help 3060d7605e7SFabrizio Castro Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 3070d7605e7SFabrizio Castro 30803ac990eSMichael Walleconfig SL28CPLD_INTC 30903ac990eSMichael Walle bool "Kontron sl28cpld IRQ controller" 31003ac990eSMichael Walle depends on MFD_SL28CPLD=y || COMPILE_TEST 31103ac990eSMichael Walle select REGMAP_IRQ 31203ac990eSMichael Walle help 31303ac990eSMichael Walle Interrupt controller driver for the board management controller 31403ac990eSMichael Walle found on the Kontron sl28 CPLD. 31503ac990eSMichael Walle 31607088484SLee Jonesconfig ST_IRQCHIP 31707088484SLee Jones bool 31807088484SLee Jones select REGMAP 31907088484SLee Jones select MFD_SYSCON 32007088484SLee Jones help 32107088484SLee Jones Enables SysCfg Controlled IRQs on STi based platforms. 32207088484SLee Jones 323d421fd6dSSamuel Hollandconfig SUN4I_INTC 324d421fd6dSSamuel Holland bool 325d421fd6dSSamuel Holland 326d421fd6dSSamuel Hollandconfig SUN6I_R_INTC 327d421fd6dSSamuel Holland bool 328d421fd6dSSamuel Holland select IRQ_DOMAIN_HIERARCHY 329d421fd6dSSamuel Holland select IRQ_FASTEOI_HIERARCHY_HANDLERS 330d421fd6dSSamuel Holland 331d421fd6dSSamuel Hollandconfig SUNXI_NMI_INTC 332d421fd6dSSamuel Holland bool 333d421fd6dSSamuel Holland select GENERIC_IRQ_CHIP 334d421fd6dSSamuel Holland 335b06eb017SChristian Ruppertconfig TB10X_IRQC 336b06eb017SChristian Ruppert bool 337b06eb017SChristian Ruppert select IRQ_DOMAIN 338b06eb017SChristian Ruppert select GENERIC_IRQ_CHIP 339b06eb017SChristian Ruppert 340d01f8633SDamien Riegelconfig TS4800_IRQ 341d01f8633SDamien Riegel tristate "TS-4800 IRQ controller" 342d01f8633SDamien Riegel select IRQ_DOMAIN 3430df337cfSRichard Weinberger depends on HAS_IOMEM 344d2b383dcSJean Delvare depends on SOC_IMX51 || COMPILE_TEST 345d01f8633SDamien Riegel help 346d01f8633SDamien Riegel Support for the TS-4800 FPGA IRQ controller 347d01f8633SDamien Riegel 3482389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ 3492389d501SLinus Walleij bool 3502389d501SLinus Walleij select IRQ_DOMAIN 3512389d501SLinus Walleij 3522389d501SLinus Walleijconfig VERSATILE_FPGA_IRQ_NR 3532389d501SLinus Walleij int 3542389d501SLinus Walleij default 4 3552389d501SLinus Walleij depends on VERSATILE_FPGA_IRQ 35626a8e96aSMax Filippov 35726a8e96aSMax Filippovconfig XTENSA_MX 35826a8e96aSMax Filippov bool 35926a8e96aSMax Filippov select IRQ_DOMAIN 3600e6c027cSSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 36196ca848eSSricharan R 3620547dc78SZubair Lutfullah Kakakhelconfig XILINX_INTC 363debf69cfSRobert Hancock bool "Xilinx Interrupt Controller IP" 364fd31000dSJamie Iles depends on OF_ADDRESS 3650547dc78SZubair Lutfullah Kakakhel select IRQ_DOMAIN 366debf69cfSRobert Hancock help 367debf69cfSRobert Hancock Support for the Xilinx Interrupt Controller IP core. 368debf69cfSRobert Hancock This is used as a primary controller with MicroBlaze and can also 369debf69cfSRobert Hancock be used as a secondary chained controller on other platforms. 3700547dc78SZubair Lutfullah Kakakhel 37196ca848eSSricharan Rconfig IRQ_CROSSBAR 37296ca848eSSricharan R bool 37396ca848eSSricharan R help 374f54619f2SMasanari Iida Support for a CROSSBAR ip that precedes the main interrupt controller. 37596ca848eSSricharan R The primary irqchip invokes the crossbar's callback which inturn allocates 37696ca848eSSricharan R a free irq and configures the IP. Thus the peripheral interrupts are 37796ca848eSSricharan R routed to one of the free irqchip interrupt lines. 37889323f8cSGrygorii Strashko 37989323f8cSGrygorii Strashkoconfig KEYSTONE_IRQ 38089323f8cSGrygorii Strashko tristate "Keystone 2 IRQ controller IP" 38189323f8cSGrygorii Strashko depends on ARCH_KEYSTONE 38289323f8cSGrygorii Strashko help 38389323f8cSGrygorii Strashko Support for Texas Instruments Keystone 2 IRQ controller IP which 38489323f8cSGrygorii Strashko is part of the Keystone 2 IPC mechanism 3858a19b8f1SAndrew Bresticker 3868a19b8f1SAndrew Brestickerconfig MIPS_GIC 3878a19b8f1SAndrew Bresticker bool 3880053892fSNathan Chancellor select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 3898190cc57SSamuel Holland select GENERIC_IRQ_IPI if SMP 3908190cc57SSamuel Holland select IRQ_DOMAIN_HIERARCHY 3918a19b8f1SAndrew Bresticker select MIPS_CM 3928a764482SYoshinori Sato 39344e08e70SPaul Burtonconfig INGENIC_IRQ 39444e08e70SPaul Burton bool 39544e08e70SPaul Burton depends on MACH_INGENIC 39644e08e70SPaul Burton default y 39778c10e55SLinus Torvalds 3989536eba0SPaul Cercueilconfig INGENIC_TCU_IRQ 3999536eba0SPaul Cercueil bool "Ingenic JZ47xx TCU interrupt controller" 4009536eba0SPaul Cercueil default MACH_INGENIC 4019536eba0SPaul Cercueil depends on MIPS || COMPILE_TEST 4029536eba0SPaul Cercueil select MFD_SYSCON 4038084499bSYueHaibing select GENERIC_IRQ_CHIP 4049536eba0SPaul Cercueil help 4059536eba0SPaul Cercueil Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 4069536eba0SPaul Cercueil JZ47xx SoCs. 4079536eba0SPaul Cercueil 4089536eba0SPaul Cercueil If unsure, say N. 4099536eba0SPaul Cercueil 410e324c4dcSShenwei Wangconfig IMX_GPCV2 411e324c4dcSShenwei Wang bool 412e324c4dcSShenwei Wang select IRQ_DOMAIN 413e324c4dcSShenwei Wang help 414e324c4dcSShenwei Wang Enables the wakeup IRQs for IMX platforms with GPCv2 block 4157e4ac676SOleksij Rempel 4167e4ac676SOleksij Rempelconfig IRQ_MXS 4177e4ac676SOleksij Rempel def_bool y if MACH_ASM9260 || ARCH_MXS 4187e4ac676SOleksij Rempel select IRQ_DOMAIN 4197e4ac676SOleksij Rempel select STMP_DEVICE 420c27f29bbSThomas Petazzoni 42119d99164SAlexandre Belloniconfig MSCC_OCELOT_IRQ 42219d99164SAlexandre Belloni bool 42319d99164SAlexandre Belloni select IRQ_DOMAIN 42419d99164SAlexandre Belloni select GENERIC_IRQ_CHIP 42519d99164SAlexandre Belloni 426a68a63cbSThomas Petazzoniconfig MVEBU_GICP 427cdb23872SThomas Gleixner select IRQ_MSI_LIB 428a68a63cbSThomas Petazzoni bool 429a68a63cbSThomas Petazzoni 430e0de91a9SThomas Petazzoniconfig MVEBU_ICU 431e0de91a9SThomas Petazzoni bool 432e0de91a9SThomas Petazzoni 433c27f29bbSThomas Petazzoniconfig MVEBU_ODMI 434c27f29bbSThomas Petazzoni bool 435e0b99c4cSThomas Gleixner select IRQ_MSI_LIB 43613e7accbSThomas Gleixner select GENERIC_MSI_IRQ 4379e2c986cSMarc Zyngier 438a109893bSThomas Petazzoniconfig MVEBU_PIC 439a109893bSThomas Petazzoni bool 440a109893bSThomas Petazzoni 44161ce8d8dSMiquel Raynalconfig MVEBU_SEI 44261ce8d8dSMiquel Raynal bool 44361ce8d8dSMiquel Raynal 4440dcd9f87SRasmus Villemoesconfig LS_EXTIRQ 4450dcd9f87SRasmus Villemoes def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 4460dcd9f87SRasmus Villemoes select MFD_SYSCON 4470dcd9f87SRasmus Villemoes 448b8f3ebe6SMinghuan Lianconfig LS_SCFG_MSI 449b8f3ebe6SMinghuan Lian def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 45096093fe5SJason Gunthorpe select IRQ_MSI_IOMMU 4519c1a7bfcSLukas Bulwahn depends on PCI_MSI 45294b59d5fSNam Cao select IRQ_MSI_LIB 453b8f3ebe6SMinghuan Lian 4549e2c986cSMarc Zyngierconfig PARTITION_PERCPU 4559e2c986cSMarc Zyngier bool 4560efacbbaSLinus Torvalds 457b20cf2dcSAntonio Borneoconfig STM32MP_EXTI 4580be58e05SAntonio Borneo tristate "STM32MP extended interrupts and event controller" 4590be58e05SAntonio Borneo depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 4609151299eSGeert Uytterhoeven default ARCH_STM32 && !ARM_SINGLE_ARMV7M 4610be58e05SAntonio Borneo select IRQ_DOMAIN_HIERARCHY 462350755e2SAntonio Borneo select GENERIC_IRQ_CHIP 4630be58e05SAntonio Borneo help 4640be58e05SAntonio Borneo Support STM32MP EXTI (extended interrupts and event) controller. 465b20cf2dcSAntonio Borneo 466e0720416SAlexandre TORGUEconfig STM32_EXTI 467e0720416SAlexandre TORGUE bool 468e0720416SAlexandre TORGUE select IRQ_DOMAIN 4690e7d7807SLudovic Barre select GENERIC_IRQ_CHIP 470f20cc9b0SAgustin Vega-Frias 471f20cc9b0SAgustin Vega-Friasconfig QCOM_IRQ_COMBINER 472f20cc9b0SAgustin Vega-Frias bool "QCOM IRQ combiner support" 473f20cc9b0SAgustin Vega-Frias depends on ARCH_QCOM && ACPI 474f20cc9b0SAgustin Vega-Frias select IRQ_DOMAIN_HIERARCHY 475f20cc9b0SAgustin Vega-Frias help 476f20cc9b0SAgustin Vega-Frias Say yes here to add support for the IRQ combiner devices embedded 477f20cc9b0SAgustin Vega-Frias in Qualcomm Technologies chips. 4785ed34d3aSMasahiro Yamada 4795ed34d3aSMasahiro Yamadaconfig IRQ_UNIPHIER_AIDET 4805ed34d3aSMasahiro Yamada bool "UniPhier AIDET support" if COMPILE_TEST 4815ed34d3aSMasahiro Yamada depends on ARCH_UNIPHIER || COMPILE_TEST 4825ed34d3aSMasahiro Yamada default ARCH_UNIPHIER 4835ed34d3aSMasahiro Yamada select IRQ_DOMAIN_HIERARCHY 4845ed34d3aSMasahiro Yamada help 4855ed34d3aSMasahiro Yamada Support for the UniPhier AIDET (ARM Interrupt Detector). 486c94fb639SRandy Dunlap 487215f4cc0SJerome Brunetconfig MESON_IRQ_GPIO 488a947aa00SNeil Armstrong tristate "Meson GPIO Interrupt Multiplexer" 489a947aa00SNeil Armstrong depends on ARCH_MESON || COMPILE_TEST 490a947aa00SNeil Armstrong default ARCH_MESON 491215f4cc0SJerome Brunet select IRQ_DOMAIN_HIERARCHY 492215f4cc0SJerome Brunet help 493215f4cc0SJerome Brunet Support Meson SoC Family GPIO Interrupt Multiplexer 494215f4cc0SJerome Brunet 4954235ff50SMiodrag Dinicconfig GOLDFISH_PIC 4964235ff50SMiodrag Dinic bool "Goldfish programmable interrupt controller" 4974235ff50SMiodrag Dinic depends on MIPS && (GOLDFISH || COMPILE_TEST) 498969ac78dSRandy Dunlap select GENERIC_IRQ_CHIP 4994235ff50SMiodrag Dinic select IRQ_DOMAIN 5004235ff50SMiodrag Dinic help 5014235ff50SMiodrag Dinic Say yes here to enable Goldfish interrupt controller driver used 5024235ff50SMiodrag Dinic for Goldfish based virtual platforms. 5034235ff50SMiodrag Dinic 504f55c73aeSArchana Sathyakumarconfig QCOM_PDC 5054acd8a4bSSaravana Kannan tristate "QCOM PDC" 506f55c73aeSArchana Sathyakumar depends on ARCH_QCOM 507f55c73aeSArchana Sathyakumar select IRQ_DOMAIN_HIERARCHY 508f55c73aeSArchana Sathyakumar help 509f55c73aeSArchana Sathyakumar Power Domain Controller driver to manage and configure wakeup 510f55c73aeSArchana Sathyakumar IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 511f55c73aeSArchana Sathyakumar 512a6199bb5SShawn Guoconfig QCOM_MPM 513a6199bb5SShawn Guo tristate "QCOM MPM" 514a6199bb5SShawn Guo depends on ARCH_QCOM 515fa4dcc88SYueHaibing depends on MAILBOX 516a6199bb5SShawn Guo select IRQ_DOMAIN_HIERARCHY 517a6199bb5SShawn Guo help 518a6199bb5SShawn Guo MSM Power Manager driver to manage and configure wakeup 519a6199bb5SShawn Guo IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 520a6199bb5SShawn Guo 521d8a5f5f7SGuo Renconfig CSKY_MPINTC 522be1abc5bSGuo Ren bool 523d8a5f5f7SGuo Ren depends on CSKY 524d8a5f5f7SGuo Ren help 525d8a5f5f7SGuo Ren Say yes here to enable C-SKY SMP interrupt controller driver used 526d8a5f5f7SGuo Ren for C-SKY SMP system. 527656b42deSRandy Dunlap In fact it's not mmio map in hardware and it uses ld/st to visit the 528d8a5f5f7SGuo Ren controller's register inside CPU. 529d8a5f5f7SGuo Ren 530edff1b48SGuo Renconfig CSKY_APB_INTC 531edff1b48SGuo Ren bool "C-SKY APB Interrupt Controller" 532edff1b48SGuo Ren depends on CSKY 533edff1b48SGuo Ren help 534edff1b48SGuo Ren Say yes here to enable C-SKY APB interrupt controller driver used 535656b42deSRandy Dunlap by C-SKY single core SOC system. It uses mmio map apb-bus to visit 536edff1b48SGuo Ren the controller's register. 537edff1b48SGuo Ren 5380136afa0SLucas Stachconfig IMX_IRQSTEER 5390136afa0SLucas Stach bool "i.MX IRQSTEER support" 5400136afa0SLucas Stach depends on ARCH_MXC || COMPILE_TEST 5410136afa0SLucas Stach default ARCH_MXC 5420136afa0SLucas Stach select IRQ_DOMAIN 5430136afa0SLucas Stach help 5440136afa0SLucas Stach Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 5450136afa0SLucas Stach 5462fbb1396SJoakim Zhangconfig IMX_INTMUX 547a890caebSGeert Uytterhoeven bool "i.MX INTMUX support" if COMPILE_TEST 548a890caebSGeert Uytterhoeven default y if ARCH_MXC 5492fbb1396SJoakim Zhang select IRQ_DOMAIN 5502fbb1396SJoakim Zhang help 5512fbb1396SJoakim Zhang Support for the i.MX INTMUX interrupt multiplexer. 5522fbb1396SJoakim Zhang 55370afdab9SFrank Liconfig IMX_MU_MSI 55470afdab9SFrank Li tristate "i.MX MU used as MSI controller" 55570afdab9SFrank Li depends on OF && HAS_IOMEM 5566c9f7434SGeert Uytterhoeven depends on ARCH_MXC || COMPILE_TEST 557*3b6a18f0SArnd Bergmann depends on ARM || ARM64 55870afdab9SFrank Li default m if ARCH_MXC 55970afdab9SFrank Li select IRQ_DOMAIN 56070afdab9SFrank Li select IRQ_DOMAIN_HIERARCHY 56113e7accbSThomas Gleixner select GENERIC_MSI_IRQ 5627b2f8aa0SThomas Gleixner select IRQ_MSI_LIB 56370afdab9SFrank Li help 5646c9f7434SGeert Uytterhoeven Provide a driver for the i.MX Messaging Unit block used as a 5656c9f7434SGeert Uytterhoeven CPU-to-CPU MSI controller. This requires a specially crafted DT 5666c9f7434SGeert Uytterhoeven to make use of this driver. 56770afdab9SFrank Li 56870afdab9SFrank Li If unsure, say N 56970afdab9SFrank Li 5709e543e22SJiaxun Yangconfig LS1X_IRQ 5719e543e22SJiaxun Yang bool "Loongson-1 Interrupt Controller" 5729e543e22SJiaxun Yang depends on MACH_LOONGSON32 5739e543e22SJiaxun Yang default y 5749e543e22SJiaxun Yang select IRQ_DOMAIN 5759e543e22SJiaxun Yang select GENERIC_IRQ_CHIP 5769e543e22SJiaxun Yang help 5779e543e22SJiaxun Yang Support for the Loongson-1 platform Interrupt Controller. 5789e543e22SJiaxun Yang 579cd844b07SLokesh Vutlaconfig TI_SCI_INTR_IRQCHIP 5802d95ffaeSNicolas Frayer tristate "TI SCI INTR Interrupt Controller" 581cd844b07SLokesh Vutla depends on TI_SCI_PROTOCOL 5822d95ffaeSNicolas Frayer depends on ARCH_K3 || COMPILE_TEST 583cd844b07SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 584cd844b07SLokesh Vutla help 585cd844b07SLokesh Vutla This enables the irqchip driver support for K3 Interrupt router 586cd844b07SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 587cd844b07SLokesh Vutla If you wish to use interrupt router irq resources managed by the 588cd844b07SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 589cd844b07SLokesh Vutla 5909f1463b8SLokesh Vutlaconfig TI_SCI_INTA_IRQCHIP 591b8b26ae3SNicolas Frayer tristate "TI SCI INTA Interrupt Controller" 5929f1463b8SLokesh Vutla depends on TI_SCI_PROTOCOL 593b8b26ae3SNicolas Frayer depends on ARCH_K3 || (COMPILE_TEST && ARM64) 5949f1463b8SLokesh Vutla select IRQ_DOMAIN_HIERARCHY 595f011df61SLokesh Vutla select TI_SCI_INTA_MSI_DOMAIN 5969f1463b8SLokesh Vutla help 5979f1463b8SLokesh Vutla This enables the irqchip driver support for K3 Interrupt aggregator 5989f1463b8SLokesh Vutla over TI System Control Interface available on some new TI's SoCs. 5999f1463b8SLokesh Vutla If you wish to use interrupt aggregator irq resources managed by the 6009f1463b8SLokesh Vutla TI System Controller, say Y here. Otherwise, say N. 6019f1463b8SLokesh Vutla 60204e2d1e0SGrzegorz Jaszczykconfig TI_PRUSS_INTC 603b8e594faSSuman Anna tristate 604b8e594faSSuman Anna depends on TI_PRUSS 605b8e594faSSuman Anna default TI_PRUSS 60604e2d1e0SGrzegorz Jaszczyk select IRQ_DOMAIN 60704e2d1e0SGrzegorz Jaszczyk help 60804e2d1e0SGrzegorz Jaszczyk This enables support for the PRU-ICSS Local Interrupt Controller 60904e2d1e0SGrzegorz Jaszczyk present within a PRU-ICSS subsystem present on various TI SoCs. 61004e2d1e0SGrzegorz Jaszczyk The PRUSS INTC enables various interrupts to be routed to multiple 61104e2d1e0SGrzegorz Jaszczyk different processors within the SoC. 61204e2d1e0SGrzegorz Jaszczyk 6136b7ce892SAnup Patelconfig RISCV_INTC 614d8fb1307SConor Dooley bool 6156b7ce892SAnup Patel depends on RISCV 616832f15f4SAnup Patel select IRQ_DOMAIN_HIERARCHY 6176b7ce892SAnup Patel 6182333df5aSAnup Patelconfig RISCV_APLIC 6192333df5aSAnup Patel bool 6202333df5aSAnup Patel depends on RISCV 6212333df5aSAnup Patel select IRQ_DOMAIN_HIERARCHY 6222333df5aSAnup Patel 623ca8df97fSAnup Patelconfig RISCV_APLIC_MSI 624ca8df97fSAnup Patel bool 625ca8df97fSAnup Patel depends on RISCV_APLIC 626ca8df97fSAnup Patel select GENERIC_MSI_IRQ 627ca8df97fSAnup Patel default RISCV_APLIC 628ca8df97fSAnup Patel 62921a8f8a0SAnup Patelconfig RISCV_IMSIC 63021a8f8a0SAnup Patel bool 63121a8f8a0SAnup Patel depends on RISCV 63221a8f8a0SAnup Patel select IRQ_DOMAIN_HIERARCHY 63321a8f8a0SAnup Patel select GENERIC_IRQ_MATRIX_ALLOCATOR 63421a8f8a0SAnup Patel select GENERIC_MSI_IRQ 635fe35eceeSThomas Gleixner select IRQ_MSI_LIB 6365c5a71d0SAnup Patel 6378237f8bcSChristoph Hellwigconfig SIFIVE_PLIC 638fdb1742aSConor Dooley bool 6398237f8bcSChristoph Hellwig depends on RISCV 640466008f9SYash Shah select IRQ_DOMAIN_HIERARCHY 641de078949SSamuel Holland select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 64201493855SJonathan Neuschäfer 643e4e53503SChanghuang Liangconfig STARFIVE_JH8100_INTC 644e4e53503SChanghuang Liang bool "StarFive JH8100 External Interrupt Controller" 645e4e53503SChanghuang Liang depends on ARCH_STARFIVE || COMPILE_TEST 646e4e53503SChanghuang Liang default ARCH_STARFIVE 647e4e53503SChanghuang Liang select IRQ_DOMAIN_HIERARCHY 648e4e53503SChanghuang Liang help 649e4e53503SChanghuang Liang This enables support for the INTC chip found in StarFive JH8100 650e4e53503SChanghuang Liang SoC. 651e4e53503SChanghuang Liang 652e4e53503SChanghuang Liang If you don't know what to do here, say Y. 653e4e53503SChanghuang Liang 654df0f030eSVladimir Kondratievconfig ACLINT_SSWI 655df0f030eSVladimir Kondratiev bool "RISC-V ACLINT S-mode IPI Interrupt Controller" 65625caea95SInochi Amaoto depends on RISCV 65725caea95SInochi Amaoto depends on SMP 65825caea95SInochi Amaoto select IRQ_DOMAIN_HIERARCHY 65925caea95SInochi Amaoto select GENERIC_IRQ_IPI_MUX 66025caea95SInochi Amaoto help 661df0f030eSVladimir Kondratiev This enables support for variants of the RISC-V ACLINT-SSWI device. 662df0f030eSVladimir Kondratiev Supported variants are: 663df0f030eSVladimir Kondratiev - T-HEAD, with compatible "thead,c900-aclint-sswi" 664df0f030eSVladimir Kondratiev - MIPS P8700, with compatible "mips,p8700-aclint-sswi" 66525caea95SInochi Amaoto 66625caea95SInochi Amaoto If you don't know what to do here, say Y. 66725caea95SInochi Amaoto 668df0f030eSVladimir Kondratiev# Backwards compatibility so oldconfig does not drop it. 669df0f030eSVladimir Kondratievconfig THEAD_C900_ACLINT_SSWI 670df0f030eSVladimir Kondratiev bool 671df0f030eSVladimir Kondratiev select ACLINT_SSWI 672df0f030eSVladimir Kondratiev 673b74416dbSHyunki Kooconfig EXYNOS_IRQ_COMBINER 674b74416dbSHyunki Koo bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 675b74416dbSHyunki Koo depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 676b74416dbSHyunki Koo help 677b74416dbSHyunki Koo Say yes here to add support for the IRQ combiner devices embedded 678b74416dbSHyunki Koo in Samsung Exynos chips. 679b74416dbSHyunki Koo 680b2d3e335SHuacai Chenconfig IRQ_LOONGARCH_CPU 681b2d3e335SHuacai Chen bool 682b2d3e335SHuacai Chen select GENERIC_IRQ_CHIP 683b2d3e335SHuacai Chen select IRQ_DOMAIN 68442a7d887STiezhu Yang select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 68570f7b6c0SHuacai Chen select LOONGSON_HTVEC 6868d5356f9SHuacai Chen select LOONGSON_LIOINTC 6878d5356f9SHuacai Chen select LOONGSON_EIOINTC 6888d5356f9SHuacai Chen select LOONGSON_PCH_PIC 6898d5356f9SHuacai Chen select LOONGSON_PCH_MSI 6908d5356f9SHuacai Chen select LOONGSON_PCH_LPC 691b2d3e335SHuacai Chen help 692b2d3e335SHuacai Chen Support for the LoongArch CPU Interrupt Controller. For details of 693b2d3e335SHuacai Chen irq chip hierarchy on LoongArch platforms please read the document 69451712e49SCosta Shulyupin Documentation/arch/loongarch/irq-chip-model.rst. 695b2d3e335SHuacai Chen 696dbb15226SJiaxun Yangconfig LOONGSON_LIOINTC 697dbb15226SJiaxun Yang bool "Loongson Local I/O Interrupt Controller" 698dbb15226SJiaxun Yang depends on MACH_LOONGSON64 699dbb15226SJiaxun Yang default y 700dbb15226SJiaxun Yang select IRQ_DOMAIN 701dbb15226SJiaxun Yang select GENERIC_IRQ_CHIP 702dbb15226SJiaxun Yang help 703dbb15226SJiaxun Yang Support for the Loongson Local I/O Interrupt Controller. 704dbb15226SJiaxun Yang 705dd281e1aSHuacai Chenconfig LOONGSON_EIOINTC 706dd281e1aSHuacai Chen bool "Loongson Extend I/O Interrupt Controller" 707dd281e1aSHuacai Chen depends on LOONGARCH 708dd281e1aSHuacai Chen depends on MACH_LOONGSON64 709dd281e1aSHuacai Chen default MACH_LOONGSON64 710dd281e1aSHuacai Chen select IRQ_DOMAIN_HIERARCHY 711dd281e1aSHuacai Chen select GENERIC_IRQ_CHIP 712dd281e1aSHuacai Chen help 713dd281e1aSHuacai Chen Support for the Loongson3 Extend I/O Interrupt Vector Controller. 714dd281e1aSHuacai Chen 715a93f1d90SJiaxun Yangconfig LOONGSON_HTPIC 716a93f1d90SJiaxun Yang bool "Loongson3 HyperTransport PIC Controller" 717987a3e03SHuacai Chen depends on MACH_LOONGSON64 && MIPS 718a93f1d90SJiaxun Yang default y 719a93f1d90SJiaxun Yang select IRQ_DOMAIN 720a93f1d90SJiaxun Yang select GENERIC_IRQ_CHIP 721a93f1d90SJiaxun Yang help 722a93f1d90SJiaxun Yang Support for the Loongson-3 HyperTransport PIC Controller. 723a93f1d90SJiaxun Yang 724818e915fSJiaxun Yangconfig LOONGSON_HTVEC 725987a3e03SHuacai Chen bool "Loongson HyperTransport Interrupt Vector Controller" 726d77aeb5dSIngo Molnar depends on MACH_LOONGSON64 727818e915fSJiaxun Yang default MACH_LOONGSON64 728818e915fSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 729818e915fSJiaxun Yang help 730987a3e03SHuacai Chen Support for the Loongson HyperTransport Interrupt Vector Controller. 731818e915fSJiaxun Yang 732ef8c01ebSJiaxun Yangconfig LOONGSON_PCH_PIC 733ef8c01ebSJiaxun Yang bool "Loongson PCH PIC Controller" 734bcdd75c5SHuacai Chen depends on MACH_LOONGSON64 735ef8c01ebSJiaxun Yang default MACH_LOONGSON64 736ef8c01ebSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 737ef8c01ebSJiaxun Yang select IRQ_FASTEOI_HIERARCHY_HANDLERS 738ef8c01ebSJiaxun Yang help 739ef8c01ebSJiaxun Yang Support for the Loongson PCH PIC Controller. 740ef8c01ebSJiaxun Yang 741632dcc2cSJiaxun Yangconfig LOONGSON_PCH_MSI 742a23df9a4SJiaxun Yang bool "Loongson PCH MSI Controller" 74302308732SHuacai Chen depends on MACH_LOONGSON64 744632dcc2cSJiaxun Yang depends on PCI 745632dcc2cSJiaxun Yang default MACH_LOONGSON64 746632dcc2cSJiaxun Yang select IRQ_DOMAIN_HIERARCHY 7470b3af759SHuacai Chen select IRQ_MSI_LIB 748632dcc2cSJiaxun Yang select PCI_MSI 749632dcc2cSJiaxun Yang help 750632dcc2cSJiaxun Yang Support for the Loongson PCH MSI Controller. 751632dcc2cSJiaxun Yang 752ee73f14eSHuacai Chenconfig LOONGSON_PCH_LPC 753ee73f14eSHuacai Chen bool "Loongson PCH LPC Controller" 754e7ccba77SJianmin Lv depends on LOONGARCH 755ee73f14eSHuacai Chen depends on MACH_LOONGSON64 756e7ccba77SJianmin Lv default MACH_LOONGSON64 757ee73f14eSHuacai Chen select IRQ_DOMAIN_HIERARCHY 758ee73f14eSHuacai Chen help 759ee73f14eSHuacai Chen Support for the Loongson PCH LPC Controller. 760ee73f14eSHuacai Chen 761ad4c938cSMark-PK Tsaiconfig MST_IRQ 762ad4c938cSMark-PK Tsai bool "MStar Interrupt Controller" 76361b0648dSGeert Uytterhoeven depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 764ad4c938cSMark-PK Tsai default ARCH_MEDIATEK 765ad4c938cSMark-PK Tsai select IRQ_DOMAIN 766ad4c938cSMark-PK Tsai select IRQ_DOMAIN_HIERARCHY 767ad4c938cSMark-PK Tsai help 768ad4c938cSMark-PK Tsai Support MStar Interrupt Controller. 769ad4c938cSMark-PK Tsai 770fead4dd4SJonathan Neuschäferconfig WPCM450_AIC 771fead4dd4SJonathan Neuschäfer bool "Nuvoton WPCM450 Advanced Interrupt Controller" 77294bc9420SMarc Zyngier depends on ARCH_WPCM450 773fead4dd4SJonathan Neuschäfer help 774fead4dd4SJonathan Neuschäfer Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 775fead4dd4SJonathan Neuschäfer 776529ea368SThomas Bogendoerferconfig IRQ_IDT3243X 777529ea368SThomas Bogendoerfer bool 778529ea368SThomas Bogendoerfer select GENERIC_IRQ_CHIP 779529ea368SThomas Bogendoerfer select IRQ_DOMAIN 780529ea368SThomas Bogendoerfer 78176cde263SHector Martinconfig APPLE_AIC 78276cde263SHector Martin bool "Apple Interrupt Controller (AIC)" 78376cde263SHector Martin depends on ARM64 7845b44955dSGeert Uytterhoeven depends on ARCH_APPLE || COMPILE_TEST 785c19f8971SMarc Zyngier select GENERIC_IRQ_IPI_MUX 78676cde263SHector Martin help 78776cde263SHector Martin Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 78876cde263SHector Martin such as the M1. 78976cde263SHector Martin 79000fa3461SClaudiu Bezneaconfig MCHP_EIC 79100fa3461SClaudiu Beznea bool "Microchip External Interrupt Controller" 79200fa3461SClaudiu Beznea depends on ARCH_AT91 || COMPILE_TEST 79300fa3461SClaudiu Beznea select IRQ_DOMAIN 79400fa3461SClaudiu Beznea select IRQ_DOMAIN_HIERARCHY 79500fa3461SClaudiu Beznea help 79600fa3461SClaudiu Beznea Support for Microchip External Interrupt Controller. 79700fa3461SClaudiu Beznea 798c6674154SChen Wangconfig SOPHGO_SG2042_MSI 799c6674154SChen Wang bool "Sophgo SG2042 MSI Controller" 800c6674154SChen Wang depends on ARCH_SOPHGO || COMPILE_TEST 801c6674154SChen Wang depends on PCI 802c6674154SChen Wang select IRQ_DOMAIN_HIERARCHY 803c6674154SChen Wang select IRQ_MSI_LIB 804c6674154SChen Wang select PCI_MSI 805c6674154SChen Wang help 806c6674154SChen Wang Support for the Sophgo SG2042 MSI Controller. 807c6674154SChen Wang This on-chip interrupt controller enables MSI sources to be 808c6674154SChen Wang routed to the primary PLIC controller on SoC. 809c6674154SChen Wang 810f7189d93SQin Jianconfig SUNPLUS_SP7021_INTC 811f7189d93SQin Jian bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 812f7189d93SQin Jian default SOC_SP7021 813f7189d93SQin Jian help 814f7189d93SQin Jian Support for the Sunplus SP7021 Interrupt Controller IP core. 815f7189d93SQin Jian SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 816f7189d93SQin Jian chained controller, routing all interrupt source in P-Chip to 817f7189d93SQin Jian the primary controller on C-Chip. 818f7189d93SQin Jian 81901493855SJonathan Neuschäferendmenu 820