1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 select IRQ_MSI_IOMMU 32 33config GIC_NON_BANKED 34 bool 35 36config ARM_GIC_V3 37 bool 38 select IRQ_DOMAIN_HIERARCHY 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 40 select HAVE_ARM_SMCCC_DISCOVERY 41 select IRQ_MSI_IOMMU 42 43config ARM_GIC_ITS_PARENT 44 bool 45 46config ARM_GIC_V3_ITS 47 bool 48 select GENERIC_MSI_IRQ 49 select IRQ_MSI_LIB 50 select ARM_GIC_ITS_PARENT 51 default ARM_GIC_V3 52 select IRQ_MSI_IOMMU 53 54config ARM_GIC_V3_ITS_FSL_MC 55 bool 56 depends on ARM_GIC_V3_ITS 57 depends on FSL_MC_BUS 58 default ARM_GIC_V3_ITS 59 60config ARM_GIC_V5 61 bool 62 select IRQ_DOMAIN_HIERARCHY 63 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 64 select GENERIC_MSI_IRQ 65 select IRQ_MSI_LIB 66 select ARM_GIC_ITS_PARENT 67 68config ARM_NVIC 69 bool 70 select IRQ_DOMAIN_HIERARCHY 71 select GENERIC_IRQ_CHIP 72 73config ARM_VIC 74 bool 75 select IRQ_DOMAIN 76 77config ARM_VIC_NR 78 int 79 default 4 if ARCH_S5PV210 80 default 2 81 depends on ARM_VIC 82 help 83 The maximum number of VICs available in the system, for 84 power management. 85 86config IRQ_MSI_LIB 87 bool 88 select GENERIC_MSI_IRQ 89 90config ARMADA_370_XP_IRQ 91 bool 92 select GENERIC_IRQ_CHIP 93 select PCI_MSI if PCI 94 select IRQ_MSI_LIB if PCI 95 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 96 97config ALPINE_MSI 98 bool 99 depends on PCI 100 select PCI_MSI 101 select IRQ_MSI_LIB 102 select GENERIC_IRQ_CHIP 103 104config AL_FIC 105 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 106 depends on OF 107 depends on HAS_IOMEM 108 select GENERIC_IRQ_CHIP 109 select IRQ_DOMAIN 110 help 111 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 112 113config ATMEL_AIC_IRQ 114 bool 115 select GENERIC_IRQ_CHIP 116 select IRQ_DOMAIN 117 select SPARSE_IRQ 118 119config ATMEL_AIC5_IRQ 120 bool 121 select GENERIC_IRQ_CHIP 122 select IRQ_DOMAIN 123 select SPARSE_IRQ 124 125config I8259 126 bool 127 select IRQ_DOMAIN 128 129config BCM2712_MIP 130 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 131 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 132 default m if ARCH_BRCMSTB || ARCH_BCM2835 133 depends on ARM_GIC 134 select GENERIC_IRQ_CHIP 135 select IRQ_DOMAIN_HIERARCHY 136 select GENERIC_MSI_IRQ 137 select IRQ_MSI_LIB 138 help 139 Enable support for the Broadcom BCM2712 MSI-X target peripheral 140 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 141 Raspberry Pi 5. 142 143 If unsure say n. 144 145config BCM6345_L1_IRQ 146 bool 147 select GENERIC_IRQ_CHIP 148 select IRQ_DOMAIN 149 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 150 151config BCM7038_L1_IRQ 152 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 153 depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 154 default ARCH_BRCMSTB || BMIPS_GENERIC 155 select GENERIC_IRQ_CHIP 156 select IRQ_DOMAIN 157 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 158 159config BCM7120_L2_IRQ 160 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 161 depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 162 default ARCH_BRCMSTB || BMIPS_GENERIC 163 select GENERIC_IRQ_CHIP 164 select IRQ_DOMAIN 165 166config BRCMSTB_L2_IRQ 167 tristate "Broadcom STB generic L2 interrupt controller driver" 168 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 169 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 170 select GENERIC_IRQ_CHIP 171 select IRQ_DOMAIN 172 173config DAVINCI_CP_INTC 174 bool 175 select GENERIC_IRQ_CHIP 176 select IRQ_DOMAIN 177 178config DW_APB_ICTL 179 bool 180 select GENERIC_IRQ_CHIP 181 select IRQ_DOMAIN_HIERARCHY 182 183config ECONET_EN751221_INTC 184 bool 185 select GENERIC_IRQ_CHIP 186 select IRQ_DOMAIN 187 188config FARADAY_FTINTC010 189 bool 190 select IRQ_DOMAIN 191 select SPARSE_IRQ 192 193config HISILICON_IRQ_MBIGEN 194 bool 195 select ARM_GIC_V3 196 select ARM_GIC_V3_ITS 197 198config IMGPDC_IRQ 199 bool 200 select GENERIC_IRQ_CHIP 201 select IRQ_DOMAIN 202 203config IXP4XX_IRQ 204 bool 205 select IRQ_DOMAIN 206 select SPARSE_IRQ 207 208config LAN966X_OIC 209 tristate "Microchip LAN966x OIC Support" 210 depends on MCHP_LAN966X_PCI || COMPILE_TEST 211 select GENERIC_IRQ_CHIP 212 select IRQ_DOMAIN 213 help 214 Enable support for the LAN966x Outbound Interrupt Controller. 215 This controller is present on the Microchip LAN966x PCI device and 216 maps the internal interrupts sources to PCIe interrupt. 217 218 To compile this driver as a module, choose M here: the module 219 will be called irq-lan966x-oic. 220 221config MADERA_IRQ 222 tristate 223 224config IRQ_MIPS_CPU 225 bool 226 select GENERIC_IRQ_CHIP 227 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 228 select IRQ_DOMAIN 229 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 230 231config CLPS711X_IRQCHIP 232 bool 233 depends on ARCH_CLPS711X 234 select IRQ_DOMAIN 235 select SPARSE_IRQ 236 default y 237 238config OMPIC 239 bool 240 241config OR1K_PIC 242 bool 243 select IRQ_DOMAIN 244 245config OMAP_IRQCHIP 246 bool 247 select GENERIC_IRQ_CHIP 248 select IRQ_DOMAIN 249 250config ORION_IRQCHIP 251 bool 252 select IRQ_DOMAIN 253 254config PIC32_EVIC 255 bool 256 select GENERIC_IRQ_CHIP 257 select IRQ_DOMAIN 258 259config JCORE_AIC 260 bool "J-Core integrated AIC" if COMPILE_TEST 261 depends on OF 262 select IRQ_DOMAIN 263 help 264 Support for the J-Core integrated AIC. 265 266config RDA_INTC 267 bool 268 select IRQ_DOMAIN 269 270config RENESAS_INTC_IRQPIN 271 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 272 select IRQ_DOMAIN 273 help 274 Enable support for the Renesas Interrupt Controller for external 275 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 276 277config RENESAS_IRQC 278 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 279 select GENERIC_IRQ_CHIP 280 select IRQ_DOMAIN 281 help 282 Enable support for the Renesas Interrupt Controller for external 283 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 284 285config RENESAS_RZA1_IRQC 286 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 287 select IRQ_DOMAIN_HIERARCHY 288 help 289 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 290 to 8 external interrupts with configurable sense select. 291 292config RENESAS_RZG2L_IRQC 293 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 294 select GENERIC_IRQ_CHIP 295 select IRQ_DOMAIN_HIERARCHY 296 help 297 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 298 for external devices. 299 300config RENESAS_RZT2H_ICU 301 bool "Renesas RZ/{T2H,N2H} ICU support" if COMPILE_TEST 302 select GENERIC_IRQ_CHIP 303 select IRQ_DOMAIN_HIERARCHY 304 help 305 Enable support for the Renesas RZ/{T2H,N2H} Interrupt Controller 306 (ICU). 307 308config RENESAS_RZV2H_ICU 309 bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 310 select GENERIC_IRQ_CHIP 311 select IRQ_DOMAIN_HIERARCHY 312 help 313 Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 314 315config SL28CPLD_INTC 316 bool "Kontron sl28cpld IRQ controller" 317 depends on MFD_SL28CPLD=y || COMPILE_TEST 318 select REGMAP_IRQ 319 help 320 Interrupt controller driver for the board management controller 321 found on the Kontron sl28 CPLD. 322 323config ST_IRQCHIP 324 bool 325 select REGMAP 326 select MFD_SYSCON 327 help 328 Enables SysCfg Controlled IRQs on STi based platforms. 329 330config SUN4I_INTC 331 bool 332 333config SUN6I_R_INTC 334 bool 335 select IRQ_DOMAIN_HIERARCHY 336 select IRQ_FASTEOI_HIERARCHY_HANDLERS 337 338config SUNXI_NMI_INTC 339 bool 340 select GENERIC_IRQ_CHIP 341 342config TB10X_IRQC 343 bool 344 select IRQ_DOMAIN 345 select GENERIC_IRQ_CHIP 346 347config TS4800_IRQ 348 tristate "TS-4800 IRQ controller" 349 select IRQ_DOMAIN 350 depends on HAS_IOMEM 351 depends on SOC_IMX51 || COMPILE_TEST 352 help 353 Support for the TS-4800 FPGA IRQ controller 354 355config VERSATILE_FPGA_IRQ 356 bool 357 select IRQ_DOMAIN 358 359config VERSATILE_FPGA_IRQ_NR 360 int 361 default 4 362 depends on VERSATILE_FPGA_IRQ 363 364config XTENSA_MX 365 bool 366 select IRQ_DOMAIN 367 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 368 369config XILINX_INTC 370 bool "Xilinx Interrupt Controller IP" 371 depends on OF_ADDRESS 372 select IRQ_DOMAIN 373 help 374 Support for the Xilinx Interrupt Controller IP core. 375 This is used as a primary controller with MicroBlaze and can also 376 be used as a secondary chained controller on other platforms. 377 378config IRQ_CROSSBAR 379 bool 380 help 381 Support for a CROSSBAR ip that precedes the main interrupt controller. 382 The primary irqchip invokes the crossbar's callback which inturn allocates 383 a free irq and configures the IP. Thus the peripheral interrupts are 384 routed to one of the free irqchip interrupt lines. 385 386config KEYSTONE_IRQ 387 tristate "Keystone 2 IRQ controller IP" 388 depends on ARCH_KEYSTONE 389 help 390 Support for Texas Instruments Keystone 2 IRQ controller IP which 391 is part of the Keystone 2 IPC mechanism 392 393config MIPS_GIC 394 bool 395 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 396 select GENERIC_IRQ_IPI if SMP 397 select IRQ_DOMAIN_HIERARCHY 398 select MIPS_CM 399 400config INGENIC_IRQ 401 bool 402 depends on MACH_INGENIC 403 default y 404 405config INGENIC_TCU_IRQ 406 bool "Ingenic JZ47xx TCU interrupt controller" 407 default MACH_INGENIC 408 depends on MIPS || COMPILE_TEST 409 select MFD_SYSCON 410 select GENERIC_IRQ_CHIP 411 help 412 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 413 JZ47xx SoCs. 414 415 If unsure, say N. 416 417config IMX_GPCV2 418 bool 419 select IRQ_DOMAIN 420 help 421 Enables the wakeup IRQs for IMX platforms with GPCv2 block 422 423config IRQ_MXS 424 def_bool y if MACH_ASM9260 || ARCH_MXS 425 select IRQ_DOMAIN 426 select STMP_DEVICE 427 428config MSCC_OCELOT_IRQ 429 bool 430 select IRQ_DOMAIN 431 select GENERIC_IRQ_CHIP 432 433config MVEBU_GICP 434 select IRQ_MSI_LIB 435 bool 436 437config MVEBU_ICU 438 bool 439 440config MVEBU_ODMI 441 bool 442 select IRQ_MSI_LIB 443 select GENERIC_MSI_IRQ 444 445config MVEBU_PIC 446 bool 447 448config MVEBU_SEI 449 bool 450 451config LS_EXTIRQ 452 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 453 select MFD_SYSCON 454 455config LS_SCFG_MSI 456 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 457 select IRQ_MSI_IOMMU 458 depends on PCI_MSI 459 select IRQ_MSI_LIB 460 461config STM32MP_EXTI 462 tristate "STM32MP extended interrupts and event controller" 463 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 464 default ARCH_STM32 && !ARM_SINGLE_ARMV7M 465 select IRQ_DOMAIN_HIERARCHY 466 select GENERIC_IRQ_CHIP 467 help 468 Support STM32MP EXTI (extended interrupts and event) controller. 469 470config STM32_EXTI 471 bool 472 select IRQ_DOMAIN 473 select GENERIC_IRQ_CHIP 474 475config QCOM_IRQ_COMBINER 476 bool "QCOM IRQ combiner support" 477 depends on ARCH_QCOM && ACPI 478 select IRQ_DOMAIN_HIERARCHY 479 help 480 Say yes here to add support for the IRQ combiner devices embedded 481 in Qualcomm Technologies chips. 482 483config IRQ_UNIPHIER_AIDET 484 bool "UniPhier AIDET support" if COMPILE_TEST 485 depends on ARCH_UNIPHIER || COMPILE_TEST 486 default ARCH_UNIPHIER 487 select IRQ_DOMAIN_HIERARCHY 488 help 489 Support for the UniPhier AIDET (ARM Interrupt Detector). 490 491config MESON_IRQ_GPIO 492 tristate "Meson GPIO Interrupt Multiplexer" 493 depends on ARCH_MESON || COMPILE_TEST 494 default ARCH_MESON 495 select IRQ_DOMAIN_HIERARCHY 496 help 497 Support Meson SoC Family GPIO Interrupt Multiplexer 498 499config GOLDFISH_PIC 500 bool "Goldfish programmable interrupt controller" 501 depends on MIPS && (GOLDFISH || COMPILE_TEST) 502 select GENERIC_IRQ_CHIP 503 select IRQ_DOMAIN 504 help 505 Say yes here to enable Goldfish interrupt controller driver used 506 for Goldfish based virtual platforms. 507 508config QCOM_PDC 509 tristate "QCOM PDC" 510 depends on ARCH_QCOM 511 select IRQ_DOMAIN_HIERARCHY 512 help 513 Power Domain Controller driver to manage and configure wakeup 514 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 515 516config QCOM_MPM 517 tristate "QCOM MPM" 518 depends on ARCH_QCOM 519 depends on MAILBOX 520 select IRQ_DOMAIN_HIERARCHY 521 help 522 MSM Power Manager driver to manage and configure wakeup 523 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 524 525config CSKY_MPINTC 526 bool 527 depends on CSKY 528 help 529 Say yes here to enable C-SKY SMP interrupt controller driver used 530 for C-SKY SMP system. 531 In fact it's not mmio map in hardware and it uses ld/st to visit the 532 controller's register inside CPU. 533 534config CSKY_APB_INTC 535 bool "C-SKY APB Interrupt Controller" 536 depends on CSKY 537 help 538 Say yes here to enable C-SKY APB interrupt controller driver used 539 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 540 the controller's register. 541 542config IMX_IRQSTEER 543 bool "i.MX IRQSTEER support" 544 depends on ARCH_MXC || COMPILE_TEST 545 default ARCH_MXC 546 select IRQ_DOMAIN 547 help 548 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 549 550config IMX_INTMUX 551 bool "i.MX INTMUX support" if COMPILE_TEST 552 default y if ARCH_MXC 553 select IRQ_DOMAIN 554 help 555 Support for the i.MX INTMUX interrupt multiplexer. 556 557config IMX_MU_MSI 558 tristate "i.MX MU used as MSI controller" 559 depends on OF && HAS_IOMEM 560 depends on ARCH_MXC || COMPILE_TEST 561 depends on ARM || ARM64 562 default m if ARCH_MXC 563 select IRQ_DOMAIN 564 select IRQ_DOMAIN_HIERARCHY 565 select GENERIC_MSI_IRQ 566 select IRQ_MSI_LIB 567 help 568 Provide a driver for the i.MX Messaging Unit block used as a 569 CPU-to-CPU MSI controller. This requires a specially crafted DT 570 to make use of this driver. 571 572 If unsure, say N 573 574config LS1X_IRQ 575 bool "Loongson-1 Interrupt Controller" 576 depends on MACH_LOONGSON32 577 default y 578 select IRQ_DOMAIN 579 select GENERIC_IRQ_CHIP 580 help 581 Support for the Loongson-1 platform Interrupt Controller. 582 583config TI_SCI_INTR_IRQCHIP 584 tristate "TI SCI INTR Interrupt Controller" 585 depends on TI_SCI_PROTOCOL 586 depends on ARCH_K3 || COMPILE_TEST 587 select IRQ_DOMAIN_HIERARCHY 588 help 589 This enables the irqchip driver support for K3 Interrupt router 590 over TI System Control Interface available on some new TI's SoCs. 591 If you wish to use interrupt router irq resources managed by the 592 TI System Controller, say Y here. Otherwise, say N. 593 594config TI_SCI_INTA_IRQCHIP 595 tristate "TI SCI INTA Interrupt Controller" 596 depends on TI_SCI_PROTOCOL 597 depends on ARCH_K3 || (COMPILE_TEST && ARM64) 598 select IRQ_DOMAIN_HIERARCHY 599 select TI_SCI_INTA_MSI_DOMAIN 600 help 601 This enables the irqchip driver support for K3 Interrupt aggregator 602 over TI System Control Interface available on some new TI's SoCs. 603 If you wish to use interrupt aggregator irq resources managed by the 604 TI System Controller, say Y here. Otherwise, say N. 605 606config TI_PRUSS_INTC 607 tristate 608 depends on TI_PRUSS 609 default TI_PRUSS 610 select IRQ_DOMAIN 611 help 612 This enables support for the PRU-ICSS Local Interrupt Controller 613 present within a PRU-ICSS subsystem present on various TI SoCs. 614 The PRUSS INTC enables various interrupts to be routed to multiple 615 different processors within the SoC. 616 617config RISCV_INTC 618 bool 619 depends on RISCV 620 select IRQ_DOMAIN_HIERARCHY 621 622config RISCV_APLIC 623 bool 624 depends on RISCV 625 select IRQ_DOMAIN_HIERARCHY 626 627config RISCV_APLIC_MSI 628 bool 629 depends on RISCV_APLIC 630 select GENERIC_MSI_IRQ 631 default RISCV_APLIC 632 633config RISCV_IMSIC 634 bool 635 depends on RISCV 636 select IRQ_DOMAIN_HIERARCHY 637 select GENERIC_IRQ_MATRIX_ALLOCATOR 638 select GENERIC_MSI_IRQ 639 select IRQ_MSI_LIB 640 641config RISCV_RPMI_SYSMSI 642 bool 643 depends on RISCV && MAILBOX 644 select IRQ_DOMAIN_HIERARCHY 645 select GENERIC_MSI_IRQ 646 default RISCV 647 648config SIFIVE_PLIC 649 bool 650 depends on RISCV 651 select IRQ_DOMAIN_HIERARCHY 652 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 653 654config STARFIVE_JH8100_INTC 655 bool "StarFive JH8100 External Interrupt Controller" 656 depends on ARCH_STARFIVE || COMPILE_TEST 657 default ARCH_STARFIVE 658 select IRQ_DOMAIN_HIERARCHY 659 help 660 This enables support for the INTC chip found in StarFive JH8100 661 SoC. 662 663 If you don't know what to do here, say Y. 664 665config ACLINT_SSWI 666 bool "RISC-V ACLINT S-mode IPI Interrupt Controller" 667 depends on RISCV 668 depends on SMP 669 select IRQ_DOMAIN_HIERARCHY 670 select GENERIC_IRQ_IPI_MUX 671 help 672 This enables support for variants of the RISC-V ACLINT-SSWI device. 673 Supported variants are: 674 - T-HEAD, with compatible "thead,c900-aclint-sswi" 675 - MIPS P8700, with compatible "mips,p8700-aclint-sswi" 676 677 If you don't know what to do here, say Y. 678 679# Backwards compatibility so oldconfig does not drop it. 680config THEAD_C900_ACLINT_SSWI 681 bool 682 select ACLINT_SSWI 683 684config EXYNOS_IRQ_COMBINER 685 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 686 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 687 help 688 Say yes here to add support for the IRQ combiner devices embedded 689 in Samsung Exynos chips. 690 691config IRQ_LOONGARCH_CPU 692 bool 693 select GENERIC_IRQ_CHIP 694 select IRQ_DOMAIN 695 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 696 select LOONGSON_HTVEC 697 select LOONGSON_LIOINTC 698 select LOONGSON_EIOINTC 699 select LOONGSON_PCH_PIC 700 select LOONGSON_PCH_MSI 701 select LOONGSON_PCH_LPC 702 help 703 Support for the LoongArch CPU Interrupt Controller. For details of 704 irq chip hierarchy on LoongArch platforms please read the document 705 Documentation/arch/loongarch/irq-chip-model.rst. 706 707config LOONGSON_LIOINTC 708 bool "Loongson Local I/O Interrupt Controller" 709 depends on MACH_LOONGSON64 || LOONGARCH 710 default y 711 select IRQ_DOMAIN 712 select GENERIC_IRQ_CHIP 713 help 714 Support for the Loongson Local I/O Interrupt Controller. 715 716config LOONGSON_EIOINTC 717 bool "Loongson Extend I/O Interrupt Controller" 718 depends on LOONGARCH 719 default MACH_LOONGSON64 720 select IRQ_DOMAIN_HIERARCHY 721 select GENERIC_IRQ_CHIP 722 help 723 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 724 725config LOONGSON_HTPIC 726 bool "Loongson3 HyperTransport PIC Controller" 727 depends on MACH_LOONGSON64 && MIPS 728 default y 729 select IRQ_DOMAIN 730 select GENERIC_IRQ_CHIP 731 help 732 Support for the Loongson-3 HyperTransport PIC Controller. 733 734config LOONGSON_HTVEC 735 bool "Loongson HyperTransport Interrupt Vector Controller" 736 depends on MACH_LOONGSON64 || LOONGARCH 737 default MACH_LOONGSON64 738 select IRQ_DOMAIN_HIERARCHY 739 help 740 Support for the Loongson HyperTransport Interrupt Vector Controller. 741 742config LOONGSON_PCH_PIC 743 bool "Loongson PCH PIC Controller" 744 depends on MACH_LOONGSON64 || LOONGARCH 745 default MACH_LOONGSON64 746 select IRQ_DOMAIN_HIERARCHY 747 select IRQ_FASTEOI_HIERARCHY_HANDLERS 748 help 749 Support for the Loongson PCH PIC Controller. 750 751config LOONGSON_PCH_MSI 752 bool "Loongson PCH MSI Controller" 753 depends on MACH_LOONGSON64 || LOONGARCH 754 depends on PCI 755 default MACH_LOONGSON64 756 select IRQ_DOMAIN_HIERARCHY 757 select IRQ_MSI_LIB 758 select PCI_MSI 759 help 760 Support for the Loongson PCH MSI Controller. 761 762config LOONGSON_PCH_LPC 763 bool "Loongson PCH LPC Controller" 764 depends on LOONGARCH 765 depends on MACH_LOONGSON64 || LOONGARCH 766 default MACH_LOONGSON64 767 select IRQ_DOMAIN_HIERARCHY 768 help 769 Support for the Loongson PCH LPC Controller. 770 771config MST_IRQ 772 bool "MStar Interrupt Controller" 773 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 774 default ARCH_MEDIATEK 775 select IRQ_DOMAIN 776 select IRQ_DOMAIN_HIERARCHY 777 help 778 Support MStar Interrupt Controller. 779 780config WPCM450_AIC 781 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 782 depends on ARCH_WPCM450 783 help 784 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 785 786config IRQ_IDT3243X 787 bool 788 select GENERIC_IRQ_CHIP 789 select IRQ_DOMAIN 790 791config APPLE_AIC 792 bool "Apple Interrupt Controller (AIC)" 793 depends on ARM64 794 depends on ARCH_APPLE || COMPILE_TEST 795 select GENERIC_IRQ_IPI_MUX 796 help 797 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 798 such as the M1. 799 800config MCHP_EIC 801 bool "Microchip External Interrupt Controller" 802 depends on ARCH_AT91 || COMPILE_TEST 803 select IRQ_DOMAIN 804 select IRQ_DOMAIN_HIERARCHY 805 help 806 Support for Microchip External Interrupt Controller. 807 808config SOPHGO_SG2042_MSI 809 bool "Sophgo SG2042 MSI Controller" 810 depends on ARCH_SOPHGO || COMPILE_TEST 811 depends on PCI 812 select IRQ_DOMAIN_HIERARCHY 813 select IRQ_MSI_LIB 814 select PCI_MSI 815 help 816 Support for the Sophgo SG2042 MSI Controller. 817 This on-chip interrupt controller enables MSI sources to be 818 routed to the primary PLIC controller on SoC. 819 820config SUNPLUS_SP7021_INTC 821 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 822 default SOC_SP7021 823 help 824 Support for the Sunplus SP7021 Interrupt Controller IP core. 825 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 826 chained controller, routing all interrupt source in P-Chip to 827 the primary controller on C-Chip. 828 829endmenu 830