1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 select IRQ_MSI_IOMMU 32 33config GIC_NON_BANKED 34 bool 35 36config ARM_GIC_V3 37 bool 38 select IRQ_DOMAIN_HIERARCHY 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 40 select HAVE_ARM_SMCCC_DISCOVERY 41 select IRQ_MSI_IOMMU 42 43config ARM_GIC_ITS_PARENT 44 bool 45 46config ARM_GIC_V3_ITS 47 bool 48 select GENERIC_MSI_IRQ 49 select IRQ_MSI_LIB 50 select ARM_GIC_ITS_PARENT 51 default ARM_GIC_V3 52 select IRQ_MSI_IOMMU 53 54config ARM_GIC_V5 55 bool 56 select IRQ_DOMAIN_HIERARCHY 57 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 58 select GENERIC_MSI_IRQ 59 select IRQ_MSI_LIB 60 select ARM_GIC_ITS_PARENT 61 62config ARM_NVIC 63 bool 64 select IRQ_DOMAIN_HIERARCHY 65 select GENERIC_IRQ_CHIP 66 67config ARM_VIC 68 bool 69 select IRQ_DOMAIN 70 71config ARM_VIC_NR 72 int 73 default 4 if ARCH_S5PV210 74 default 2 75 depends on ARM_VIC 76 help 77 The maximum number of VICs available in the system, for 78 power management. 79 80config IRQ_MSI_LIB 81 bool 82 select GENERIC_MSI_IRQ 83 84config ARMADA_370_XP_IRQ 85 bool 86 select GENERIC_IRQ_CHIP 87 select PCI_MSI if PCI 88 select IRQ_MSI_LIB if PCI 89 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 90 91config ALPINE_MSI 92 bool 93 depends on PCI 94 select PCI_MSI 95 select IRQ_MSI_LIB 96 select GENERIC_IRQ_CHIP 97 98config AL_FIC 99 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 100 depends on OF 101 depends on HAS_IOMEM 102 select GENERIC_IRQ_CHIP 103 select IRQ_DOMAIN 104 help 105 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 106 107config ASPEED_AST2700_INTC 108 bool "ASPEED AST2700 Interrupt Controller support" 109 depends on OF 110 depends on ARCH_ASPEED || COMPILE_TEST 111 select IRQ_DOMAIN_HIERARCHY 112 help 113 Enable support for the ASPEED AST2700 interrupt controller. 114 This driver handles interrupt, routing and merged interrupt 115 sources to upstream parent interrupt controllers. 116 117 If unsure, say N. 118 119config ASPEED_AST2700_INTC_TEST 120 bool "Tests for the ASPEED AST2700 Interrupt Controller" 121 depends on ASPEED_AST2700_INTC && KUNIT=y 122 default KUNIT_ALL_TESTS 123 help 124 Enable KUnit tests for AST2700 INTC route resolution. 125 The tests exercise error handling and route selection paths. 126 This option is intended for test builds. 127 128 If unsure, say N. 129 130config ATMEL_AIC_IRQ 131 bool 132 select GENERIC_IRQ_CHIP 133 select IRQ_DOMAIN 134 select SPARSE_IRQ 135 136config ATMEL_AIC5_IRQ 137 bool 138 select GENERIC_IRQ_CHIP 139 select IRQ_DOMAIN 140 select SPARSE_IRQ 141 142config I8259 143 bool 144 select IRQ_DOMAIN 145 146config BCM2712_MIP 147 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 148 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 149 default m if ARCH_BRCMSTB || ARCH_BCM2835 150 depends on ARM_GIC 151 select GENERIC_IRQ_CHIP 152 select IRQ_DOMAIN_HIERARCHY 153 select GENERIC_MSI_IRQ 154 select IRQ_MSI_LIB 155 help 156 Enable support for the Broadcom BCM2712 MSI-X target peripheral 157 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 158 Raspberry Pi 5. 159 160 If unsure say n. 161 162config BCM6345_L1_IRQ 163 bool 164 select GENERIC_IRQ_CHIP 165 select IRQ_DOMAIN 166 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 167 168config BCM7038_L1_IRQ 169 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 170 depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 171 default ARCH_BRCMSTB || BMIPS_GENERIC 172 select GENERIC_IRQ_CHIP 173 select IRQ_DOMAIN 174 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 175 176config BCM7120_L2_IRQ 177 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 178 depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 179 default ARCH_BRCMSTB || BMIPS_GENERIC 180 select GENERIC_IRQ_CHIP 181 select IRQ_DOMAIN 182 183config BRCMSTB_L2_IRQ 184 tristate "Broadcom STB generic L2 interrupt controller driver" 185 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 186 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 187 select GENERIC_IRQ_CHIP 188 select IRQ_DOMAIN 189 190config DAVINCI_CP_INTC 191 bool 192 select GENERIC_IRQ_CHIP 193 select IRQ_DOMAIN 194 195config DW_APB_ICTL 196 bool 197 select GENERIC_IRQ_CHIP 198 select IRQ_DOMAIN_HIERARCHY 199 200config ECONET_EN751221_INTC 201 bool 202 select GENERIC_IRQ_CHIP 203 select IRQ_DOMAIN 204 205config FARADAY_FTINTC010 206 bool 207 select IRQ_DOMAIN 208 select SPARSE_IRQ 209 210config HISILICON_IRQ_MBIGEN 211 bool 212 select ARM_GIC_V3 213 select ARM_GIC_V3_ITS 214 215config IXP4XX_IRQ 216 bool 217 select IRQ_DOMAIN 218 select SPARSE_IRQ 219 220config LAN966X_OIC 221 tristate "Microchip LAN966x OIC Support" 222 depends on MCHP_LAN966X_PCI || COMPILE_TEST 223 select GENERIC_IRQ_CHIP 224 select IRQ_DOMAIN 225 help 226 Enable support for the LAN966x Outbound Interrupt Controller. 227 This controller is present on the Microchip LAN966x PCI device and 228 maps the internal interrupts sources to PCIe interrupt. 229 230 To compile this driver as a module, choose M here: the module 231 will be called irq-lan966x-oic. 232 233config MADERA_IRQ 234 tristate 235 236config IRQ_MIPS_CPU 237 bool 238 select GENERIC_IRQ_CHIP 239 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 240 select IRQ_DOMAIN 241 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 242 243config CLPS711X_IRQCHIP 244 bool 245 depends on ARCH_CLPS711X 246 select IRQ_DOMAIN 247 select SPARSE_IRQ 248 default y 249 250config OMPIC 251 bool 252 253config OR1K_PIC 254 bool 255 select IRQ_DOMAIN 256 257config OMAP_IRQCHIP 258 bool 259 select GENERIC_IRQ_CHIP 260 select IRQ_DOMAIN 261 262config ORION_IRQCHIP 263 bool 264 select IRQ_DOMAIN 265 266config PIC32_EVIC 267 def_bool MACH_PIC32 || COMPILE_TEST 268 select GENERIC_IRQ_CHIP 269 select IRQ_DOMAIN 270 help 271 Enable support for the interrupt controller on the Microchip PIC32 272 family of platforms. 273 274config JCORE_AIC 275 bool "J-Core integrated AIC" if COMPILE_TEST 276 depends on OF 277 select IRQ_DOMAIN 278 help 279 Support for the J-Core integrated AIC. 280 281config RDA_INTC 282 bool 283 select IRQ_DOMAIN 284 285config RENESAS_INTC_IRQPIN 286 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 287 select IRQ_DOMAIN 288 help 289 Enable support for the Renesas Interrupt Controller for external 290 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 291 292config RENESAS_IRQC 293 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 294 select GENERIC_IRQ_CHIP 295 select IRQ_DOMAIN 296 help 297 Enable support for the Renesas Interrupt Controller for external 298 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 299 300config RENESAS_RZA1_IRQC 301 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 302 select IRQ_DOMAIN_HIERARCHY 303 help 304 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 305 to 8 external interrupts with configurable sense select. 306 307config RENESAS_RZG2L_IRQC 308 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 309 select GENERIC_IRQ_CHIP 310 select IRQ_DOMAIN_HIERARCHY 311 help 312 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 313 for external devices. 314 315config RENESAS_RZT2H_ICU 316 bool "Renesas RZ/{T2H,N2H} ICU support" if COMPILE_TEST 317 select GENERIC_IRQ_CHIP 318 select IRQ_DOMAIN_HIERARCHY 319 help 320 Enable support for the Renesas RZ/{T2H,N2H} Interrupt Controller 321 (ICU). 322 323config RENESAS_RZV2H_ICU 324 bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 325 select GENERIC_IRQ_CHIP 326 select IRQ_DOMAIN_HIERARCHY 327 help 328 Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 329 330config SL28CPLD_INTC 331 bool "Kontron sl28cpld IRQ controller" 332 depends on MFD_SL28CPLD=y || COMPILE_TEST 333 select REGMAP_IRQ 334 help 335 Interrupt controller driver for the board management controller 336 found on the Kontron sl28 CPLD. 337 338config ST_IRQCHIP 339 bool 340 select REGMAP 341 select MFD_SYSCON 342 help 343 Enables SysCfg Controlled IRQs on STi based platforms. 344 345config SUN4I_INTC 346 bool 347 348config SUN6I_R_INTC 349 bool 350 select IRQ_DOMAIN_HIERARCHY 351 select IRQ_FASTEOI_HIERARCHY_HANDLERS 352 353config SUNXI_NMI_INTC 354 bool 355 select GENERIC_IRQ_CHIP 356 357config TB10X_IRQC 358 bool 359 select IRQ_DOMAIN 360 select GENERIC_IRQ_CHIP 361 362config TS4800_IRQ 363 tristate "TS-4800 IRQ controller" 364 select IRQ_DOMAIN 365 depends on HAS_IOMEM 366 depends on SOC_IMX51 || COMPILE_TEST 367 help 368 Support for the TS-4800 FPGA IRQ controller 369 370config VERSATILE_FPGA_IRQ 371 bool 372 select IRQ_DOMAIN 373 374config VERSATILE_FPGA_IRQ_NR 375 int 376 default 4 377 depends on VERSATILE_FPGA_IRQ 378 379config XTENSA_MX 380 bool 381 select IRQ_DOMAIN 382 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 383 384config XILINX_INTC 385 bool "Xilinx Interrupt Controller IP" 386 depends on OF_ADDRESS 387 select IRQ_DOMAIN 388 help 389 Support for the Xilinx Interrupt Controller IP core. 390 This is used as a primary controller with MicroBlaze and can also 391 be used as a secondary chained controller on other platforms. 392 393config IRQ_CROSSBAR 394 bool 395 help 396 Support for a CROSSBAR ip that precedes the main interrupt controller. 397 The primary irqchip invokes the crossbar's callback which inturn allocates 398 a free irq and configures the IP. Thus the peripheral interrupts are 399 routed to one of the free irqchip interrupt lines. 400 401config KEYSTONE_IRQ 402 tristate "Keystone 2 IRQ controller IP" 403 depends on ARCH_KEYSTONE 404 help 405 Support for Texas Instruments Keystone 2 IRQ controller IP which 406 is part of the Keystone 2 IPC mechanism 407 408config MIPS_GIC 409 bool 410 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 411 select GENERIC_IRQ_IPI if SMP 412 select IRQ_DOMAIN_HIERARCHY 413 select MIPS_CM 414 415config INGENIC_IRQ 416 bool 417 depends on MACH_INGENIC 418 default y 419 420config INGENIC_TCU_IRQ 421 bool "Ingenic JZ47xx TCU interrupt controller" 422 default MACH_INGENIC 423 depends on MIPS || COMPILE_TEST 424 select MFD_SYSCON 425 select GENERIC_IRQ_CHIP 426 help 427 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 428 JZ47xx SoCs. 429 430 If unsure, say N. 431 432config IMX_GPCV2 433 bool 434 select IRQ_DOMAIN 435 help 436 Enables the wakeup IRQs for IMX platforms with GPCv2 block 437 438config IRQ_MXS 439 def_bool y if MACH_ASM9260 || ARCH_MXS 440 select IRQ_DOMAIN 441 select STMP_DEVICE 442 443config MSCC_OCELOT_IRQ 444 bool 445 select IRQ_DOMAIN 446 select GENERIC_IRQ_CHIP 447 448config MVEBU_GICP 449 select IRQ_MSI_LIB 450 bool 451 452config MVEBU_ICU 453 bool 454 455config MVEBU_ODMI 456 bool 457 select IRQ_MSI_LIB 458 select GENERIC_MSI_IRQ 459 460config MVEBU_PIC 461 bool 462 463config MVEBU_SEI 464 bool 465 466config LS_EXTIRQ 467 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 468 select MFD_SYSCON 469 470config LS_SCFG_MSI 471 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 472 select IRQ_MSI_IOMMU 473 depends on PCI_MSI 474 select IRQ_MSI_LIB 475 476config STM32MP_EXTI 477 tristate "STM32MP extended interrupts and event controller" 478 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 479 default ARCH_STM32 && !ARM_SINGLE_ARMV7M 480 select IRQ_DOMAIN_HIERARCHY 481 select GENERIC_IRQ_CHIP 482 help 483 Support STM32MP EXTI (extended interrupts and event) controller. 484 485config STM32_EXTI 486 bool 487 select IRQ_DOMAIN 488 select GENERIC_IRQ_CHIP 489 490config QCOM_IRQ_COMBINER 491 bool "Qualcomm IRQ combiner support" 492 depends on ARCH_QCOM && ACPI 493 select IRQ_DOMAIN_HIERARCHY 494 help 495 Say yes here to add support for the IRQ combiner devices embedded 496 in Qualcomm Technologies chips. 497 498config IRQ_UNIPHIER_AIDET 499 bool "UniPhier AIDET support" if COMPILE_TEST 500 depends on ARCH_UNIPHIER || COMPILE_TEST 501 default ARCH_UNIPHIER 502 select IRQ_DOMAIN_HIERARCHY 503 help 504 Support for the UniPhier AIDET (ARM Interrupt Detector). 505 506config MESON_IRQ_GPIO 507 tristate "Meson GPIO Interrupt Multiplexer" 508 depends on ARCH_MESON || COMPILE_TEST 509 default ARCH_MESON 510 select IRQ_DOMAIN_HIERARCHY 511 help 512 Support Meson SoC Family GPIO Interrupt Multiplexer 513 514config GOLDFISH_PIC 515 bool "Goldfish programmable interrupt controller" 516 depends on MIPS && (GOLDFISH || COMPILE_TEST) 517 select GENERIC_IRQ_CHIP 518 select IRQ_DOMAIN 519 help 520 Say yes here to enable Goldfish interrupt controller driver used 521 for Goldfish based virtual platforms. 522 523config QCOM_PDC 524 tristate "Qualcomm PDC" 525 depends on ARCH_QCOM 526 select IRQ_DOMAIN_HIERARCHY 527 help 528 Power Domain Controller driver to manage and configure wakeup 529 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 530 531config QCOM_MPM 532 tristate "Qualcomm MPM" 533 depends on ARCH_QCOM 534 depends on MAILBOX 535 select IRQ_DOMAIN_HIERARCHY 536 help 537 MSM Power Manager driver to manage and configure wakeup 538 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 539 540config CSKY_MPINTC 541 bool 542 depends on CSKY 543 help 544 Say yes here to enable C-SKY SMP interrupt controller driver used 545 for C-SKY SMP system. 546 In fact it's not mmio map in hardware and it uses ld/st to visit the 547 controller's register inside CPU. 548 549config CSKY_APB_INTC 550 bool "C-SKY APB Interrupt Controller" 551 depends on CSKY 552 help 553 Say yes here to enable C-SKY APB interrupt controller driver used 554 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 555 the controller's register. 556 557config IMX_IRQSTEER 558 bool "i.MX IRQSTEER support" 559 depends on ARCH_MXC || ARCH_S32 || COMPILE_TEST 560 default y if ARCH_MXC || ARCH_S32 561 select IRQ_DOMAIN 562 help 563 Support for the i.MX and S32 IRQSTEER interrupt multiplexer/remapper. 564 565config IMX_INTMUX 566 bool "i.MX INTMUX support" if COMPILE_TEST 567 default y if ARCH_MXC 568 select IRQ_DOMAIN 569 help 570 Support for the i.MX INTMUX interrupt multiplexer. 571 572config IMX_MU_MSI 573 tristate "i.MX MU used as MSI controller" 574 depends on OF && HAS_IOMEM 575 depends on ARCH_MXC || COMPILE_TEST 576 depends on ARM || ARM64 577 default m if ARCH_MXC 578 select IRQ_DOMAIN 579 select IRQ_DOMAIN_HIERARCHY 580 select GENERIC_MSI_IRQ 581 select IRQ_MSI_LIB 582 help 583 Provide a driver for the i.MX Messaging Unit block used as a 584 CPU-to-CPU MSI controller. This requires a specially crafted DT 585 to make use of this driver. 586 587 If unsure, say N 588 589config LS1X_IRQ 590 bool "Loongson-1 Interrupt Controller" 591 depends on MACH_LOONGSON32 592 default y 593 select IRQ_DOMAIN 594 select GENERIC_IRQ_CHIP 595 help 596 Support for the Loongson-1 platform Interrupt Controller. 597 598config TI_SCI_INTR_IRQCHIP 599 tristate "TI SCI INTR Interrupt Controller" 600 depends on TI_SCI_PROTOCOL 601 depends on ARCH_K3 || COMPILE_TEST 602 select IRQ_DOMAIN_HIERARCHY 603 help 604 This enables the irqchip driver support for K3 Interrupt router 605 over TI System Control Interface available on some new TI's SoCs. 606 If you wish to use interrupt router irq resources managed by the 607 TI System Controller, say Y here. Otherwise, say N. 608 609config TI_SCI_INTA_IRQCHIP 610 tristate "TI SCI INTA Interrupt Controller" 611 depends on TI_SCI_PROTOCOL 612 depends on ARCH_K3 || (COMPILE_TEST && ARM64) 613 select IRQ_DOMAIN_HIERARCHY 614 select TI_SCI_INTA_MSI_DOMAIN 615 help 616 This enables the irqchip driver support for K3 Interrupt aggregator 617 over TI System Control Interface available on some new TI's SoCs. 618 If you wish to use interrupt aggregator irq resources managed by the 619 TI System Controller, say Y here. Otherwise, say N. 620 621config TI_PRUSS_INTC 622 tristate 623 depends on TI_PRUSS 624 default TI_PRUSS 625 select IRQ_DOMAIN 626 help 627 This enables support for the PRU-ICSS Local Interrupt Controller 628 present within a PRU-ICSS subsystem present on various TI SoCs. 629 The PRUSS INTC enables various interrupts to be routed to multiple 630 different processors within the SoC. 631 632config RISCV_INTC 633 bool 634 depends on RISCV 635 select IRQ_DOMAIN_HIERARCHY 636 637config RISCV_APLIC 638 bool 639 depends on RISCV 640 select IRQ_DOMAIN_HIERARCHY 641 642config RISCV_APLIC_MSI 643 bool 644 depends on RISCV_APLIC 645 select GENERIC_MSI_IRQ 646 default RISCV_APLIC 647 648config RISCV_IMSIC 649 bool 650 depends on RISCV 651 select IRQ_DOMAIN_HIERARCHY 652 select GENERIC_IRQ_MATRIX_ALLOCATOR 653 select GENERIC_MSI_IRQ 654 select IRQ_MSI_LIB 655 656config RISCV_RPMI_SYSMSI 657 bool 658 depends on RISCV && MAILBOX 659 select IRQ_DOMAIN_HIERARCHY 660 select GENERIC_MSI_IRQ 661 default RISCV 662 663config SIFIVE_PLIC 664 bool 665 depends on RISCV 666 select IRQ_DOMAIN_HIERARCHY 667 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 668 669config STARFIVE_JHB100_INTC 670 bool "StarFive JHB100 External Interrupt Controller" 671 depends on ARCH_STARFIVE || COMPILE_TEST 672 default ARCH_STARFIVE 673 select IRQ_DOMAIN_HIERARCHY 674 help 675 This enables support for the INTC chip found in StarFive JHB100 676 SoC. 677 678 If you don't know what to do here, say Y. 679 680config ACLINT_SSWI 681 bool "RISC-V ACLINT S-mode IPI Interrupt Controller" 682 depends on RISCV 683 depends on SMP 684 select IRQ_DOMAIN_HIERARCHY 685 select GENERIC_IRQ_IPI_MUX 686 help 687 This enables support for variants of the RISC-V ACLINT-SSWI device. 688 Supported variants are: 689 - T-HEAD, with compatible "thead,c900-aclint-sswi" 690 - MIPS P8700, with compatible "mips,p8700-aclint-sswi" 691 692 If you don't know what to do here, say Y. 693 694# Backwards compatibility so oldconfig does not drop it. 695config THEAD_C900_ACLINT_SSWI 696 bool 697 select ACLINT_SSWI 698 699config EXYNOS_IRQ_COMBINER 700 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 701 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 702 help 703 Say yes here to add support for the IRQ combiner devices embedded 704 in Samsung Exynos chips. 705 706config IRQ_LOONGARCH_CPU 707 bool 708 select GENERIC_IRQ_CHIP 709 select IRQ_DOMAIN 710 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 711 select LOONGSON_HTVEC 712 select LOONGSON_LIOINTC 713 select LOONGSON_EIOINTC 714 select LOONGSON_PCH_PIC 715 select LOONGSON_PCH_MSI 716 select LOONGSON_PCH_LPC 717 help 718 Support for the LoongArch CPU Interrupt Controller. For details of 719 irq chip hierarchy on LoongArch platforms please read the document 720 Documentation/arch/loongarch/irq-chip-model.rst. 721 722config LOONGSON_LIOINTC 723 bool "Loongson Local I/O Interrupt Controller" 724 depends on MACH_LOONGSON64 || LOONGARCH 725 default y 726 select IRQ_DOMAIN 727 select GENERIC_IRQ_CHIP 728 help 729 Support for the Loongson Local I/O Interrupt Controller. 730 731config LOONGSON_EIOINTC 732 bool "Loongson Extend I/O Interrupt Controller" 733 depends on LOONGARCH 734 default MACH_LOONGSON64 735 select IRQ_DOMAIN_HIERARCHY 736 select GENERIC_IRQ_CHIP 737 help 738 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 739 740config LOONGSON_HTPIC 741 bool "Loongson3 HyperTransport PIC Controller" 742 depends on MACH_LOONGSON64 && MIPS 743 default y 744 select IRQ_DOMAIN 745 select GENERIC_IRQ_CHIP 746 help 747 Support for the Loongson-3 HyperTransport PIC Controller. 748 749config LOONGSON_HTVEC 750 bool "Loongson HyperTransport Interrupt Vector Controller" 751 depends on MACH_LOONGSON64 || LOONGARCH 752 default MACH_LOONGSON64 753 select IRQ_DOMAIN_HIERARCHY 754 help 755 Support for the Loongson HyperTransport Interrupt Vector Controller. 756 757config LOONGSON_PCH_PIC 758 bool "Loongson PCH PIC Controller" 759 depends on MACH_LOONGSON64 || LOONGARCH 760 default MACH_LOONGSON64 761 select IRQ_DOMAIN_HIERARCHY 762 select IRQ_FASTEOI_HIERARCHY_HANDLERS 763 help 764 Support for the Loongson PCH PIC Controller. 765 766config LOONGSON_PCH_MSI 767 bool "Loongson PCH MSI Controller" 768 depends on MACH_LOONGSON64 || LOONGARCH 769 depends on PCI 770 default MACH_LOONGSON64 771 select IRQ_DOMAIN_HIERARCHY 772 select IRQ_MSI_LIB 773 select PCI_MSI 774 help 775 Support for the Loongson PCH MSI Controller. 776 777config LOONGSON_PCH_LPC 778 bool "Loongson PCH LPC Controller" 779 depends on MACH_LOONGSON64 || LOONGARCH 780 default MACH_LOONGSON64 781 select IRQ_DOMAIN_HIERARCHY 782 help 783 Support for the Loongson PCH LPC Controller. 784 785config MST_IRQ 786 bool "MStar Interrupt Controller" 787 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 788 default ARCH_MEDIATEK 789 select IRQ_DOMAIN 790 select IRQ_DOMAIN_HIERARCHY 791 help 792 Support MStar Interrupt Controller. 793 794config WPCM450_AIC 795 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 796 depends on ARCH_WPCM450 797 help 798 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 799 800config IRQ_IDT3243X 801 bool 802 select GENERIC_IRQ_CHIP 803 select IRQ_DOMAIN 804 805config APPLE_AIC 806 bool "Apple Interrupt Controller (AIC)" 807 depends on ARM64 808 depends on ARCH_APPLE || COMPILE_TEST 809 select GENERIC_IRQ_IPI_MUX 810 help 811 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 812 such as the M1. 813 814config MCHP_EIC 815 bool "Microchip External Interrupt Controller" 816 depends on ARCH_AT91 || COMPILE_TEST 817 select IRQ_DOMAIN 818 select IRQ_DOMAIN_HIERARCHY 819 help 820 Support for Microchip External Interrupt Controller. 821 822config SOPHGO_SG2042_MSI 823 bool "Sophgo SG2042 MSI Controller" 824 depends on ARCH_SOPHGO || COMPILE_TEST 825 depends on PCI 826 select IRQ_DOMAIN_HIERARCHY 827 select IRQ_MSI_LIB 828 select PCI_MSI 829 help 830 Support for the Sophgo SG2042 MSI Controller. 831 This on-chip interrupt controller enables MSI sources to be 832 routed to the primary PLIC controller on SoC. 833 834config SUNPLUS_SP7021_INTC 835 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 836 default SOC_SP7021 837 help 838 Support for the Sunplus SP7021 Interrupt Controller IP core. 839 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 840 chained controller, routing all interrupt source in P-Chip to 841 the primary controller on C-Chip. 842 843endmenu 844