1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 select IRQ_MSI_IOMMU 32 33config GIC_NON_BANKED 34 bool 35 36config ARM_GIC_V3 37 bool 38 select IRQ_DOMAIN_HIERARCHY 39 select PARTITION_PERCPU 40 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 41 select HAVE_ARM_SMCCC_DISCOVERY 42 select IRQ_MSI_IOMMU 43 44config ARM_GIC_V3_ITS 45 bool 46 select GENERIC_MSI_IRQ 47 select IRQ_MSI_LIB 48 default ARM_GIC_V3 49 select IRQ_MSI_IOMMU 50 51config ARM_GIC_V3_ITS_FSL_MC 52 bool 53 depends on ARM_GIC_V3_ITS 54 depends on FSL_MC_BUS 55 default ARM_GIC_V3_ITS 56 57config ARM_NVIC 58 bool 59 select IRQ_DOMAIN_HIERARCHY 60 select GENERIC_IRQ_CHIP 61 62config ARM_VIC 63 bool 64 select IRQ_DOMAIN 65 66config ARM_VIC_NR 67 int 68 default 4 if ARCH_S5PV210 69 default 2 70 depends on ARM_VIC 71 help 72 The maximum number of VICs available in the system, for 73 power management. 74 75config IRQ_MSI_LIB 76 bool 77 78config ARMADA_370_XP_IRQ 79 bool 80 select GENERIC_IRQ_CHIP 81 select PCI_MSI if PCI 82 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 83 84config ALPINE_MSI 85 bool 86 depends on PCI 87 select PCI_MSI 88 select GENERIC_IRQ_CHIP 89 90config AL_FIC 91 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 92 depends on OF 93 depends on HAS_IOMEM 94 select GENERIC_IRQ_CHIP 95 select IRQ_DOMAIN 96 help 97 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 98 99config ATMEL_AIC_IRQ 100 bool 101 select GENERIC_IRQ_CHIP 102 select IRQ_DOMAIN 103 select SPARSE_IRQ 104 105config ATMEL_AIC5_IRQ 106 bool 107 select GENERIC_IRQ_CHIP 108 select IRQ_DOMAIN 109 select SPARSE_IRQ 110 111config I8259 112 bool 113 select IRQ_DOMAIN 114 115config BCM2712_MIP 116 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 117 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 118 default m if ARCH_BRCMSTB || ARCH_BCM2835 119 depends on ARM_GIC 120 select GENERIC_IRQ_CHIP 121 select IRQ_DOMAIN_HIERARCHY 122 select GENERIC_MSI_IRQ 123 select IRQ_MSI_LIB 124 help 125 Enable support for the Broadcom BCM2712 MSI-X target peripheral 126 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 127 Raspberry Pi 5. 128 129 If unsure say n. 130 131config BCM6345_L1_IRQ 132 bool 133 select GENERIC_IRQ_CHIP 134 select IRQ_DOMAIN 135 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 136 137config BCM7038_L1_IRQ 138 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 139 depends on ARCH_BRCMSTB || BMIPS_GENERIC 140 default ARCH_BRCMSTB || BMIPS_GENERIC 141 select GENERIC_IRQ_CHIP 142 select IRQ_DOMAIN 143 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 144 145config BCM7120_L2_IRQ 146 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 147 depends on ARCH_BRCMSTB || BMIPS_GENERIC 148 default ARCH_BRCMSTB || BMIPS_GENERIC 149 select GENERIC_IRQ_CHIP 150 select IRQ_DOMAIN 151 152config BRCMSTB_L2_IRQ 153 tristate "Broadcom STB generic L2 interrupt controller driver" 154 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 155 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 156 select GENERIC_IRQ_CHIP 157 select IRQ_DOMAIN 158 159config DAVINCI_CP_INTC 160 bool 161 select GENERIC_IRQ_CHIP 162 select IRQ_DOMAIN 163 164config DW_APB_ICTL 165 bool 166 select GENERIC_IRQ_CHIP 167 select IRQ_DOMAIN_HIERARCHY 168 169config FARADAY_FTINTC010 170 bool 171 select IRQ_DOMAIN 172 select SPARSE_IRQ 173 174config HISILICON_IRQ_MBIGEN 175 bool 176 select ARM_GIC_V3 177 select ARM_GIC_V3_ITS 178 179config IMGPDC_IRQ 180 bool 181 select GENERIC_IRQ_CHIP 182 select IRQ_DOMAIN 183 184config IXP4XX_IRQ 185 bool 186 select IRQ_DOMAIN 187 select SPARSE_IRQ 188 189config LAN966X_OIC 190 tristate "Microchip LAN966x OIC Support" 191 depends on MCHP_LAN966X_PCI || COMPILE_TEST 192 select GENERIC_IRQ_CHIP 193 select IRQ_DOMAIN 194 help 195 Enable support for the LAN966x Outbound Interrupt Controller. 196 This controller is present on the Microchip LAN966x PCI device and 197 maps the internal interrupts sources to PCIe interrupt. 198 199 To compile this driver as a module, choose M here: the module 200 will be called irq-lan966x-oic. 201 202config MADERA_IRQ 203 tristate 204 205config IRQ_MIPS_CPU 206 bool 207 select GENERIC_IRQ_CHIP 208 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 209 select IRQ_DOMAIN 210 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 211 212config CLPS711X_IRQCHIP 213 bool 214 depends on ARCH_CLPS711X 215 select IRQ_DOMAIN 216 select SPARSE_IRQ 217 default y 218 219config OMPIC 220 bool 221 222config OR1K_PIC 223 bool 224 select IRQ_DOMAIN 225 226config OMAP_IRQCHIP 227 bool 228 select GENERIC_IRQ_CHIP 229 select IRQ_DOMAIN 230 231config ORION_IRQCHIP 232 bool 233 select IRQ_DOMAIN 234 235config PIC32_EVIC 236 bool 237 select GENERIC_IRQ_CHIP 238 select IRQ_DOMAIN 239 240config JCORE_AIC 241 bool "J-Core integrated AIC" if COMPILE_TEST 242 depends on OF 243 select IRQ_DOMAIN 244 help 245 Support for the J-Core integrated AIC. 246 247config RDA_INTC 248 bool 249 select IRQ_DOMAIN 250 251config RENESAS_INTC_IRQPIN 252 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 253 select IRQ_DOMAIN 254 help 255 Enable support for the Renesas Interrupt Controller for external 256 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 257 258config RENESAS_IRQC 259 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 260 select GENERIC_IRQ_CHIP 261 select IRQ_DOMAIN 262 help 263 Enable support for the Renesas Interrupt Controller for external 264 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 265 266config RENESAS_RZA1_IRQC 267 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 268 select IRQ_DOMAIN_HIERARCHY 269 help 270 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 271 to 8 external interrupts with configurable sense select. 272 273config RENESAS_RZG2L_IRQC 274 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 275 select GENERIC_IRQ_CHIP 276 select IRQ_DOMAIN_HIERARCHY 277 help 278 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 279 for external devices. 280 281config RENESAS_RZV2H_ICU 282 bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 283 select GENERIC_IRQ_CHIP 284 select IRQ_DOMAIN_HIERARCHY 285 help 286 Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 287 288config SL28CPLD_INTC 289 bool "Kontron sl28cpld IRQ controller" 290 depends on MFD_SL28CPLD=y || COMPILE_TEST 291 select REGMAP_IRQ 292 help 293 Interrupt controller driver for the board management controller 294 found on the Kontron sl28 CPLD. 295 296config ST_IRQCHIP 297 bool 298 select REGMAP 299 select MFD_SYSCON 300 help 301 Enables SysCfg Controlled IRQs on STi based platforms. 302 303config SUN4I_INTC 304 bool 305 306config SUN6I_R_INTC 307 bool 308 select IRQ_DOMAIN_HIERARCHY 309 select IRQ_FASTEOI_HIERARCHY_HANDLERS 310 311config SUNXI_NMI_INTC 312 bool 313 select GENERIC_IRQ_CHIP 314 315config TB10X_IRQC 316 bool 317 select IRQ_DOMAIN 318 select GENERIC_IRQ_CHIP 319 320config TS4800_IRQ 321 tristate "TS-4800 IRQ controller" 322 select IRQ_DOMAIN 323 depends on HAS_IOMEM 324 depends on SOC_IMX51 || COMPILE_TEST 325 help 326 Support for the TS-4800 FPGA IRQ controller 327 328config VERSATILE_FPGA_IRQ 329 bool 330 select IRQ_DOMAIN 331 332config VERSATILE_FPGA_IRQ_NR 333 int 334 default 4 335 depends on VERSATILE_FPGA_IRQ 336 337config XTENSA_MX 338 bool 339 select IRQ_DOMAIN 340 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 341 342config XILINX_INTC 343 bool "Xilinx Interrupt Controller IP" 344 depends on OF_ADDRESS 345 select IRQ_DOMAIN 346 help 347 Support for the Xilinx Interrupt Controller IP core. 348 This is used as a primary controller with MicroBlaze and can also 349 be used as a secondary chained controller on other platforms. 350 351config IRQ_CROSSBAR 352 bool 353 help 354 Support for a CROSSBAR ip that precedes the main interrupt controller. 355 The primary irqchip invokes the crossbar's callback which inturn allocates 356 a free irq and configures the IP. Thus the peripheral interrupts are 357 routed to one of the free irqchip interrupt lines. 358 359config KEYSTONE_IRQ 360 tristate "Keystone 2 IRQ controller IP" 361 depends on ARCH_KEYSTONE 362 help 363 Support for Texas Instruments Keystone 2 IRQ controller IP which 364 is part of the Keystone 2 IPC mechanism 365 366config MIPS_GIC 367 bool 368 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 369 select GENERIC_IRQ_IPI if SMP 370 select IRQ_DOMAIN_HIERARCHY 371 select MIPS_CM 372 373config INGENIC_IRQ 374 bool 375 depends on MACH_INGENIC 376 default y 377 378config INGENIC_TCU_IRQ 379 bool "Ingenic JZ47xx TCU interrupt controller" 380 default MACH_INGENIC 381 depends on MIPS || COMPILE_TEST 382 select MFD_SYSCON 383 select GENERIC_IRQ_CHIP 384 help 385 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 386 JZ47xx SoCs. 387 388 If unsure, say N. 389 390config IMX_GPCV2 391 bool 392 select IRQ_DOMAIN 393 help 394 Enables the wakeup IRQs for IMX platforms with GPCv2 block 395 396config IRQ_MXS 397 def_bool y if MACH_ASM9260 || ARCH_MXS 398 select IRQ_DOMAIN 399 select STMP_DEVICE 400 401config MSCC_OCELOT_IRQ 402 bool 403 select IRQ_DOMAIN 404 select GENERIC_IRQ_CHIP 405 406config MVEBU_GICP 407 select IRQ_MSI_LIB 408 bool 409 410config MVEBU_ICU 411 bool 412 413config MVEBU_ODMI 414 bool 415 select IRQ_MSI_LIB 416 select GENERIC_MSI_IRQ 417 418config MVEBU_PIC 419 bool 420 421config MVEBU_SEI 422 bool 423 424config LS_EXTIRQ 425 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 426 select MFD_SYSCON 427 428config LS_SCFG_MSI 429 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 430 select IRQ_MSI_IOMMU 431 depends on PCI_MSI 432 433config PARTITION_PERCPU 434 bool 435 436config STM32MP_EXTI 437 tristate "STM32MP extended interrupts and event controller" 438 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 439 default ARCH_STM32 && !ARM_SINGLE_ARMV7M 440 select IRQ_DOMAIN_HIERARCHY 441 select GENERIC_IRQ_CHIP 442 help 443 Support STM32MP EXTI (extended interrupts and event) controller. 444 445config STM32_EXTI 446 bool 447 select IRQ_DOMAIN 448 select GENERIC_IRQ_CHIP 449 450config QCOM_IRQ_COMBINER 451 bool "QCOM IRQ combiner support" 452 depends on ARCH_QCOM && ACPI 453 select IRQ_DOMAIN_HIERARCHY 454 help 455 Say yes here to add support for the IRQ combiner devices embedded 456 in Qualcomm Technologies chips. 457 458config IRQ_UNIPHIER_AIDET 459 bool "UniPhier AIDET support" if COMPILE_TEST 460 depends on ARCH_UNIPHIER || COMPILE_TEST 461 default ARCH_UNIPHIER 462 select IRQ_DOMAIN_HIERARCHY 463 help 464 Support for the UniPhier AIDET (ARM Interrupt Detector). 465 466config MESON_IRQ_GPIO 467 tristate "Meson GPIO Interrupt Multiplexer" 468 depends on ARCH_MESON || COMPILE_TEST 469 default ARCH_MESON 470 select IRQ_DOMAIN_HIERARCHY 471 help 472 Support Meson SoC Family GPIO Interrupt Multiplexer 473 474config GOLDFISH_PIC 475 bool "Goldfish programmable interrupt controller" 476 depends on MIPS && (GOLDFISH || COMPILE_TEST) 477 select GENERIC_IRQ_CHIP 478 select IRQ_DOMAIN 479 help 480 Say yes here to enable Goldfish interrupt controller driver used 481 for Goldfish based virtual platforms. 482 483config QCOM_PDC 484 tristate "QCOM PDC" 485 depends on ARCH_QCOM 486 select IRQ_DOMAIN_HIERARCHY 487 help 488 Power Domain Controller driver to manage and configure wakeup 489 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 490 491config QCOM_MPM 492 tristate "QCOM MPM" 493 depends on ARCH_QCOM 494 depends on MAILBOX 495 select IRQ_DOMAIN_HIERARCHY 496 help 497 MSM Power Manager driver to manage and configure wakeup 498 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 499 500config CSKY_MPINTC 501 bool 502 depends on CSKY 503 help 504 Say yes here to enable C-SKY SMP interrupt controller driver used 505 for C-SKY SMP system. 506 In fact it's not mmio map in hardware and it uses ld/st to visit the 507 controller's register inside CPU. 508 509config CSKY_APB_INTC 510 bool "C-SKY APB Interrupt Controller" 511 depends on CSKY 512 help 513 Say yes here to enable C-SKY APB interrupt controller driver used 514 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 515 the controller's register. 516 517config IMX_IRQSTEER 518 bool "i.MX IRQSTEER support" 519 depends on ARCH_MXC || COMPILE_TEST 520 default ARCH_MXC 521 select IRQ_DOMAIN 522 help 523 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 524 525config IMX_INTMUX 526 bool "i.MX INTMUX support" if COMPILE_TEST 527 default y if ARCH_MXC 528 select IRQ_DOMAIN 529 help 530 Support for the i.MX INTMUX interrupt multiplexer. 531 532config IMX_MU_MSI 533 tristate "i.MX MU used as MSI controller" 534 depends on OF && HAS_IOMEM 535 depends on ARCH_MXC || COMPILE_TEST 536 default m if ARCH_MXC 537 select IRQ_DOMAIN 538 select IRQ_DOMAIN_HIERARCHY 539 select GENERIC_MSI_IRQ 540 select IRQ_MSI_LIB 541 help 542 Provide a driver for the i.MX Messaging Unit block used as a 543 CPU-to-CPU MSI controller. This requires a specially crafted DT 544 to make use of this driver. 545 546 If unsure, say N 547 548config LS1X_IRQ 549 bool "Loongson-1 Interrupt Controller" 550 depends on MACH_LOONGSON32 551 default y 552 select IRQ_DOMAIN 553 select GENERIC_IRQ_CHIP 554 help 555 Support for the Loongson-1 platform Interrupt Controller. 556 557config TI_SCI_INTR_IRQCHIP 558 tristate "TI SCI INTR Interrupt Controller" 559 depends on TI_SCI_PROTOCOL 560 depends on ARCH_K3 || COMPILE_TEST 561 select IRQ_DOMAIN_HIERARCHY 562 help 563 This enables the irqchip driver support for K3 Interrupt router 564 over TI System Control Interface available on some new TI's SoCs. 565 If you wish to use interrupt router irq resources managed by the 566 TI System Controller, say Y here. Otherwise, say N. 567 568config TI_SCI_INTA_IRQCHIP 569 tristate "TI SCI INTA Interrupt Controller" 570 depends on TI_SCI_PROTOCOL 571 depends on ARCH_K3 || (COMPILE_TEST && ARM64) 572 select IRQ_DOMAIN_HIERARCHY 573 select TI_SCI_INTA_MSI_DOMAIN 574 help 575 This enables the irqchip driver support for K3 Interrupt aggregator 576 over TI System Control Interface available on some new TI's SoCs. 577 If you wish to use interrupt aggregator irq resources managed by the 578 TI System Controller, say Y here. Otherwise, say N. 579 580config TI_PRUSS_INTC 581 tristate 582 depends on TI_PRUSS 583 default TI_PRUSS 584 select IRQ_DOMAIN 585 help 586 This enables support for the PRU-ICSS Local Interrupt Controller 587 present within a PRU-ICSS subsystem present on various TI SoCs. 588 The PRUSS INTC enables various interrupts to be routed to multiple 589 different processors within the SoC. 590 591config RISCV_INTC 592 bool 593 depends on RISCV 594 select IRQ_DOMAIN_HIERARCHY 595 596config RISCV_APLIC 597 bool 598 depends on RISCV 599 select IRQ_DOMAIN_HIERARCHY 600 601config RISCV_APLIC_MSI 602 bool 603 depends on RISCV_APLIC 604 select GENERIC_MSI_IRQ 605 default RISCV_APLIC 606 607config RISCV_IMSIC 608 bool 609 depends on RISCV 610 select IRQ_DOMAIN_HIERARCHY 611 select GENERIC_IRQ_MATRIX_ALLOCATOR 612 select GENERIC_MSI_IRQ 613 select IRQ_MSI_LIB 614 615config SIFIVE_PLIC 616 bool 617 depends on RISCV 618 select IRQ_DOMAIN_HIERARCHY 619 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 620 621config STARFIVE_JH8100_INTC 622 bool "StarFive JH8100 External Interrupt Controller" 623 depends on ARCH_STARFIVE || COMPILE_TEST 624 default ARCH_STARFIVE 625 select IRQ_DOMAIN_HIERARCHY 626 help 627 This enables support for the INTC chip found in StarFive JH8100 628 SoC. 629 630 If you don't know what to do here, say Y. 631 632config THEAD_C900_ACLINT_SSWI 633 bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller" 634 depends on RISCV 635 depends on SMP 636 select IRQ_DOMAIN_HIERARCHY 637 select GENERIC_IRQ_IPI_MUX 638 help 639 This enables support for T-HEAD specific ACLINT SSWI device 640 support. 641 642 If you don't know what to do here, say Y. 643 644config EXYNOS_IRQ_COMBINER 645 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 646 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 647 help 648 Say yes here to add support for the IRQ combiner devices embedded 649 in Samsung Exynos chips. 650 651config IRQ_LOONGARCH_CPU 652 bool 653 select GENERIC_IRQ_CHIP 654 select IRQ_DOMAIN 655 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 656 select LOONGSON_HTVEC 657 select LOONGSON_LIOINTC 658 select LOONGSON_EIOINTC 659 select LOONGSON_PCH_PIC 660 select LOONGSON_PCH_MSI 661 select LOONGSON_PCH_LPC 662 help 663 Support for the LoongArch CPU Interrupt Controller. For details of 664 irq chip hierarchy on LoongArch platforms please read the document 665 Documentation/arch/loongarch/irq-chip-model.rst. 666 667config LOONGSON_LIOINTC 668 bool "Loongson Local I/O Interrupt Controller" 669 depends on MACH_LOONGSON64 670 default y 671 select IRQ_DOMAIN 672 select GENERIC_IRQ_CHIP 673 help 674 Support for the Loongson Local I/O Interrupt Controller. 675 676config LOONGSON_EIOINTC 677 bool "Loongson Extend I/O Interrupt Controller" 678 depends on LOONGARCH 679 depends on MACH_LOONGSON64 680 default MACH_LOONGSON64 681 select IRQ_DOMAIN_HIERARCHY 682 select GENERIC_IRQ_CHIP 683 help 684 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 685 686config LOONGSON_HTPIC 687 bool "Loongson3 HyperTransport PIC Controller" 688 depends on MACH_LOONGSON64 && MIPS 689 default y 690 select IRQ_DOMAIN 691 select GENERIC_IRQ_CHIP 692 help 693 Support for the Loongson-3 HyperTransport PIC Controller. 694 695config LOONGSON_HTVEC 696 bool "Loongson HyperTransport Interrupt Vector Controller" 697 depends on MACH_LOONGSON64 698 default MACH_LOONGSON64 699 select IRQ_DOMAIN_HIERARCHY 700 help 701 Support for the Loongson HyperTransport Interrupt Vector Controller. 702 703config LOONGSON_PCH_PIC 704 bool "Loongson PCH PIC Controller" 705 depends on MACH_LOONGSON64 706 default MACH_LOONGSON64 707 select IRQ_DOMAIN_HIERARCHY 708 select IRQ_FASTEOI_HIERARCHY_HANDLERS 709 help 710 Support for the Loongson PCH PIC Controller. 711 712config LOONGSON_PCH_MSI 713 bool "Loongson PCH MSI Controller" 714 depends on MACH_LOONGSON64 715 depends on PCI 716 default MACH_LOONGSON64 717 select IRQ_DOMAIN_HIERARCHY 718 select IRQ_MSI_LIB 719 select PCI_MSI 720 help 721 Support for the Loongson PCH MSI Controller. 722 723config LOONGSON_PCH_LPC 724 bool "Loongson PCH LPC Controller" 725 depends on LOONGARCH 726 depends on MACH_LOONGSON64 727 default MACH_LOONGSON64 728 select IRQ_DOMAIN_HIERARCHY 729 help 730 Support for the Loongson PCH LPC Controller. 731 732config MST_IRQ 733 bool "MStar Interrupt Controller" 734 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 735 default ARCH_MEDIATEK 736 select IRQ_DOMAIN 737 select IRQ_DOMAIN_HIERARCHY 738 help 739 Support MStar Interrupt Controller. 740 741config WPCM450_AIC 742 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 743 depends on ARCH_WPCM450 744 help 745 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 746 747config IRQ_IDT3243X 748 bool 749 select GENERIC_IRQ_CHIP 750 select IRQ_DOMAIN 751 752config APPLE_AIC 753 bool "Apple Interrupt Controller (AIC)" 754 depends on ARM64 755 depends on ARCH_APPLE || COMPILE_TEST 756 select GENERIC_IRQ_IPI_MUX 757 help 758 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 759 such as the M1. 760 761config MCHP_EIC 762 bool "Microchip External Interrupt Controller" 763 depends on ARCH_AT91 || COMPILE_TEST 764 select IRQ_DOMAIN 765 select IRQ_DOMAIN_HIERARCHY 766 help 767 Support for Microchip External Interrupt Controller. 768 769config SOPHGO_SG2042_MSI 770 bool "Sophgo SG2042 MSI Controller" 771 depends on ARCH_SOPHGO || COMPILE_TEST 772 depends on PCI 773 select IRQ_DOMAIN_HIERARCHY 774 select IRQ_MSI_LIB 775 select PCI_MSI 776 help 777 Support for the Sophgo SG2042 MSI Controller. 778 This on-chip interrupt controller enables MSI sources to be 779 routed to the primary PLIC controller on SoC. 780 781config SUNPLUS_SP7021_INTC 782 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 783 default SOC_SP7021 784 help 785 Support for the Sunplus SP7021 Interrupt Controller IP core. 786 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 787 chained controller, routing all interrupt source in P-Chip to 788 the primary controller on C-Chip. 789 790endmenu 791