1 // SPDX-License-Identifier: GPL-2.0
3  * MediaTek PCIe host controller driver.
15 #include <linux/irqchip/irq-msi-lib.h>
33 /* PCIe shared registers */
39 /* PCIe per port registers */
70 /* PCIe V2 share registers */
75 /* PCIe V2 per-port registers */
98  * Define PCIe to AHB window size as 2^33 to support max 8GB address space
104 /* PCIe V2 configuration transaction header */
128 	(GENMASK(((size) - 1), 0) << ((where) & 0x3))
146  * struct mtk_pcie_soc - differentiate between host generations
166  * struct mtk_pcie_port - PCIe port information
169  * @pcie: pointer to PCIe host info
176  *          when pcie_mac_ck/pcie_pipe_ck is turned off
190 	struct mtk_pcie *pcie;  member
208  * struct mtk_pcie - PCIe host information
209  * @dev: pointer to PCIe device
211  * @cfg: IO mapped register map for PCIe config
212  * @free_ck: free-run reference clock
213  * @ports: pointer to PCIe port information
214  * @soc: pointer to SoC-dependent operations
226 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)  in mtk_pcie_subsys_powerdown()  argument
228 	struct device *dev = pcie->dev;  in mtk_pcie_subsys_powerdown()
230 	clk_disable_unprepare(pcie->free_ck);  in mtk_pcie_subsys_powerdown()
238 	struct mtk_pcie *pcie = port->pcie;  in mtk_pcie_port_free()  local
239 	struct device *dev = pcie->dev;  in mtk_pcie_port_free()
241 	devm_iounmap(dev, port->base);  in mtk_pcie_port_free()
242 	list_del(&port->list);  in mtk_pcie_port_free()
246 static void mtk_pcie_put_resources(struct mtk_pcie *pcie)  in mtk_pcie_put_resources()  argument
250 	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {  in mtk_pcie_put_resources()
251 		phy_power_off(port->phy);  in mtk_pcie_put_resources()
252 		phy_exit(port->phy);  in mtk_pcie_put_resources()
253 		clk_disable_unprepare(port->pipe_ck);  in mtk_pcie_put_resources()
254 		clk_disable_unprepare(port->obff_ck);  in mtk_pcie_put_resources()
255 		clk_disable_unprepare(port->axi_ck);  in mtk_pcie_put_resources()
256 		clk_disable_unprepare(port->aux_ck);  in mtk_pcie_put_resources()
257 		clk_disable_unprepare(port->ahb_ck);  in mtk_pcie_put_resources()
258 		clk_disable_unprepare(port->sys_ck);  in mtk_pcie_put_resources()
262 	mtk_pcie_subsys_powerdown(pcie);  in mtk_pcie_put_resources()
270 	err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,  in mtk_pcie_check_cfg_cpld()
276 	if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)  in mtk_pcie_check_cfg_cpld()
287 	/* Write PCIe configuration transaction header for Cfgrd */  in mtk_pcie_hw_rd_cfg()
289 	       port->base + PCIE_CFG_HEADER0);  in mtk_pcie_hw_rd_cfg()
290 	writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);  in mtk_pcie_hw_rd_cfg()
292 	       port->base + PCIE_CFG_HEADER2);  in mtk_pcie_hw_rd_cfg()
295 	tmp = readl(port->base + PCIE_APP_TLP_REQ);  in mtk_pcie_hw_rd_cfg()
297 	writel(tmp, port->base + PCIE_APP_TLP_REQ);  in mtk_pcie_hw_rd_cfg()
304 	*val = readl(port->base + PCIE_CFG_RDATA);  in mtk_pcie_hw_rd_cfg()
317 	/* Write PCIe configuration transaction header for Cfgwr */  in mtk_pcie_hw_wr_cfg()
319 	       port->base + PCIE_CFG_HEADER0);  in mtk_pcie_hw_wr_cfg()
320 	writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);  in mtk_pcie_hw_wr_cfg()
322 	       port->base + PCIE_CFG_HEADER2);  in mtk_pcie_hw_wr_cfg()
326 	writel(val, port->base + PCIE_CFG_WDATA);  in mtk_pcie_hw_wr_cfg()
329 	val = readl(port->base + PCIE_APP_TLP_REQ);  in mtk_pcie_hw_wr_cfg()
331 	writel(val, port->base + PCIE_APP_TLP_REQ);  in mtk_pcie_hw_wr_cfg()
340 	struct mtk_pcie *pcie = bus->sysdata;  in mtk_pcie_find_port()  local
348 	while (bus && bus->number) {  in mtk_pcie_find_port()
349 		dev = bus->self;  in mtk_pcie_find_port()
350 		bus = dev->bus;  in mtk_pcie_find_port()
351 		devfn = dev->devfn;  in mtk_pcie_find_port()
354 	list_for_each_entry(port, &pcie->ports, list)  in mtk_pcie_find_port()
355 		if (port->slot == PCI_SLOT(devfn))  in mtk_pcie_find_port()
365 	u32 bn = bus->number;  in mtk_pcie_config_read()
378 	u32 bn = bus->number;  in mtk_pcie_config_write()
397 	/* MT2712/MT7622 only support 32-bit MSI addresses */  in mtk_compose_msi_msg()
398 	addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);  in mtk_compose_msi_msg()
399 	msg->address_hi = 0;  in mtk_compose_msi_msg()
400 	msg->address_lo = lower_32_bits(addr);  in mtk_compose_msi_msg()
402 	msg->data = data->hwirq;  in mtk_compose_msi_msg()
404 	dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n",  in mtk_compose_msi_msg()
405 		(int)data->hwirq, msg->address_hi, msg->address_lo);  in mtk_compose_msi_msg()
411 	u32 hwirq = data->hwirq;  in mtk_msi_ack_irq()
413 	writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);  in mtk_msi_ack_irq()
425 	struct mtk_pcie_port *port = domain->host_data;  in mtk_pcie_irq_domain_alloc()
429 	mutex_lock(&port->lock);  in mtk_pcie_irq_domain_alloc()
431 	bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);  in mtk_pcie_irq_domain_alloc()
433 		mutex_unlock(&port->lock);  in mtk_pcie_irq_domain_alloc()
434 		return -ENOSPC;  in mtk_pcie_irq_domain_alloc()
437 	__set_bit(bit, port->msi_irq_in_use);  in mtk_pcie_irq_domain_alloc()
439 	mutex_unlock(&port->lock);  in mtk_pcie_irq_domain_alloc()
442 			    domain->host_data, handle_edge_irq,  in mtk_pcie_irq_domain_alloc()
454 	mutex_lock(&port->lock);  in mtk_pcie_irq_domain_free()
456 	if (!test_bit(d->hwirq, port->msi_irq_in_use))  in mtk_pcie_irq_domain_free()
457 		dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n",  in mtk_pcie_irq_domain_free()
458 			d->hwirq);  in mtk_pcie_irq_domain_free()
460 		__clear_bit(d->hwirq, port->msi_irq_in_use);  in mtk_pcie_irq_domain_free()
462 	mutex_unlock(&port->lock);  in mtk_pcie_irq_domain_free()
484 	.prefix			= "MTK-",
490 	mutex_init(&port->lock);  in mtk_pcie_allocate_msi_domains()
493 		.fwnode		= dev_fwnode(port->pcie->dev),  in mtk_pcie_allocate_msi_domains()
499 	port->inner_domain = msi_create_parent_irq_domain(&info, &mtk_msi_parent_ops);  in mtk_pcie_allocate_msi_domains()
500 	if (!port->inner_domain) {  in mtk_pcie_allocate_msi_domains()
501 		dev_err(port->pcie->dev, "failed to create IRQ domain\n");  in mtk_pcie_allocate_msi_domains()
502 		return -ENOMEM;  in mtk_pcie_allocate_msi_domains()
513 	msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);  in mtk_pcie_enable_msi()
515 	writel(val, port->base + PCIE_IMSI_ADDR);  in mtk_pcie_enable_msi()
517 	val = readl(port->base + PCIE_INT_MASK);  in mtk_pcie_enable_msi()
519 	writel(val, port->base + PCIE_INT_MASK);  in mtk_pcie_enable_msi()
522 static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)  in mtk_pcie_irq_teardown()  argument
526 	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {  in mtk_pcie_irq_teardown()
527 		irq_set_chained_handler_and_data(port->irq, NULL, NULL);  in mtk_pcie_irq_teardown()
529 		if (port->irq_domain)  in mtk_pcie_irq_teardown()
530 			irq_domain_remove(port->irq_domain);  in mtk_pcie_irq_teardown()
533 			if (port->inner_domain)  in mtk_pcie_irq_teardown()
534 				irq_domain_remove(port->inner_domain);  in mtk_pcie_irq_teardown()
537 		irq_dispose_mapping(port->irq);  in mtk_pcie_irq_teardown()
545 	irq_set_chip_data(irq, domain->host_data);  in mtk_pcie_intx_map()
557 	struct device *dev = port->pcie->dev;  in mtk_pcie_init_irq_domain()
564 		dev_err(dev, "no PCIe Intc node found\n");  in mtk_pcie_init_irq_domain()
565 		return -ENODEV;  in mtk_pcie_init_irq_domain()
568 	port->irq_domain = irq_domain_create_linear(of_fwnode_handle(pcie_intc_node), PCI_NUM_INTX,  in mtk_pcie_init_irq_domain()
571 	if (!port->irq_domain) {  in mtk_pcie_init_irq_domain()
573 		return -ENODEV;  in mtk_pcie_init_irq_domain()
594 	status = readl(port->base + PCIE_INT_STATUS);  in mtk_pcie_intr_handler()
598 			writel(1 << bit, port->base + PCIE_INT_STATUS);  in mtk_pcie_intr_handler()
599 			generic_handle_domain_irq(port->irq_domain,  in mtk_pcie_intr_handler()
600 						  bit - INTX_SHIFT);  in mtk_pcie_intr_handler()
611 			 * edge-triggered interrupt type, its status should  in mtk_pcie_intr_handler()
615 			writel(MSI_STATUS, port->base + PCIE_INT_STATUS);  in mtk_pcie_intr_handler()
616 			while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {  in mtk_pcie_intr_handler()
618 					generic_handle_domain_irq(port->inner_domain, bit);  in mtk_pcie_intr_handler()
629 	struct mtk_pcie *pcie = port->pcie;  in mtk_pcie_setup_irq()  local
630 	struct device *dev = pcie->dev;  in mtk_pcie_setup_irq()
636 		dev_err(dev, "failed to init PCIe IRQ domain\n");  in mtk_pcie_setup_irq()
640 	if (of_property_present(dev->of_node, "interrupt-names"))  in mtk_pcie_setup_irq()
641 		port->irq = platform_get_irq_byname(pdev, "pcie_irq");  in mtk_pcie_setup_irq()
643 		port->irq = platform_get_irq(pdev, port->slot);  in mtk_pcie_setup_irq()
645 	if (port->irq < 0)  in mtk_pcie_setup_irq()
646 		return port->irq;  in mtk_pcie_setup_irq()
648 	irq_set_chained_handler_and_data(port->irq,  in mtk_pcie_setup_irq()
656 	struct mtk_pcie *pcie = port->pcie;  in mtk_pcie_startup_port_v2()  local
657 	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);  in mtk_pcie_startup_port_v2()
660 	const struct mtk_pcie_soc *soc = port->pcie->soc;  in mtk_pcie_startup_port_v2()
664 	entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);  in mtk_pcie_startup_port_v2()
666 		mem = entry->res;  in mtk_pcie_startup_port_v2()
668 		return -EINVAL;  in mtk_pcie_startup_port_v2()
670 	/* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */  in mtk_pcie_startup_port_v2()
671 	if (pcie->base) {  in mtk_pcie_startup_port_v2()
672 		val = readl(pcie->base + PCIE_SYS_CFG_V2);  in mtk_pcie_startup_port_v2()
673 		val |= PCIE_CSR_LTSSM_EN(port->slot) |  in mtk_pcie_startup_port_v2()
674 		       PCIE_CSR_ASPM_L1_EN(port->slot);  in mtk_pcie_startup_port_v2()
675 		writel(val, pcie->base + PCIE_SYS_CFG_V2);  in mtk_pcie_startup_port_v2()
676 	} else if (pcie->cfg) {  in mtk_pcie_startup_port_v2()
677 		val = PCIE_CSR_LTSSM_EN(port->slot) |  in mtk_pcie_startup_port_v2()
678 		      PCIE_CSR_ASPM_L1_EN(port->slot);  in mtk_pcie_startup_port_v2()
679 		regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val);  in mtk_pcie_startup_port_v2()
683 	writel(0, port->base + PCIE_RST_CTRL);  in mtk_pcie_startup_port_v2()
686 	 * Enable PCIe link down reset, if link status changed from link up to  in mtk_pcie_startup_port_v2()
690 	writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);  in mtk_pcie_startup_port_v2()
693 	 * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and  in mtk_pcie_startup_port_v2()
694 	 * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should  in mtk_pcie_startup_port_v2()
699 	/* De-assert PHY, PE, PIPE, MAC and configuration reset	*/  in mtk_pcie_startup_port_v2()
700 	val = readl(port->base + PCIE_RST_CTRL);  in mtk_pcie_startup_port_v2()
703 	writel(val, port->base + PCIE_RST_CTRL);  in mtk_pcie_startup_port_v2()
706 	if (soc->need_fix_class_id) {  in mtk_pcie_startup_port_v2()
708 		writew(val, port->base + PCIE_CONF_VEND_ID);  in mtk_pcie_startup_port_v2()
711 		writew(val, port->base + PCIE_CONF_CLASS_ID);  in mtk_pcie_startup_port_v2()
714 	if (soc->need_fix_device_id)  in mtk_pcie_startup_port_v2()
715 		writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);  in mtk_pcie_startup_port_v2()
717 	/* 100ms timeout value should be enough for Gen1/2 training */  in mtk_pcie_startup_port_v2()
718 	err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,  in mtk_pcie_startup_port_v2()
722 		return -ETIMEDOUT;  in mtk_pcie_startup_port_v2()
725 	val = readl(port->base + PCIE_INT_MASK);  in mtk_pcie_startup_port_v2()
727 	writel(val, port->base + PCIE_INT_MASK);  in mtk_pcie_startup_port_v2()
732 	/* Set AHB to PCIe translation windows */  in mtk_pcie_startup_port_v2()
733 	val = lower_32_bits(mem->start) |  in mtk_pcie_startup_port_v2()
735 	writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);  in mtk_pcie_startup_port_v2()
737 	val = upper_32_bits(mem->start);  in mtk_pcie_startup_port_v2()
738 	writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);  in mtk_pcie_startup_port_v2()
740 	/* Set PCIe to AXI translation memory space.*/  in mtk_pcie_startup_port_v2()
742 	writel(val, port->base + PCIE_AXI_WINDOW0);  in mtk_pcie_startup_port_v2()
750 	struct mtk_pcie *pcie = bus->sysdata;  in mtk_pcie_map_bus()  local
753 			      bus->number), pcie->base + PCIE_CFG_ADDR);  in mtk_pcie_map_bus()
755 	return pcie->base + PCIE_CFG_DATA + (where & 3);  in mtk_pcie_map_bus()
766 	struct mtk_pcie *pcie = port->pcie;  in mtk_pcie_startup_port()  local
767 	u32 func = PCI_FUNC(port->slot);  in mtk_pcie_startup_port()
768 	u32 slot = PCI_SLOT(port->slot << 3);  in mtk_pcie_startup_port()
773 	val = readl(pcie->base + PCIE_SYS_CFG);  in mtk_pcie_startup_port()
774 	val |= PCIE_PORT_PERST(port->slot);  in mtk_pcie_startup_port()
775 	writel(val, pcie->base + PCIE_SYS_CFG);  in mtk_pcie_startup_port()
777 	/* de-assert port PERST_N */  in mtk_pcie_startup_port()
778 	val = readl(pcie->base + PCIE_SYS_CFG);  in mtk_pcie_startup_port()
779 	val &= ~PCIE_PORT_PERST(port->slot);  in mtk_pcie_startup_port()
780 	writel(val, pcie->base + PCIE_SYS_CFG);  in mtk_pcie_startup_port()
782 	/* 100ms timeout value should be enough for Gen1/2 training */  in mtk_pcie_startup_port()
783 	err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,  in mtk_pcie_startup_port()
787 		return -ETIMEDOUT;  in mtk_pcie_startup_port()
790 	val = readl(pcie->base + PCIE_INT_ENABLE);  in mtk_pcie_startup_port()
791 	val |= PCIE_PORT_INT_EN(port->slot);  in mtk_pcie_startup_port()
792 	writel(val, pcie->base + PCIE_INT_ENABLE);  in mtk_pcie_startup_port()
796 	       port->base + PCIE_BAR0_SETUP);  in mtk_pcie_startup_port()
799 	writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);  in mtk_pcie_startup_port()
803 	       pcie->base + PCIE_CFG_ADDR);  in mtk_pcie_startup_port()
804 	val = readl(pcie->base + PCIE_CFG_DATA);  in mtk_pcie_startup_port()
808 	       pcie->base + PCIE_CFG_ADDR);  in mtk_pcie_startup_port()
809 	writel(val, pcie->base + PCIE_CFG_DATA);  in mtk_pcie_startup_port()
813 	       pcie->base + PCIE_CFG_ADDR);  in mtk_pcie_startup_port()
814 	val = readl(pcie->base + PCIE_CFG_DATA);  in mtk_pcie_startup_port()
818 	       pcie->base + PCIE_CFG_ADDR);  in mtk_pcie_startup_port()
819 	writel(val, pcie->base + PCIE_CFG_DATA);  in mtk_pcie_startup_port()
826 	struct mtk_pcie *pcie = port->pcie;  in mtk_pcie_enable_port()  local
827 	struct device *dev = pcie->dev;  in mtk_pcie_enable_port()
830 	err = clk_prepare_enable(port->sys_ck);  in mtk_pcie_enable_port()
832 		dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);  in mtk_pcie_enable_port()
836 	err = clk_prepare_enable(port->ahb_ck);  in mtk_pcie_enable_port()
838 		dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);  in mtk_pcie_enable_port()
842 	err = clk_prepare_enable(port->aux_ck);  in mtk_pcie_enable_port()
844 		dev_err(dev, "failed to enable aux_ck%d\n", port->slot);  in mtk_pcie_enable_port()
848 	err = clk_prepare_enable(port->axi_ck);  in mtk_pcie_enable_port()
850 		dev_err(dev, "failed to enable axi_ck%d\n", port->slot);  in mtk_pcie_enable_port()
854 	err = clk_prepare_enable(port->obff_ck);  in mtk_pcie_enable_port()
856 		dev_err(dev, "failed to enable obff_ck%d\n", port->slot);  in mtk_pcie_enable_port()
860 	err = clk_prepare_enable(port->pipe_ck);  in mtk_pcie_enable_port()
862 		dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);  in mtk_pcie_enable_port()
866 	reset_control_assert(port->reset);  in mtk_pcie_enable_port()
867 	reset_control_deassert(port->reset);  in mtk_pcie_enable_port()
869 	err = phy_init(port->phy);  in mtk_pcie_enable_port()
871 		dev_err(dev, "failed to initialize port%d phy\n", port->slot);  in mtk_pcie_enable_port()
875 	err = phy_power_on(port->phy);  in mtk_pcie_enable_port()
877 		dev_err(dev, "failed to power on port%d phy\n", port->slot);  in mtk_pcie_enable_port()
881 	if (!pcie->soc->startup(port))  in mtk_pcie_enable_port()
884 	dev_info(dev, "Port%d link down\n", port->slot);  in mtk_pcie_enable_port()
886 	phy_power_off(port->phy);  in mtk_pcie_enable_port()
888 	phy_exit(port->phy);  in mtk_pcie_enable_port()
890 	clk_disable_unprepare(port->pipe_ck);  in mtk_pcie_enable_port()
892 	clk_disable_unprepare(port->obff_ck);  in mtk_pcie_enable_port()
894 	clk_disable_unprepare(port->axi_ck);  in mtk_pcie_enable_port()
896 	clk_disable_unprepare(port->aux_ck);  in mtk_pcie_enable_port()
898 	clk_disable_unprepare(port->ahb_ck);  in mtk_pcie_enable_port()
900 	clk_disable_unprepare(port->sys_ck);  in mtk_pcie_enable_port()
905 static int mtk_pcie_parse_port(struct mtk_pcie *pcie,  in mtk_pcie_parse_port()  argument
910 	struct device *dev = pcie->dev;  in mtk_pcie_parse_port()
917 		return -ENOMEM;  in mtk_pcie_parse_port()
920 	port->base = devm_platform_ioremap_resource_byname(pdev, name);  in mtk_pcie_parse_port()
921 	if (IS_ERR(port->base)) {  in mtk_pcie_parse_port()
923 		return PTR_ERR(port->base);  in mtk_pcie_parse_port()
927 	port->sys_ck = devm_clk_get(dev, name);  in mtk_pcie_parse_port()
928 	if (IS_ERR(port->sys_ck)) {  in mtk_pcie_parse_port()
930 		return PTR_ERR(port->sys_ck);  in mtk_pcie_parse_port()
935 	port->ahb_ck = devm_clk_get_optional(dev, name);  in mtk_pcie_parse_port()
936 	if (IS_ERR(port->ahb_ck))  in mtk_pcie_parse_port()
937 		return PTR_ERR(port->ahb_ck);  in mtk_pcie_parse_port()
940 	port->axi_ck = devm_clk_get_optional(dev, name);  in mtk_pcie_parse_port()
941 	if (IS_ERR(port->axi_ck))  in mtk_pcie_parse_port()
942 		return PTR_ERR(port->axi_ck);  in mtk_pcie_parse_port()
945 	port->aux_ck = devm_clk_get_optional(dev, name);  in mtk_pcie_parse_port()
946 	if (IS_ERR(port->aux_ck))  in mtk_pcie_parse_port()
947 		return PTR_ERR(port->aux_ck);  in mtk_pcie_parse_port()
950 	port->obff_ck = devm_clk_get_optional(dev, name);  in mtk_pcie_parse_port()
951 	if (IS_ERR(port->obff_ck))  in mtk_pcie_parse_port()
952 		return PTR_ERR(port->obff_ck);  in mtk_pcie_parse_port()
955 	port->pipe_ck = devm_clk_get_optional(dev, name);  in mtk_pcie_parse_port()
956 	if (IS_ERR(port->pipe_ck))  in mtk_pcie_parse_port()
957 		return PTR_ERR(port->pipe_ck);  in mtk_pcie_parse_port()
959 	snprintf(name, sizeof(name), "pcie-rst%d", slot);  in mtk_pcie_parse_port()
960 	port->reset = devm_reset_control_get_optional_exclusive(dev, name);  in mtk_pcie_parse_port()
961 	if (PTR_ERR(port->reset) == -EPROBE_DEFER)  in mtk_pcie_parse_port()
962 		return PTR_ERR(port->reset);  in mtk_pcie_parse_port()
965 	snprintf(name, sizeof(name), "pcie-phy%d", slot);  in mtk_pcie_parse_port()
966 	port->phy = devm_phy_optional_get(dev, name);  in mtk_pcie_parse_port()
967 	if (IS_ERR(port->phy))  in mtk_pcie_parse_port()
968 		return PTR_ERR(port->phy);  in mtk_pcie_parse_port()
970 	port->slot = slot;  in mtk_pcie_parse_port()
971 	port->pcie = pcie;  in mtk_pcie_parse_port()
973 	if (pcie->soc->setup_irq) {  in mtk_pcie_parse_port()
974 		err = pcie->soc->setup_irq(port, node);  in mtk_pcie_parse_port()
979 	INIT_LIST_HEAD(&port->list);  in mtk_pcie_parse_port()
980 	list_add_tail(&port->list, &pcie->ports);  in mtk_pcie_parse_port()
985 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)  in mtk_pcie_subsys_powerup()  argument
987 	struct device *dev = pcie->dev;  in mtk_pcie_subsys_powerup()
996 		pcie->base = devm_ioremap_resource(dev, regs);  in mtk_pcie_subsys_powerup()
997 		if (IS_ERR(pcie->base))  in mtk_pcie_subsys_powerup()
998 			return PTR_ERR(pcie->base);  in mtk_pcie_subsys_powerup()
1002 					   "mediatek,generic-pciecfg");  in mtk_pcie_subsys_powerup()
1004 		pcie->cfg = syscon_node_to_regmap(cfg_node);  in mtk_pcie_subsys_powerup()
1006 		if (IS_ERR(pcie->cfg))  in mtk_pcie_subsys_powerup()
1007 			return PTR_ERR(pcie->cfg);  in mtk_pcie_subsys_powerup()
1010 	pcie->free_ck = devm_clk_get(dev, "free_ck");  in mtk_pcie_subsys_powerup()
1011 	if (IS_ERR(pcie->free_ck)) {  in mtk_pcie_subsys_powerup()
1012 		if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)  in mtk_pcie_subsys_powerup()
1013 			return -EPROBE_DEFER;  in mtk_pcie_subsys_powerup()
1015 		pcie->free_ck = NULL;  in mtk_pcie_subsys_powerup()
1022 	err = clk_prepare_enable(pcie->free_ck);  in mtk_pcie_subsys_powerup()
1037 static int mtk_pcie_setup(struct mtk_pcie *pcie)  in mtk_pcie_setup()  argument
1039 	struct device *dev = pcie->dev;  in mtk_pcie_setup()
1040 	struct device_node *node = dev->of_node;  in mtk_pcie_setup()
1044 	slot = of_get_pci_domain_nr(dev->of_node);  in mtk_pcie_setup()
1053 			err = mtk_pcie_parse_port(pcie, child, slot);  in mtk_pcie_setup()
1058 		err = mtk_pcie_parse_port(pcie, node, slot);  in mtk_pcie_setup()
1063 	err = mtk_pcie_subsys_powerup(pcie);  in mtk_pcie_setup()
1068 	list_for_each_entry_safe(port, tmp, &pcie->ports, list)  in mtk_pcie_setup()
1071 	/* power down PCIe subsys if slots are all empty (link down) */  in mtk_pcie_setup()
1072 	if (list_empty(&pcie->ports))  in mtk_pcie_setup()
1073 		mtk_pcie_subsys_powerdown(pcie);  in mtk_pcie_setup()
1080 	struct device *dev = &pdev->dev;  in mtk_pcie_probe()
1081 	struct mtk_pcie *pcie;  in mtk_pcie_probe()  local
1085 	host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));  in mtk_pcie_probe()
1087 		return -ENOMEM;  in mtk_pcie_probe()
1089 	pcie = pci_host_bridge_priv(host);  in mtk_pcie_probe()
1091 	pcie->dev = dev;  in mtk_pcie_probe()
1092 	pcie->soc = of_device_get_match_data(dev);  in mtk_pcie_probe()
1093 	platform_set_drvdata(pdev, pcie);  in mtk_pcie_probe()
1094 	INIT_LIST_HEAD(&pcie->ports);  in mtk_pcie_probe()
1096 	err = mtk_pcie_setup(pcie);  in mtk_pcie_probe()
1100 	host->ops = pcie->soc->ops;  in mtk_pcie_probe()
1101 	host->sysdata = pcie;  in mtk_pcie_probe()
1102 	host->msi_domain = pcie->soc->no_msi;  in mtk_pcie_probe()
1111 	if (!list_empty(&pcie->ports))  in mtk_pcie_probe()
1112 		mtk_pcie_put_resources(pcie);  in mtk_pcie_probe()
1118 static void mtk_pcie_free_resources(struct mtk_pcie *pcie)  in mtk_pcie_free_resources()  argument
1120 	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);  in mtk_pcie_free_resources()
1121 	struct list_head *windows = &host->windows;  in mtk_pcie_free_resources()
1128 	struct mtk_pcie *pcie = platform_get_drvdata(pdev);  in mtk_pcie_remove()  local
1129 	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);  in mtk_pcie_remove()
1131 	pci_stop_root_bus(host->bus);  in mtk_pcie_remove()
1132 	pci_remove_root_bus(host->bus);  in mtk_pcie_remove()
1133 	mtk_pcie_free_resources(pcie);  in mtk_pcie_remove()
1135 	mtk_pcie_irq_teardown(pcie);  in mtk_pcie_remove()
1137 	mtk_pcie_put_resources(pcie);  in mtk_pcie_remove()
1142 	struct mtk_pcie *pcie = dev_get_drvdata(dev);  in mtk_pcie_suspend_noirq()  local
1145 	if (list_empty(&pcie->ports))  in mtk_pcie_suspend_noirq()
1148 	list_for_each_entry(port, &pcie->ports, list) {  in mtk_pcie_suspend_noirq()
1149 		clk_disable_unprepare(port->pipe_ck);  in mtk_pcie_suspend_noirq()
1150 		clk_disable_unprepare(port->obff_ck);  in mtk_pcie_suspend_noirq()
1151 		clk_disable_unprepare(port->axi_ck);  in mtk_pcie_suspend_noirq()
1152 		clk_disable_unprepare(port->aux_ck);  in mtk_pcie_suspend_noirq()
1153 		clk_disable_unprepare(port->ahb_ck);  in mtk_pcie_suspend_noirq()
1154 		clk_disable_unprepare(port->sys_ck);  in mtk_pcie_suspend_noirq()
1155 		phy_power_off(port->phy);  in mtk_pcie_suspend_noirq()
1156 		phy_exit(port->phy);  in mtk_pcie_suspend_noirq()
1159 	clk_disable_unprepare(pcie->free_ck);  in mtk_pcie_suspend_noirq()
1166 	struct mtk_pcie *pcie = dev_get_drvdata(dev);  in mtk_pcie_resume_noirq()  local
1169 	if (list_empty(&pcie->ports))  in mtk_pcie_resume_noirq()
1172 	clk_prepare_enable(pcie->free_ck);  in mtk_pcie_resume_noirq()
1174 	list_for_each_entry_safe(port, tmp, &pcie->ports, list)  in mtk_pcie_resume_noirq()
1178 	if (list_empty(&pcie->ports))  in mtk_pcie_resume_noirq()
1179 		clk_disable_unprepare(pcie->free_ck);  in mtk_pcie_resume_noirq()
1218 	{ .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1219 	{ .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1220 	{ .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1221 	{ .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1222 	{ .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1231 		.name = "mtk-pcie",
1238 MODULE_DESCRIPTION("MediaTek PCIe host controller driver");