1 // SPDX-License-Identifier: GPL-2.0
3  * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
5  * SPEAr13xx PCIe Glue Layer Source Code
7  * Copyright (C) 2010-2014 ST Microelectronics
22 #include "pcie-designware.h"
67 #define to_spear13xx_pcie(x)	dev_get_drvdata((x)->dev)
72 	struct pcie_app_reg __iomem *app_reg = spear13xx_pcie->app_base;  in spear13xx_pcie_start_link()
78 			&app_reg->app_ctrl_0);  in spear13xx_pcie_start_link()
86 	struct pcie_app_reg __iomem *app_reg = spear13xx_pcie->app_base;  in spear13xx_pcie_irq_handler()
87 	struct dw_pcie *pci = spear13xx_pcie->pci;  in spear13xx_pcie_irq_handler()
88 	struct dw_pcie_rp *pp = &pci->pp;  in spear13xx_pcie_irq_handler()
91 	status = readl(&app_reg->int_sts);  in spear13xx_pcie_irq_handler()
98 	writel(status, &app_reg->int_clr);  in spear13xx_pcie_irq_handler()
105 	struct pcie_app_reg __iomem *app_reg = spear13xx_pcie->app_base;  in spear13xx_pcie_enable_interrupts()
109 		writel(readl(&app_reg->int_mask) |  in spear13xx_pcie_enable_interrupts()
110 				MSI_CTRL_INT, &app_reg->int_mask);  in spear13xx_pcie_enable_interrupts()
116 	struct pcie_app_reg __iomem *app_reg = spear13xx_pcie->app_base;  in spear13xx_pcie_link_up()
118 	return readl(&app_reg->app_status_1) & XMLH_LINK_UP;  in spear13xx_pcie_link_up()
128 	spear13xx_pcie->app_base = pci->dbi_base + 0x2000;  in spear13xx_pcie_host_init()
132 	 * default value in capability register is 512 bytes. So force  in spear13xx_pcie_host_init()
154 	struct dw_pcie *pci = spear13xx_pcie->pci;  in spear13xx_add_pcie_port()
155 	struct dw_pcie_rp *pp = &pci->pp;  in spear13xx_add_pcie_port()
156 	struct device *dev = &pdev->dev;  in spear13xx_add_pcie_port()
159 	pp->irq = platform_get_irq(pdev, 0);  in spear13xx_add_pcie_port()
160 	if (pp->irq < 0)  in spear13xx_add_pcie_port()
161 		return pp->irq;  in spear13xx_add_pcie_port()
163 	ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,  in spear13xx_add_pcie_port()
165 			       "spear1340-pcie", spear13xx_pcie);  in spear13xx_add_pcie_port()
167 		dev_err(dev, "failed to request irq %d\n", pp->irq);  in spear13xx_add_pcie_port()
171 	pp->ops = &spear13xx_pcie_host_ops;  in spear13xx_add_pcie_port()
172 	pp->msi_irq[0] = -ENODEV;  in spear13xx_add_pcie_port()
190 	struct device *dev = &pdev->dev;  in spear13xx_pcie_probe()
193 	struct device_node *np = dev->of_node;  in spear13xx_pcie_probe()
198 		return -ENOMEM;  in spear13xx_pcie_probe()
202 		return -ENOMEM;  in spear13xx_pcie_probe()
204 	pci->dev = dev;  in spear13xx_pcie_probe()
205 	pci->ops = &dw_pcie_ops;  in spear13xx_pcie_probe()
207 	spear13xx_pcie->pci = pci;  in spear13xx_pcie_probe()
209 	spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");  in spear13xx_pcie_probe()
210 	if (IS_ERR(spear13xx_pcie->phy)) {  in spear13xx_pcie_probe()
211 		ret = PTR_ERR(spear13xx_pcie->phy);  in spear13xx_pcie_probe()
212 		if (ret == -EPROBE_DEFER)  in spear13xx_pcie_probe()
215 			dev_err(dev, "couldn't get pcie-phy\n");  in spear13xx_pcie_probe()
219 	phy_init(spear13xx_pcie->phy);  in spear13xx_pcie_probe()
221 	spear13xx_pcie->clk = devm_clk_get(dev, NULL);  in spear13xx_pcie_probe()
222 	if (IS_ERR(spear13xx_pcie->clk)) {  in spear13xx_pcie_probe()
223 		dev_err(dev, "couldn't get clk for pcie\n");  in spear13xx_pcie_probe()
224 		return PTR_ERR(spear13xx_pcie->clk);  in spear13xx_pcie_probe()
226 	ret = clk_prepare_enable(spear13xx_pcie->clk);  in spear13xx_pcie_probe()
228 		dev_err(dev, "couldn't enable clk for pcie\n");  in spear13xx_pcie_probe()
232 	if (of_property_read_bool(np, "st,pcie-is-gen1"))  in spear13xx_pcie_probe()
233 		pci->max_link_speed = 1;  in spear13xx_pcie_probe()
244 	clk_disable_unprepare(spear13xx_pcie->clk);  in spear13xx_pcie_probe()
250 	{ .compatible = "st,spear1340-pcie", },
257 		.name	= "spear-pcie",