1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Freescale i.MX6 SoCs 4 * 5 * Copyright (C) 2013 Kosagi 6 * https://www.kosagi.com 7 * 8 * Author: Sean Cross <xobs@kosagi.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kernel.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/pci.h> 23 #include <linux/platform_device.h> 24 #include <linux/regmap.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/resource.h> 27 #include <linux/signal.h> 28 #include <linux/types.h> 29 #include <linux/interrupt.h> 30 #include <linux/reset.h> 31 #include <linux/phy/phy.h> 32 #include <linux/pm_domain.h> 33 #include <linux/pm_runtime.h> 34 35 #include "pcie-designware.h" 36 37 #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) 38 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10) 39 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) 40 #define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12) 41 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) 42 #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 43 44 #define IMX95_PCIE_PHY_GEN_CTRL 0x0 45 #define IMX95_PCIE_REF_USE_PAD BIT(17) 46 47 #define IMX95_PCIE_SS_RW_REG_0 0xf0 48 #define IMX95_PCIE_REF_CLKEN BIT(23) 49 #define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9) 50 51 #define IMX95_PE0_GEN_CTRL_1 0x1050 52 #define IMX95_PCIE_DEVICE_TYPE GENMASK(3, 0) 53 54 #define IMX95_PE0_GEN_CTRL_3 0x1058 55 #define IMX95_PCIE_LTSSM_EN BIT(0) 56 57 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) 58 59 enum imx6_pcie_variants { 60 IMX6Q, 61 IMX6SX, 62 IMX6QP, 63 IMX7D, 64 IMX8MQ, 65 IMX8MM, 66 IMX8MP, 67 IMX95, 68 IMX8MQ_EP, 69 IMX8MM_EP, 70 IMX8MP_EP, 71 IMX95_EP, 72 }; 73 74 #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) 75 #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) 76 #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) 77 #define IMX6_PCIE_FLAG_HAS_PHYDRV BIT(3) 78 #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) 79 #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) 80 #define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) 81 #define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7) 82 83 #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) 84 85 #define IMX6_PCIE_MAX_CLKS 6 86 87 #define IMX6_PCIE_MAX_INSTANCES 2 88 89 struct imx6_pcie; 90 91 struct imx6_pcie_drvdata { 92 enum imx6_pcie_variants variant; 93 enum dw_pcie_device_mode mode; 94 u32 flags; 95 int dbi_length; 96 const char *gpr; 97 const char * const *clk_names; 98 const u32 clks_cnt; 99 const u32 ltssm_off; 100 const u32 ltssm_mask; 101 const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; 102 const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; 103 const struct pci_epc_features *epc_features; 104 int (*init_phy)(struct imx6_pcie *pcie); 105 }; 106 107 struct imx6_pcie { 108 struct dw_pcie *pci; 109 struct gpio_desc *reset_gpiod; 110 bool link_is_up; 111 struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS]; 112 struct regmap *iomuxc_gpr; 113 u16 msi_ctrl; 114 u32 controller_id; 115 struct reset_control *pciephy_reset; 116 struct reset_control *apps_reset; 117 struct reset_control *turnoff_reset; 118 u32 tx_deemph_gen1; 119 u32 tx_deemph_gen2_3p5db; 120 u32 tx_deemph_gen2_6db; 121 u32 tx_swing_full; 122 u32 tx_swing_low; 123 struct regulator *vpcie; 124 struct regulator *vph; 125 void __iomem *phy_base; 126 127 /* power domain for pcie */ 128 struct device *pd_pcie; 129 /* power domain for pcie phy */ 130 struct device *pd_pcie_phy; 131 struct phy *phy; 132 const struct imx6_pcie_drvdata *drvdata; 133 }; 134 135 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ 136 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200 137 #define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX) 138 139 /* PCIe Port Logic registers (memory-mapped) */ 140 #define PL_OFFSET 0x700 141 142 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) 143 #define PCIE_PHY_CTRL_DATA(x) FIELD_PREP(GENMASK(15, 0), (x)) 144 #define PCIE_PHY_CTRL_CAP_ADR BIT(16) 145 #define PCIE_PHY_CTRL_CAP_DAT BIT(17) 146 #define PCIE_PHY_CTRL_WR BIT(18) 147 #define PCIE_PHY_CTRL_RD BIT(19) 148 149 #define PCIE_PHY_STAT (PL_OFFSET + 0x110) 150 #define PCIE_PHY_STAT_ACK BIT(16) 151 152 /* PHY registers (not memory-mapped) */ 153 #define PCIE_PHY_ATEOVRD 0x10 154 #define PCIE_PHY_ATEOVRD_EN BIT(2) 155 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0 156 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1 157 158 #define PCIE_PHY_MPLL_OVRD_IN_LO 0x11 159 #define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2 160 #define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f 161 #define PCIE_PHY_MPLL_MULTIPLIER_OVRD BIT(9) 162 163 #define PCIE_PHY_RX_ASIC_OUT 0x100D 164 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0) 165 166 /* iMX7 PCIe PHY registers */ 167 #define PCIE_PHY_CMN_REG4 0x14 168 /* These are probably the bits that *aren't* DCC_FB_EN */ 169 #define PCIE_PHY_CMN_REG4_DCC_FB_EN 0x29 170 171 #define PCIE_PHY_CMN_REG15 0x54 172 #define PCIE_PHY_CMN_REG15_DLY_4 BIT(2) 173 #define PCIE_PHY_CMN_REG15_PLL_PD BIT(5) 174 #define PCIE_PHY_CMN_REG15_OVRD_PLL_PD BIT(7) 175 176 #define PCIE_PHY_CMN_REG24 0x90 177 #define PCIE_PHY_CMN_REG24_RX_EQ BIT(6) 178 #define PCIE_PHY_CMN_REG24_RX_EQ_SEL BIT(3) 179 180 #define PCIE_PHY_CMN_REG26 0x98 181 #define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC 182 183 #define PHY_RX_OVRD_IN_LO 0x1005 184 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) 185 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) 186 187 static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) 188 { 189 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ && 190 imx6_pcie->drvdata->variant != IMX8MQ_EP && 191 imx6_pcie->drvdata->variant != IMX8MM && 192 imx6_pcie->drvdata->variant != IMX8MM_EP && 193 imx6_pcie->drvdata->variant != IMX8MP && 194 imx6_pcie->drvdata->variant != IMX8MP_EP); 195 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; 196 } 197 198 static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie) 199 { 200 regmap_update_bits(imx6_pcie->iomuxc_gpr, 201 IMX95_PCIE_SS_RW_REG_0, 202 IMX95_PCIE_PHY_CR_PARA_SEL, 203 IMX95_PCIE_PHY_CR_PARA_SEL); 204 205 regmap_update_bits(imx6_pcie->iomuxc_gpr, 206 IMX95_PCIE_PHY_GEN_CTRL, 207 IMX95_PCIE_REF_USE_PAD, 0); 208 regmap_update_bits(imx6_pcie->iomuxc_gpr, 209 IMX95_PCIE_SS_RW_REG_0, 210 IMX95_PCIE_REF_CLKEN, 211 IMX95_PCIE_REF_CLKEN); 212 213 return 0; 214 } 215 216 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) 217 { 218 const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; 219 unsigned int mask, val, mode, id; 220 221 if (drvdata->mode == DW_PCIE_EP_TYPE) 222 mode = PCI_EXP_TYPE_ENDPOINT; 223 else 224 mode = PCI_EXP_TYPE_ROOT_PORT; 225 226 id = imx6_pcie->controller_id; 227 228 /* If mode_mask[id] is zero, means each controller have its individual gpr */ 229 if (!drvdata->mode_mask[id]) 230 id = 0; 231 232 mask = drvdata->mode_mask[id]; 233 val = mode << (ffs(mask) - 1); 234 235 regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); 236 } 237 238 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) 239 { 240 struct dw_pcie *pci = imx6_pcie->pci; 241 bool val; 242 u32 max_iterations = 10; 243 u32 wait_counter = 0; 244 245 do { 246 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) & 247 PCIE_PHY_STAT_ACK; 248 wait_counter++; 249 250 if (val == exp_val) 251 return 0; 252 253 udelay(1); 254 } while (wait_counter < max_iterations); 255 256 return -ETIMEDOUT; 257 } 258 259 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) 260 { 261 struct dw_pcie *pci = imx6_pcie->pci; 262 u32 val; 263 int ret; 264 265 val = PCIE_PHY_CTRL_DATA(addr); 266 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 267 268 val |= PCIE_PHY_CTRL_CAP_ADR; 269 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 270 271 ret = pcie_phy_poll_ack(imx6_pcie, true); 272 if (ret) 273 return ret; 274 275 val = PCIE_PHY_CTRL_DATA(addr); 276 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 277 278 return pcie_phy_poll_ack(imx6_pcie, false); 279 } 280 281 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ 282 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) 283 { 284 struct dw_pcie *pci = imx6_pcie->pci; 285 u32 phy_ctl; 286 int ret; 287 288 ret = pcie_phy_wait_ack(imx6_pcie, addr); 289 if (ret) 290 return ret; 291 292 /* assert Read signal */ 293 phy_ctl = PCIE_PHY_CTRL_RD; 294 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); 295 296 ret = pcie_phy_poll_ack(imx6_pcie, true); 297 if (ret) 298 return ret; 299 300 *data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); 301 302 /* deassert Read signal */ 303 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); 304 305 return pcie_phy_poll_ack(imx6_pcie, false); 306 } 307 308 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) 309 { 310 struct dw_pcie *pci = imx6_pcie->pci; 311 u32 var; 312 int ret; 313 314 /* write addr */ 315 /* cap addr */ 316 ret = pcie_phy_wait_ack(imx6_pcie, addr); 317 if (ret) 318 return ret; 319 320 var = PCIE_PHY_CTRL_DATA(data); 321 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 322 323 /* capture data */ 324 var |= PCIE_PHY_CTRL_CAP_DAT; 325 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 326 327 ret = pcie_phy_poll_ack(imx6_pcie, true); 328 if (ret) 329 return ret; 330 331 /* deassert cap data */ 332 var = PCIE_PHY_CTRL_DATA(data); 333 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 334 335 /* wait for ack de-assertion */ 336 ret = pcie_phy_poll_ack(imx6_pcie, false); 337 if (ret) 338 return ret; 339 340 /* assert wr signal */ 341 var = PCIE_PHY_CTRL_WR; 342 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 343 344 /* wait for ack */ 345 ret = pcie_phy_poll_ack(imx6_pcie, true); 346 if (ret) 347 return ret; 348 349 /* deassert wr signal */ 350 var = PCIE_PHY_CTRL_DATA(data); 351 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 352 353 /* wait for ack de-assertion */ 354 ret = pcie_phy_poll_ack(imx6_pcie, false); 355 if (ret) 356 return ret; 357 358 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0); 359 360 return 0; 361 } 362 363 static int imx8mq_pcie_init_phy(struct imx6_pcie *imx6_pcie) 364 { 365 /* TODO: Currently this code assumes external oscillator is being used */ 366 regmap_update_bits(imx6_pcie->iomuxc_gpr, 367 imx6_pcie_grp_offset(imx6_pcie), 368 IMX8MQ_GPR_PCIE_REF_USE_PAD, 369 IMX8MQ_GPR_PCIE_REF_USE_PAD); 370 /* 371 * Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is 372 * supplied by 3.3V, the VREG_BYPASS should be cleared to zero. 373 */ 374 if (imx6_pcie->vph && regulator_get_voltage(imx6_pcie->vph) > 3000000) 375 regmap_update_bits(imx6_pcie->iomuxc_gpr, 376 imx6_pcie_grp_offset(imx6_pcie), 377 IMX8MQ_GPR_PCIE_VREG_BYPASS, 378 0); 379 380 return 0; 381 } 382 383 static int imx7d_pcie_init_phy(struct imx6_pcie *imx6_pcie) 384 { 385 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); 386 387 return 0; 388 } 389 390 static int imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) 391 { 392 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 393 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); 394 395 /* configure constant input signal to the pcie ctrl and phy */ 396 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 397 IMX6Q_GPR12_LOS_LEVEL, 9 << 4); 398 399 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 400 IMX6Q_GPR8_TX_DEEMPH_GEN1, 401 imx6_pcie->tx_deemph_gen1 << 0); 402 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 403 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 404 imx6_pcie->tx_deemph_gen2_3p5db << 6); 405 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 406 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 407 imx6_pcie->tx_deemph_gen2_6db << 12); 408 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 409 IMX6Q_GPR8_TX_SWING_FULL, 410 imx6_pcie->tx_swing_full << 18); 411 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 412 IMX6Q_GPR8_TX_SWING_LOW, 413 imx6_pcie->tx_swing_low << 25); 414 return 0; 415 } 416 417 static int imx6sx_pcie_init_phy(struct imx6_pcie *imx6_pcie) 418 { 419 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 420 IMX6SX_GPR12_PCIE_RX_EQ_MASK, IMX6SX_GPR12_PCIE_RX_EQ_2); 421 422 return imx6_pcie_init_phy(imx6_pcie); 423 } 424 425 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) 426 { 427 u32 val; 428 struct device *dev = imx6_pcie->pci->dev; 429 430 if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, 431 IOMUXC_GPR22, val, 432 val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED, 433 PHY_PLL_LOCK_WAIT_USLEEP_MAX, 434 PHY_PLL_LOCK_WAIT_TIMEOUT)) 435 dev_err(dev, "PCIe PLL lock timeout\n"); 436 } 437 438 static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) 439 { 440 unsigned long phy_rate = 0; 441 int mult, div; 442 u16 val; 443 int i; 444 445 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 446 return 0; 447 448 for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++) 449 if (strncmp(imx6_pcie->clks[i].id, "pcie_phy", 8) == 0) 450 phy_rate = clk_get_rate(imx6_pcie->clks[i].clk); 451 452 switch (phy_rate) { 453 case 125000000: 454 /* 455 * The default settings of the MPLL are for a 125MHz input 456 * clock, so no need to reconfigure anything in that case. 457 */ 458 return 0; 459 case 100000000: 460 mult = 25; 461 div = 0; 462 break; 463 case 200000000: 464 mult = 25; 465 div = 1; 466 break; 467 default: 468 dev_err(imx6_pcie->pci->dev, 469 "Unsupported PHY reference clock rate %lu\n", phy_rate); 470 return -EINVAL; 471 } 472 473 pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); 474 val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK << 475 PCIE_PHY_MPLL_MULTIPLIER_SHIFT); 476 val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT; 477 val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD; 478 pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); 479 480 pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val); 481 val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK << 482 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT); 483 val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT; 484 val |= PCIE_PHY_ATEOVRD_EN; 485 pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val); 486 487 return 0; 488 } 489 490 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) 491 { 492 u16 tmp; 493 494 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 495 return; 496 497 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 498 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | 499 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 500 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 501 502 usleep_range(2000, 3000); 503 504 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 505 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | 506 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 507 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 508 } 509 510 #ifdef CONFIG_ARM 511 /* Added for PCI abort handling */ 512 static int imx6q_pcie_abort_handler(unsigned long addr, 513 unsigned int fsr, struct pt_regs *regs) 514 { 515 unsigned long pc = instruction_pointer(regs); 516 unsigned long instr = *(unsigned long *)pc; 517 int reg = (instr >> 12) & 15; 518 519 /* 520 * If the instruction being executed was a read, 521 * make it look like it read all-ones. 522 */ 523 if ((instr & 0x0c100000) == 0x04100000) { 524 unsigned long val; 525 526 if (instr & 0x00400000) 527 val = 255; 528 else 529 val = -1; 530 531 regs->uregs[reg] = val; 532 regs->ARM_pc += 4; 533 return 0; 534 } 535 536 if ((instr & 0x0e100090) == 0x00100090) { 537 regs->uregs[reg] = -1; 538 regs->ARM_pc += 4; 539 return 0; 540 } 541 542 return 1; 543 } 544 #endif 545 546 static int imx6_pcie_attach_pd(struct device *dev) 547 { 548 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 549 struct device_link *link; 550 551 /* Do nothing when in a single power domain */ 552 if (dev->pm_domain) 553 return 0; 554 555 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); 556 if (IS_ERR(imx6_pcie->pd_pcie)) 557 return PTR_ERR(imx6_pcie->pd_pcie); 558 /* Do nothing when power domain missing */ 559 if (!imx6_pcie->pd_pcie) 560 return 0; 561 link = device_link_add(dev, imx6_pcie->pd_pcie, 562 DL_FLAG_STATELESS | 563 DL_FLAG_PM_RUNTIME | 564 DL_FLAG_RPM_ACTIVE); 565 if (!link) { 566 dev_err(dev, "Failed to add device_link to pcie pd.\n"); 567 return -EINVAL; 568 } 569 570 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); 571 if (IS_ERR(imx6_pcie->pd_pcie_phy)) 572 return PTR_ERR(imx6_pcie->pd_pcie_phy); 573 574 link = device_link_add(dev, imx6_pcie->pd_pcie_phy, 575 DL_FLAG_STATELESS | 576 DL_FLAG_PM_RUNTIME | 577 DL_FLAG_RPM_ACTIVE); 578 if (!link) { 579 dev_err(dev, "Failed to add device_link to pcie_phy pd.\n"); 580 return -EINVAL; 581 } 582 583 return 0; 584 } 585 586 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) 587 { 588 unsigned int offset; 589 int ret = 0; 590 591 switch (imx6_pcie->drvdata->variant) { 592 case IMX6SX: 593 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 594 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); 595 break; 596 case IMX6QP: 597 case IMX6Q: 598 /* power up core phy and enable ref clock */ 599 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 600 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); 601 /* 602 * the async reset input need ref clock to sync internally, 603 * when the ref clock comes after reset, internal synced 604 * reset time is too short, cannot meet the requirement. 605 * add one ~10us delay here. 606 */ 607 usleep_range(10, 100); 608 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 609 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); 610 break; 611 case IMX7D: 612 case IMX95: 613 case IMX95_EP: 614 break; 615 case IMX8MM: 616 case IMX8MM_EP: 617 case IMX8MQ: 618 case IMX8MQ_EP: 619 case IMX8MP: 620 case IMX8MP_EP: 621 offset = imx6_pcie_grp_offset(imx6_pcie); 622 /* 623 * Set the over ride low and enabled 624 * make sure that REF_CLK is turned on. 625 */ 626 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 627 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, 628 0); 629 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 630 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, 631 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); 632 break; 633 } 634 635 return ret; 636 } 637 638 static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) 639 { 640 switch (imx6_pcie->drvdata->variant) { 641 case IMX6QP: 642 case IMX6Q: 643 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 644 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); 645 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 646 IMX6Q_GPR1_PCIE_TEST_PD, 647 IMX6Q_GPR1_PCIE_TEST_PD); 648 break; 649 case IMX7D: 650 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 651 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 652 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); 653 break; 654 default: 655 break; 656 } 657 } 658 659 static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) 660 { 661 struct dw_pcie *pci = imx6_pcie->pci; 662 struct device *dev = pci->dev; 663 int ret; 664 665 ret = clk_bulk_prepare_enable(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); 666 if (ret) 667 return ret; 668 669 ret = imx6_pcie_enable_ref_clk(imx6_pcie); 670 if (ret) { 671 dev_err(dev, "unable to enable pcie ref clock\n"); 672 goto err_ref_clk; 673 } 674 675 /* allow the clocks to stabilize */ 676 usleep_range(200, 500); 677 return 0; 678 679 err_ref_clk: 680 clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); 681 682 return ret; 683 } 684 685 static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) 686 { 687 imx6_pcie_disable_ref_clk(imx6_pcie); 688 clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); 689 } 690 691 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) 692 { 693 reset_control_assert(imx6_pcie->pciephy_reset); 694 reset_control_assert(imx6_pcie->apps_reset); 695 696 switch (imx6_pcie->drvdata->variant) { 697 case IMX6SX: 698 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 699 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 700 IMX6SX_GPR12_PCIE_TEST_POWERDOWN); 701 /* Force PCIe PHY reset */ 702 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 703 IMX6SX_GPR5_PCIE_BTNRST_RESET, 704 IMX6SX_GPR5_PCIE_BTNRST_RESET); 705 break; 706 case IMX6QP: 707 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 708 IMX6Q_GPR1_PCIE_SW_RST, 709 IMX6Q_GPR1_PCIE_SW_RST); 710 break; 711 case IMX6Q: 712 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 713 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); 714 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 715 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); 716 break; 717 default: 718 break; 719 } 720 721 /* Some boards don't have PCIe reset GPIO. */ 722 gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 1); 723 } 724 725 static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) 726 { 727 struct dw_pcie *pci = imx6_pcie->pci; 728 struct device *dev = pci->dev; 729 730 reset_control_deassert(imx6_pcie->pciephy_reset); 731 732 switch (imx6_pcie->drvdata->variant) { 733 case IMX7D: 734 /* Workaround for ERR010728, failure of PCI-e PLL VCO to 735 * oscillate, especially when cold. This turns off "Duty-cycle 736 * Corrector" and other mysterious undocumented things. 737 */ 738 if (likely(imx6_pcie->phy_base)) { 739 /* De-assert DCC_FB_EN */ 740 writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, 741 imx6_pcie->phy_base + PCIE_PHY_CMN_REG4); 742 /* Assert RX_EQS and RX_EQS_SEL */ 743 writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL 744 | PCIE_PHY_CMN_REG24_RX_EQ, 745 imx6_pcie->phy_base + PCIE_PHY_CMN_REG24); 746 /* Assert ATT_MODE */ 747 writel(PCIE_PHY_CMN_REG26_ATT_MODE, 748 imx6_pcie->phy_base + PCIE_PHY_CMN_REG26); 749 } else { 750 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); 751 } 752 753 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); 754 break; 755 case IMX6SX: 756 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 757 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); 758 break; 759 case IMX6QP: 760 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 761 IMX6Q_GPR1_PCIE_SW_RST, 0); 762 763 usleep_range(200, 500); 764 break; 765 default: 766 break; 767 } 768 769 /* Some boards don't have PCIe reset GPIO. */ 770 if (imx6_pcie->reset_gpiod) { 771 msleep(100); 772 gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 0); 773 /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ 774 msleep(100); 775 } 776 777 return 0; 778 } 779 780 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) 781 { 782 struct dw_pcie *pci = imx6_pcie->pci; 783 struct device *dev = pci->dev; 784 u32 tmp; 785 unsigned int retries; 786 787 for (retries = 0; retries < 200; retries++) { 788 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 789 /* Test if the speed change finished. */ 790 if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) 791 return 0; 792 usleep_range(100, 1000); 793 } 794 795 dev_err(dev, "Speed change timeout\n"); 796 return -ETIMEDOUT; 797 } 798 799 static void imx6_pcie_ltssm_enable(struct device *dev) 800 { 801 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 802 const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; 803 804 if (drvdata->ltssm_mask) 805 regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, 806 drvdata->ltssm_mask); 807 808 reset_control_deassert(imx6_pcie->apps_reset); 809 } 810 811 static void imx6_pcie_ltssm_disable(struct device *dev) 812 { 813 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 814 const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; 815 816 if (drvdata->ltssm_mask) 817 regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, 818 drvdata->ltssm_mask, 0); 819 820 reset_control_assert(imx6_pcie->apps_reset); 821 } 822 823 static int imx6_pcie_start_link(struct dw_pcie *pci) 824 { 825 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 826 struct device *dev = pci->dev; 827 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 828 u32 tmp; 829 int ret; 830 831 /* 832 * Force Gen1 operation when starting the link. In case the link is 833 * started in Gen2 mode, there is a possibility the devices on the 834 * bus will not be detected at all. This happens with PCIe switches. 835 */ 836 dw_pcie_dbi_ro_wr_en(pci); 837 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 838 tmp &= ~PCI_EXP_LNKCAP_SLS; 839 tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; 840 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); 841 dw_pcie_dbi_ro_wr_dis(pci); 842 843 /* Start LTSSM. */ 844 imx6_pcie_ltssm_enable(dev); 845 846 ret = dw_pcie_wait_for_link(pci); 847 if (ret) 848 goto err_reset_phy; 849 850 if (pci->link_gen > 1) { 851 /* Allow faster modes after the link is up */ 852 dw_pcie_dbi_ro_wr_en(pci); 853 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 854 tmp &= ~PCI_EXP_LNKCAP_SLS; 855 tmp |= pci->link_gen; 856 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); 857 858 /* 859 * Start Directed Speed Change so the best possible 860 * speed both link partners support can be negotiated. 861 */ 862 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 863 tmp |= PORT_LOGIC_SPEED_CHANGE; 864 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); 865 dw_pcie_dbi_ro_wr_dis(pci); 866 867 if (imx6_pcie->drvdata->flags & 868 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) { 869 /* 870 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently 871 * from i.MX6 family when no link speed transition 872 * occurs and we go Gen1 -> yep, Gen1. The difference 873 * is that, in such case, it will not be cleared by HW 874 * which will cause the following code to report false 875 * failure. 876 */ 877 878 ret = imx6_pcie_wait_for_speed_change(imx6_pcie); 879 if (ret) { 880 dev_err(dev, "Failed to bring link up!\n"); 881 goto err_reset_phy; 882 } 883 } 884 885 /* Make sure link training is finished as well! */ 886 ret = dw_pcie_wait_for_link(pci); 887 if (ret) 888 goto err_reset_phy; 889 } else { 890 dev_info(dev, "Link: Only Gen1 is enabled\n"); 891 } 892 893 imx6_pcie->link_is_up = true; 894 tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); 895 dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); 896 return 0; 897 898 err_reset_phy: 899 imx6_pcie->link_is_up = false; 900 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", 901 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), 902 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); 903 imx6_pcie_reset_phy(imx6_pcie); 904 return 0; 905 } 906 907 static void imx6_pcie_stop_link(struct dw_pcie *pci) 908 { 909 struct device *dev = pci->dev; 910 911 /* Turn off PCIe LTSSM */ 912 imx6_pcie_ltssm_disable(dev); 913 } 914 915 static int imx6_pcie_host_init(struct dw_pcie_rp *pp) 916 { 917 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 918 struct device *dev = pci->dev; 919 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 920 int ret; 921 922 if (imx6_pcie->vpcie) { 923 ret = regulator_enable(imx6_pcie->vpcie); 924 if (ret) { 925 dev_err(dev, "failed to enable vpcie regulator: %d\n", 926 ret); 927 return ret; 928 } 929 } 930 931 imx6_pcie_assert_core_reset(imx6_pcie); 932 933 if (imx6_pcie->drvdata->init_phy) 934 imx6_pcie->drvdata->init_phy(imx6_pcie); 935 936 imx6_pcie_configure_type(imx6_pcie); 937 938 ret = imx6_pcie_clk_enable(imx6_pcie); 939 if (ret) { 940 dev_err(dev, "unable to enable pcie clocks: %d\n", ret); 941 goto err_reg_disable; 942 } 943 944 if (imx6_pcie->phy) { 945 ret = phy_init(imx6_pcie->phy); 946 if (ret) { 947 dev_err(dev, "pcie PHY power up failed\n"); 948 goto err_clk_disable; 949 } 950 } 951 952 if (imx6_pcie->phy) { 953 ret = phy_power_on(imx6_pcie->phy); 954 if (ret) { 955 dev_err(dev, "waiting for PHY ready timeout!\n"); 956 goto err_phy_off; 957 } 958 } 959 960 ret = imx6_pcie_deassert_core_reset(imx6_pcie); 961 if (ret < 0) { 962 dev_err(dev, "pcie deassert core reset failed: %d\n", ret); 963 goto err_phy_off; 964 } 965 966 imx6_setup_phy_mpll(imx6_pcie); 967 968 return 0; 969 970 err_phy_off: 971 if (imx6_pcie->phy) 972 phy_exit(imx6_pcie->phy); 973 err_clk_disable: 974 imx6_pcie_clk_disable(imx6_pcie); 975 err_reg_disable: 976 if (imx6_pcie->vpcie) 977 regulator_disable(imx6_pcie->vpcie); 978 return ret; 979 } 980 981 static void imx6_pcie_host_exit(struct dw_pcie_rp *pp) 982 { 983 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 984 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 985 986 if (imx6_pcie->phy) { 987 if (phy_power_off(imx6_pcie->phy)) 988 dev_err(pci->dev, "unable to power off PHY\n"); 989 phy_exit(imx6_pcie->phy); 990 } 991 imx6_pcie_clk_disable(imx6_pcie); 992 993 if (imx6_pcie->vpcie) 994 regulator_disable(imx6_pcie->vpcie); 995 } 996 997 static const struct dw_pcie_host_ops imx6_pcie_host_ops = { 998 .init = imx6_pcie_host_init, 999 .deinit = imx6_pcie_host_exit, 1000 }; 1001 1002 static const struct dw_pcie_ops dw_pcie_ops = { 1003 .start_link = imx6_pcie_start_link, 1004 .stop_link = imx6_pcie_stop_link, 1005 }; 1006 1007 static void imx6_pcie_ep_init(struct dw_pcie_ep *ep) 1008 { 1009 enum pci_barno bar; 1010 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1011 1012 for (bar = BAR_0; bar <= BAR_5; bar++) 1013 dw_pcie_ep_reset_bar(pci, bar); 1014 } 1015 1016 static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 1017 unsigned int type, u16 interrupt_num) 1018 { 1019 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1020 1021 switch (type) { 1022 case PCI_IRQ_INTX: 1023 return dw_pcie_ep_raise_intx_irq(ep, func_no); 1024 case PCI_IRQ_MSI: 1025 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 1026 case PCI_IRQ_MSIX: 1027 return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); 1028 default: 1029 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 1030 return -EINVAL; 1031 } 1032 1033 return 0; 1034 } 1035 1036 static const struct pci_epc_features imx8m_pcie_epc_features = { 1037 .linkup_notifier = false, 1038 .msi_capable = true, 1039 .msix_capable = false, 1040 .bar[BAR_1] = { .type = BAR_RESERVED, }, 1041 .bar[BAR_3] = { .type = BAR_RESERVED, }, 1042 .align = SZ_64K, 1043 }; 1044 1045 /* 1046 * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme 1047 * ================================================================================================ 1048 * BAR0 | Enable | 64-bit | 1 MB | Programmable Size 1049 * BAR1 | Disable | 32-bit | 64 KB | Fixed Size 1050 * BAR1 should be disabled if BAR0 is 64bit. 1051 * BAR2 | Enable | 32-bit | 1 MB | Programmable Size 1052 * BAR3 | Enable | 32-bit | 64 KB | Programmable Size 1053 * BAR4 | Enable | 32-bit | 1M | Programmable Size 1054 * BAR5 | Enable | 32-bit | 64 KB | Programmable Size 1055 */ 1056 static const struct pci_epc_features imx95_pcie_epc_features = { 1057 .msi_capable = true, 1058 .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_64K, }, 1059 .align = SZ_4K, 1060 }; 1061 1062 static const struct pci_epc_features* 1063 imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) 1064 { 1065 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1066 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 1067 1068 return imx6_pcie->drvdata->epc_features; 1069 } 1070 1071 static const struct dw_pcie_ep_ops pcie_ep_ops = { 1072 .init = imx6_pcie_ep_init, 1073 .raise_irq = imx6_pcie_ep_raise_irq, 1074 .get_features = imx6_pcie_ep_get_features, 1075 }; 1076 1077 static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, 1078 struct platform_device *pdev) 1079 { 1080 int ret; 1081 unsigned int pcie_dbi2_offset; 1082 struct dw_pcie_ep *ep; 1083 struct dw_pcie *pci = imx6_pcie->pci; 1084 struct dw_pcie_rp *pp = &pci->pp; 1085 struct device *dev = pci->dev; 1086 1087 imx6_pcie_host_init(pp); 1088 ep = &pci->ep; 1089 ep->ops = &pcie_ep_ops; 1090 1091 switch (imx6_pcie->drvdata->variant) { 1092 case IMX8MQ_EP: 1093 case IMX8MM_EP: 1094 case IMX8MP_EP: 1095 pcie_dbi2_offset = SZ_1M; 1096 break; 1097 default: 1098 pcie_dbi2_offset = SZ_4K; 1099 break; 1100 } 1101 1102 pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; 1103 1104 /* 1105 * FIXME: Ideally, dbi2 base address should come from DT. But since only IMX95 is defining 1106 * "dbi2" in DT, "dbi_base2" is set to NULL here for that platform alone so that the DWC 1107 * core code can fetch that from DT. But once all platform DTs were fixed, this and the 1108 * above "dbi_base2" setting should be removed. 1109 */ 1110 if (device_property_match_string(dev, "reg-names", "dbi2") >= 0) 1111 pci->dbi_base2 = NULL; 1112 1113 if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) 1114 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 1115 1116 ret = dw_pcie_ep_init(ep); 1117 if (ret) { 1118 dev_err(dev, "failed to initialize endpoint\n"); 1119 return ret; 1120 } 1121 1122 ret = dw_pcie_ep_init_registers(ep); 1123 if (ret) { 1124 dev_err(dev, "Failed to initialize DWC endpoint registers\n"); 1125 dw_pcie_ep_deinit(ep); 1126 return ret; 1127 } 1128 1129 pci_epc_init_notify(ep->epc); 1130 1131 /* Start LTSSM. */ 1132 imx6_pcie_ltssm_enable(dev); 1133 1134 return 0; 1135 } 1136 1137 static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) 1138 { 1139 struct device *dev = imx6_pcie->pci->dev; 1140 1141 /* Some variants have a turnoff reset in DT */ 1142 if (imx6_pcie->turnoff_reset) { 1143 reset_control_assert(imx6_pcie->turnoff_reset); 1144 reset_control_deassert(imx6_pcie->turnoff_reset); 1145 goto pm_turnoff_sleep; 1146 } 1147 1148 /* Others poke directly at IOMUXC registers */ 1149 switch (imx6_pcie->drvdata->variant) { 1150 case IMX6SX: 1151 case IMX6QP: 1152 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 1153 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 1154 IMX6SX_GPR12_PCIE_PM_TURN_OFF); 1155 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 1156 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); 1157 break; 1158 default: 1159 dev_err(dev, "PME_Turn_Off not implemented\n"); 1160 return; 1161 } 1162 1163 /* 1164 * Components with an upstream port must respond to 1165 * PME_Turn_Off with PME_TO_Ack but we can't check. 1166 * 1167 * The standard recommends a 1-10ms timeout after which to 1168 * proceed anyway as if acks were received. 1169 */ 1170 pm_turnoff_sleep: 1171 usleep_range(1000, 10000); 1172 } 1173 1174 static void imx6_pcie_msi_save_restore(struct imx6_pcie *imx6_pcie, bool save) 1175 { 1176 u8 offset; 1177 u16 val; 1178 struct dw_pcie *pci = imx6_pcie->pci; 1179 1180 if (pci_msi_enabled()) { 1181 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); 1182 if (save) { 1183 val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); 1184 imx6_pcie->msi_ctrl = val; 1185 } else { 1186 dw_pcie_dbi_ro_wr_en(pci); 1187 val = imx6_pcie->msi_ctrl; 1188 dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); 1189 dw_pcie_dbi_ro_wr_dis(pci); 1190 } 1191 } 1192 } 1193 1194 static int imx6_pcie_suspend_noirq(struct device *dev) 1195 { 1196 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 1197 struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; 1198 1199 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) 1200 return 0; 1201 1202 imx6_pcie_msi_save_restore(imx6_pcie, true); 1203 imx6_pcie_pm_turnoff(imx6_pcie); 1204 imx6_pcie_stop_link(imx6_pcie->pci); 1205 imx6_pcie_host_exit(pp); 1206 1207 return 0; 1208 } 1209 1210 static int imx6_pcie_resume_noirq(struct device *dev) 1211 { 1212 int ret; 1213 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 1214 struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; 1215 1216 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) 1217 return 0; 1218 1219 ret = imx6_pcie_host_init(pp); 1220 if (ret) 1221 return ret; 1222 imx6_pcie_msi_save_restore(imx6_pcie, false); 1223 dw_pcie_setup_rc(pp); 1224 1225 if (imx6_pcie->link_is_up) 1226 imx6_pcie_start_link(imx6_pcie->pci); 1227 1228 return 0; 1229 } 1230 1231 static const struct dev_pm_ops imx6_pcie_pm_ops = { 1232 NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq, 1233 imx6_pcie_resume_noirq) 1234 }; 1235 1236 static int imx6_pcie_probe(struct platform_device *pdev) 1237 { 1238 struct device *dev = &pdev->dev; 1239 struct dw_pcie *pci; 1240 struct imx6_pcie *imx6_pcie; 1241 struct device_node *np; 1242 struct resource *dbi_base; 1243 struct device_node *node = dev->of_node; 1244 int ret; 1245 u16 val; 1246 int i; 1247 1248 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); 1249 if (!imx6_pcie) 1250 return -ENOMEM; 1251 1252 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1253 if (!pci) 1254 return -ENOMEM; 1255 1256 pci->dev = dev; 1257 pci->ops = &dw_pcie_ops; 1258 pci->pp.ops = &imx6_pcie_host_ops; 1259 1260 imx6_pcie->pci = pci; 1261 imx6_pcie->drvdata = of_device_get_match_data(dev); 1262 1263 /* Find the PHY if one is defined, only imx7d uses it */ 1264 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); 1265 if (np) { 1266 struct resource res; 1267 1268 ret = of_address_to_resource(np, 0, &res); 1269 if (ret) { 1270 dev_err(dev, "Unable to map PCIe PHY\n"); 1271 return ret; 1272 } 1273 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res); 1274 if (IS_ERR(imx6_pcie->phy_base)) 1275 return PTR_ERR(imx6_pcie->phy_base); 1276 } 1277 1278 pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base); 1279 if (IS_ERR(pci->dbi_base)) 1280 return PTR_ERR(pci->dbi_base); 1281 1282 /* Fetch GPIOs */ 1283 imx6_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1284 if (IS_ERR(imx6_pcie->reset_gpiod)) 1285 return dev_err_probe(dev, PTR_ERR(imx6_pcie->reset_gpiod), 1286 "unable to get reset gpio\n"); 1287 gpiod_set_consumer_name(imx6_pcie->reset_gpiod, "PCIe reset"); 1288 1289 if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS) 1290 return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n"); 1291 1292 for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++) 1293 imx6_pcie->clks[i].id = imx6_pcie->drvdata->clk_names[i]; 1294 1295 /* Fetch clocks */ 1296 ret = devm_clk_bulk_get(dev, imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); 1297 if (ret) 1298 return ret; 1299 1300 if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHYDRV)) { 1301 imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); 1302 if (IS_ERR(imx6_pcie->phy)) 1303 return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), 1304 "failed to get pcie phy\n"); 1305 } 1306 1307 if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) { 1308 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); 1309 if (IS_ERR(imx6_pcie->apps_reset)) 1310 return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), 1311 "failed to get pcie apps reset control\n"); 1312 } 1313 1314 if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) { 1315 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); 1316 if (IS_ERR(imx6_pcie->pciephy_reset)) 1317 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset), 1318 "Failed to get PCIEPHY reset control\n"); 1319 } 1320 1321 switch (imx6_pcie->drvdata->variant) { 1322 case IMX8MQ: 1323 case IMX8MQ_EP: 1324 case IMX7D: 1325 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) 1326 imx6_pcie->controller_id = 1; 1327 break; 1328 default: 1329 break; 1330 } 1331 1332 /* Grab turnoff reset */ 1333 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); 1334 if (IS_ERR(imx6_pcie->turnoff_reset)) { 1335 dev_err(dev, "Failed to get TURNOFF reset control\n"); 1336 return PTR_ERR(imx6_pcie->turnoff_reset); 1337 } 1338 1339 if (imx6_pcie->drvdata->gpr) { 1340 /* Grab GPR config register range */ 1341 imx6_pcie->iomuxc_gpr = 1342 syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); 1343 if (IS_ERR(imx6_pcie->iomuxc_gpr)) 1344 return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), 1345 "unable to find iomuxc registers\n"); 1346 } 1347 1348 if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) { 1349 void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app"); 1350 1351 if (IS_ERR(off)) 1352 return dev_err_probe(dev, PTR_ERR(off), 1353 "unable to find serdes registers\n"); 1354 1355 static const struct regmap_config regmap_config = { 1356 .reg_bits = 32, 1357 .val_bits = 32, 1358 .reg_stride = 4, 1359 }; 1360 1361 imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config); 1362 if (IS_ERR(imx6_pcie->iomuxc_gpr)) 1363 return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), 1364 "unable to find iomuxc registers\n"); 1365 } 1366 1367 /* Grab PCIe PHY Tx Settings */ 1368 if (of_property_read_u32(node, "fsl,tx-deemph-gen1", 1369 &imx6_pcie->tx_deemph_gen1)) 1370 imx6_pcie->tx_deemph_gen1 = 0; 1371 1372 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", 1373 &imx6_pcie->tx_deemph_gen2_3p5db)) 1374 imx6_pcie->tx_deemph_gen2_3p5db = 0; 1375 1376 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", 1377 &imx6_pcie->tx_deemph_gen2_6db)) 1378 imx6_pcie->tx_deemph_gen2_6db = 20; 1379 1380 if (of_property_read_u32(node, "fsl,tx-swing-full", 1381 &imx6_pcie->tx_swing_full)) 1382 imx6_pcie->tx_swing_full = 127; 1383 1384 if (of_property_read_u32(node, "fsl,tx-swing-low", 1385 &imx6_pcie->tx_swing_low)) 1386 imx6_pcie->tx_swing_low = 127; 1387 1388 /* Limit link speed */ 1389 pci->link_gen = 1; 1390 of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen); 1391 1392 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); 1393 if (IS_ERR(imx6_pcie->vpcie)) { 1394 if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV) 1395 return PTR_ERR(imx6_pcie->vpcie); 1396 imx6_pcie->vpcie = NULL; 1397 } 1398 1399 imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); 1400 if (IS_ERR(imx6_pcie->vph)) { 1401 if (PTR_ERR(imx6_pcie->vph) != -ENODEV) 1402 return PTR_ERR(imx6_pcie->vph); 1403 imx6_pcie->vph = NULL; 1404 } 1405 1406 platform_set_drvdata(pdev, imx6_pcie); 1407 1408 ret = imx6_pcie_attach_pd(dev); 1409 if (ret) 1410 return ret; 1411 1412 if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { 1413 ret = imx6_add_pcie_ep(imx6_pcie, pdev); 1414 if (ret < 0) 1415 return ret; 1416 } else { 1417 ret = dw_pcie_host_init(&pci->pp); 1418 if (ret < 0) 1419 return ret; 1420 1421 if (pci_msi_enabled()) { 1422 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); 1423 1424 val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); 1425 val |= PCI_MSI_FLAGS_ENABLE; 1426 dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); 1427 } 1428 } 1429 1430 return 0; 1431 } 1432 1433 static void imx6_pcie_shutdown(struct platform_device *pdev) 1434 { 1435 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); 1436 1437 /* bring down link, so bootloader gets clean state in case of reboot */ 1438 imx6_pcie_assert_core_reset(imx6_pcie); 1439 } 1440 1441 static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"}; 1442 static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"}; 1443 static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}; 1444 static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"}; 1445 1446 static const struct imx6_pcie_drvdata drvdata[] = { 1447 [IMX6Q] = { 1448 .variant = IMX6Q, 1449 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1450 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, 1451 .dbi_length = 0x200, 1452 .gpr = "fsl,imx6q-iomuxc-gpr", 1453 .clk_names = imx6q_clks, 1454 .clks_cnt = ARRAY_SIZE(imx6q_clks), 1455 .ltssm_off = IOMUXC_GPR12, 1456 .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, 1457 .mode_off[0] = IOMUXC_GPR12, 1458 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1459 .init_phy = imx6_pcie_init_phy, 1460 }, 1461 [IMX6SX] = { 1462 .variant = IMX6SX, 1463 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1464 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | 1465 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1466 .gpr = "fsl,imx6q-iomuxc-gpr", 1467 .clk_names = imx6sx_clks, 1468 .clks_cnt = ARRAY_SIZE(imx6sx_clks), 1469 .ltssm_off = IOMUXC_GPR12, 1470 .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, 1471 .mode_off[0] = IOMUXC_GPR12, 1472 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1473 .init_phy = imx6sx_pcie_init_phy, 1474 }, 1475 [IMX6QP] = { 1476 .variant = IMX6QP, 1477 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1478 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | 1479 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1480 .dbi_length = 0x200, 1481 .gpr = "fsl,imx6q-iomuxc-gpr", 1482 .clk_names = imx6q_clks, 1483 .clks_cnt = ARRAY_SIZE(imx6q_clks), 1484 .ltssm_off = IOMUXC_GPR12, 1485 .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, 1486 .mode_off[0] = IOMUXC_GPR12, 1487 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1488 .init_phy = imx6_pcie_init_phy, 1489 }, 1490 [IMX7D] = { 1491 .variant = IMX7D, 1492 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | 1493 IMX6_PCIE_FLAG_HAS_APP_RESET | 1494 IMX6_PCIE_FLAG_HAS_PHY_RESET, 1495 .gpr = "fsl,imx7d-iomuxc-gpr", 1496 .clk_names = imx6q_clks, 1497 .clks_cnt = ARRAY_SIZE(imx6q_clks), 1498 .mode_off[0] = IOMUXC_GPR12, 1499 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1500 .init_phy = imx7d_pcie_init_phy, 1501 }, 1502 [IMX8MQ] = { 1503 .variant = IMX8MQ, 1504 .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | 1505 IMX6_PCIE_FLAG_HAS_PHY_RESET, 1506 .gpr = "fsl,imx8mq-iomuxc-gpr", 1507 .clk_names = imx8mq_clks, 1508 .clks_cnt = ARRAY_SIZE(imx8mq_clks), 1509 .mode_off[0] = IOMUXC_GPR12, 1510 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1511 .mode_off[1] = IOMUXC_GPR12, 1512 .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, 1513 .init_phy = imx8mq_pcie_init_phy, 1514 }, 1515 [IMX8MM] = { 1516 .variant = IMX8MM, 1517 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | 1518 IMX6_PCIE_FLAG_HAS_PHYDRV | 1519 IMX6_PCIE_FLAG_HAS_APP_RESET, 1520 .gpr = "fsl,imx8mm-iomuxc-gpr", 1521 .clk_names = imx8mm_clks, 1522 .clks_cnt = ARRAY_SIZE(imx8mm_clks), 1523 .mode_off[0] = IOMUXC_GPR12, 1524 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1525 }, 1526 [IMX8MP] = { 1527 .variant = IMX8MP, 1528 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | 1529 IMX6_PCIE_FLAG_HAS_PHYDRV | 1530 IMX6_PCIE_FLAG_HAS_APP_RESET, 1531 .gpr = "fsl,imx8mp-iomuxc-gpr", 1532 .clk_names = imx8mm_clks, 1533 .clks_cnt = ARRAY_SIZE(imx8mm_clks), 1534 .mode_off[0] = IOMUXC_GPR12, 1535 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1536 }, 1537 [IMX95] = { 1538 .variant = IMX95, 1539 .flags = IMX6_PCIE_FLAG_HAS_SERDES, 1540 .clk_names = imx8mq_clks, 1541 .clks_cnt = ARRAY_SIZE(imx8mq_clks), 1542 .ltssm_off = IMX95_PE0_GEN_CTRL_3, 1543 .ltssm_mask = IMX95_PCIE_LTSSM_EN, 1544 .mode_off[0] = IMX95_PE0_GEN_CTRL_1, 1545 .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, 1546 .init_phy = imx95_pcie_init_phy, 1547 }, 1548 [IMX8MQ_EP] = { 1549 .variant = IMX8MQ_EP, 1550 .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | 1551 IMX6_PCIE_FLAG_HAS_PHY_RESET, 1552 .mode = DW_PCIE_EP_TYPE, 1553 .gpr = "fsl,imx8mq-iomuxc-gpr", 1554 .clk_names = imx8mq_clks, 1555 .clks_cnt = ARRAY_SIZE(imx8mq_clks), 1556 .mode_off[0] = IOMUXC_GPR12, 1557 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1558 .mode_off[1] = IOMUXC_GPR12, 1559 .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, 1560 .epc_features = &imx8m_pcie_epc_features, 1561 .init_phy = imx8mq_pcie_init_phy, 1562 }, 1563 [IMX8MM_EP] = { 1564 .variant = IMX8MM_EP, 1565 .flags = IMX6_PCIE_FLAG_HAS_PHYDRV, 1566 .mode = DW_PCIE_EP_TYPE, 1567 .gpr = "fsl,imx8mm-iomuxc-gpr", 1568 .clk_names = imx8mm_clks, 1569 .clks_cnt = ARRAY_SIZE(imx8mm_clks), 1570 .mode_off[0] = IOMUXC_GPR12, 1571 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1572 .epc_features = &imx8m_pcie_epc_features, 1573 }, 1574 [IMX8MP_EP] = { 1575 .variant = IMX8MP_EP, 1576 .flags = IMX6_PCIE_FLAG_HAS_PHYDRV, 1577 .mode = DW_PCIE_EP_TYPE, 1578 .gpr = "fsl,imx8mp-iomuxc-gpr", 1579 .clk_names = imx8mm_clks, 1580 .clks_cnt = ARRAY_SIZE(imx8mm_clks), 1581 .mode_off[0] = IOMUXC_GPR12, 1582 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1583 .epc_features = &imx8m_pcie_epc_features, 1584 }, 1585 [IMX95_EP] = { 1586 .variant = IMX95_EP, 1587 .flags = IMX6_PCIE_FLAG_HAS_SERDES | 1588 IMX6_PCIE_FLAG_SUPPORT_64BIT, 1589 .clk_names = imx8mq_clks, 1590 .clks_cnt = ARRAY_SIZE(imx8mq_clks), 1591 .ltssm_off = IMX95_PE0_GEN_CTRL_3, 1592 .ltssm_mask = IMX95_PCIE_LTSSM_EN, 1593 .mode_off[0] = IMX95_PE0_GEN_CTRL_1, 1594 .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, 1595 .init_phy = imx95_pcie_init_phy, 1596 .epc_features = &imx95_pcie_epc_features, 1597 .mode = DW_PCIE_EP_TYPE, 1598 }, 1599 }; 1600 1601 static const struct of_device_id imx6_pcie_of_match[] = { 1602 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], }, 1603 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], }, 1604 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, 1605 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], }, 1606 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], }, 1607 { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], }, 1608 { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], }, 1609 { .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], }, 1610 { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, 1611 { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, 1612 { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, 1613 { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, 1614 {}, 1615 }; 1616 1617 static struct platform_driver imx6_pcie_driver = { 1618 .driver = { 1619 .name = "imx6q-pcie", 1620 .of_match_table = imx6_pcie_of_match, 1621 .suppress_bind_attrs = true, 1622 .pm = &imx6_pcie_pm_ops, 1623 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1624 }, 1625 .probe = imx6_pcie_probe, 1626 .shutdown = imx6_pcie_shutdown, 1627 }; 1628 1629 static void imx6_pcie_quirk(struct pci_dev *dev) 1630 { 1631 struct pci_bus *bus = dev->bus; 1632 struct dw_pcie_rp *pp = bus->sysdata; 1633 1634 /* Bus parent is the PCI bridge, its parent is this platform driver */ 1635 if (!bus->dev.parent || !bus->dev.parent->parent) 1636 return; 1637 1638 /* Make sure we only quirk devices associated with this driver */ 1639 if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver) 1640 return; 1641 1642 if (pci_is_root_bus(bus)) { 1643 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1644 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 1645 1646 /* 1647 * Limit config length to avoid the kernel reading beyond 1648 * the register set and causing an abort on i.MX 6Quad 1649 */ 1650 if (imx6_pcie->drvdata->dbi_length) { 1651 dev->cfg_size = imx6_pcie->drvdata->dbi_length; 1652 dev_info(&dev->dev, "Limiting cfg_size to %d\n", 1653 dev->cfg_size); 1654 } 1655 } 1656 } 1657 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd, 1658 PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk); 1659 1660 static int __init imx6_pcie_init(void) 1661 { 1662 #ifdef CONFIG_ARM 1663 struct device_node *np; 1664 1665 np = of_find_matching_node(NULL, imx6_pcie_of_match); 1666 if (!np) 1667 return -ENODEV; 1668 of_node_put(np); 1669 1670 /* 1671 * Since probe() can be deferred we need to make sure that 1672 * hook_fault_code is not called after __init memory is freed 1673 * by kernel and since imx6q_pcie_abort_handler() is a no-op, 1674 * we can install the handler here without risking it 1675 * accessing some uninitialized driver state. 1676 */ 1677 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0, 1678 "external abort on non-linefetch"); 1679 #endif 1680 1681 return platform_driver_register(&imx6_pcie_driver); 1682 } 1683 device_initcall(imx6_pcie_init); 1684