Lines Matching +full:pcie +full:- +full:is +full:- +full:gen1
1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Freescale i.MX6 SoCs
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
31 #include <linux/phy/pcie.h>
37 #include "pcie-designware.h"
82 #define to_imx_pcie(x) dev_get_drvdata((x)->dev)
111 * Because of ERR005723 (PCIe does not support L2 power down) we need to
118 #define imx_check_flag(pci, val) (pci->drvdata->flags & val)
135 int (*init_phy)(struct imx_pcie *pcie);
136 int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable);
137 int (*core_reset)(struct imx_pcie *pcie, bool assert);
138 int (*wait_pll_lock)(struct imx_pcie *pcie);
166 /* LUT data for pcie */
168 /* power domain for pcie */
170 /* power domain for pcie phy */
175 /* Ensure that only one device's LUT is configured at any given time */
179 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
183 /* PCIe Port Logic registers (memory-mapped) */
196 /* PHY registers (not memory-mapped) */
210 /* iMX7 PCIe PHY registers */
233 WARN_ON(imx_pcie->drvdata->variant != IMX8MQ && in imx_pcie_grp_offset()
234 imx_pcie->drvdata->variant != IMX8MQ_EP && in imx_pcie_grp_offset()
235 imx_pcie->drvdata->variant != IMX8MM && in imx_pcie_grp_offset()
236 imx_pcie->drvdata->variant != IMX8MM_EP && in imx_pcie_grp_offset()
237 imx_pcie->drvdata->variant != IMX8MP && in imx_pcie_grp_offset()
238 imx_pcie->drvdata->variant != IMX8MP_EP); in imx_pcie_grp_offset()
239 return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; in imx_pcie_grp_offset()
246 * Through Beacon or PERST# De-assertion in imx95_pcie_init_phy()
248 * When the auxiliary power is not available, the controller in imx95_pcie_init_phy()
249 * cannot exit from L23 Ready with beacon or PERST# de-assertion in imx95_pcie_init_phy()
250 * when main power is not removed. in imx95_pcie_init_phy()
254 regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1, in imx95_pcie_init_phy()
257 regmap_update_bits(imx_pcie->iomuxc_gpr, in imx95_pcie_init_phy()
262 regmap_update_bits(imx_pcie->iomuxc_gpr, in imx95_pcie_init_phy()
265 regmap_update_bits(imx_pcie->iomuxc_gpr, in imx95_pcie_init_phy()
275 const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; in imx_pcie_configure_type()
278 if (drvdata->mode == DW_PCIE_EP_TYPE) in imx_pcie_configure_type()
283 id = imx_pcie->controller_id; in imx_pcie_configure_type()
285 /* If mode_mask is 0, generic PHY driver is used to set the mode */ in imx_pcie_configure_type()
286 if (!drvdata->mode_mask[0]) in imx_pcie_configure_type()
289 /* If mode_mask[id] is 0, each controller has its individual GPR */ in imx_pcie_configure_type()
290 if (!drvdata->mode_mask[id]) in imx_pcie_configure_type()
293 mask = drvdata->mode_mask[id]; in imx_pcie_configure_type()
294 val = mode << (ffs(mask) - 1); in imx_pcie_configure_type()
296 regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); in imx_pcie_configure_type()
301 struct dw_pcie *pci = imx_pcie->pci; in pcie_phy_poll_ack()
317 return -ETIMEDOUT; in pcie_phy_poll_ack()
322 struct dw_pcie *pci = imx_pcie->pci; in pcie_phy_wait_ack()
342 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
345 struct dw_pcie *pci = imx_pcie->pci; in pcie_phy_read()
371 struct dw_pcie *pci = imx_pcie->pci; in pcie_phy_write()
396 /* wait for ack de-assertion */ in pcie_phy_write()
414 /* wait for ack de-assertion */ in pcie_phy_write()
426 /* TODO: This code assumes external oscillator is being used */ in imx8mq_pcie_init_phy()
427 regmap_update_bits(imx_pcie->iomuxc_gpr, in imx8mq_pcie_init_phy()
432 * Per the datasheet, the PCIE_VPH is suggested to be 1.8V. If the in imx8mq_pcie_init_phy()
433 * PCIE_VPH is supplied by 3.3V, the VREG_BYPASS should be cleared in imx8mq_pcie_init_phy()
436 if (imx_pcie->vph && regulator_get_voltage(imx_pcie->vph) > 3000000) in imx8mq_pcie_init_phy()
437 regmap_update_bits(imx_pcie->iomuxc_gpr, in imx8mq_pcie_init_phy()
447 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx_pcie_init_phy()
450 /* configure constant input signal to the pcie ctrl and phy */ in imx_pcie_init_phy()
451 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx_pcie_init_phy()
454 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx_pcie_init_phy()
456 imx_pcie->tx_deemph_gen1 << 0); in imx_pcie_init_phy()
457 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx_pcie_init_phy()
459 imx_pcie->tx_deemph_gen2_3p5db << 6); in imx_pcie_init_phy()
460 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx_pcie_init_phy()
462 imx_pcie->tx_deemph_gen2_6db << 12); in imx_pcie_init_phy()
463 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx_pcie_init_phy()
465 imx_pcie->tx_swing_full << 18); in imx_pcie_init_phy()
466 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx_pcie_init_phy()
468 imx_pcie->tx_swing_low << 25); in imx_pcie_init_phy()
474 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6sx_pcie_init_phy()
483 struct device *dev = imx_pcie->pci->dev; in imx7d_pcie_wait_for_phy_pll_lock()
485 if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr, in imx7d_pcie_wait_for_phy_pll_lock()
490 dev_err(dev, "PCIe PLL lock timeout\n"); in imx7d_pcie_wait_for_phy_pll_lock()
496 struct device *dev = imx_pcie->pci->dev; in imx95_pcie_wait_for_phy_pll_lock()
498 if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr, in imx95_pcie_wait_for_phy_pll_lock()
503 dev_err(dev, "PCIe PLL lock timeout\n"); in imx95_pcie_wait_for_phy_pll_lock()
504 return -ETIMEDOUT; in imx95_pcie_wait_for_phy_pll_lock()
516 struct clk_bulk_data *clks = imx_pcie->clks; in imx_setup_phy_mpll()
518 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY)) in imx_setup_phy_mpll()
521 for (i = 0; i < imx_pcie->num_clks; i++) in imx_setup_phy_mpll()
541 dev_err(imx_pcie->pci->dev, in imx_setup_phy_mpll()
543 return -EINVAL; in imx_setup_phy_mpll()
567 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY)) in imx_pcie_reset_phy()
594 * make it look like it read all-ones. in imx6q_pcie_abort_handler()
602 val = -1; in imx6q_pcie_abort_handler()
604 regs->uregs[reg] = val; in imx6q_pcie_abort_handler()
605 regs->ARM_pc += 4; in imx6q_pcie_abort_handler()
610 regs->uregs[reg] = -1; in imx6q_pcie_abort_handler()
611 regs->ARM_pc += 4; in imx6q_pcie_abort_handler()
625 if (dev->pm_domain) in imx_pcie_attach_pd()
628 imx_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); in imx_pcie_attach_pd()
629 if (IS_ERR(imx_pcie->pd_pcie)) in imx_pcie_attach_pd()
630 return PTR_ERR(imx_pcie->pd_pcie); in imx_pcie_attach_pd()
632 if (!imx_pcie->pd_pcie) in imx_pcie_attach_pd()
634 link = device_link_add(dev, imx_pcie->pd_pcie, in imx_pcie_attach_pd()
639 dev_err(dev, "Failed to add device_link to pcie pd\n"); in imx_pcie_attach_pd()
640 return -EINVAL; in imx_pcie_attach_pd()
643 imx_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); in imx_pcie_attach_pd()
644 if (IS_ERR(imx_pcie->pd_pcie_phy)) in imx_pcie_attach_pd()
645 return PTR_ERR(imx_pcie->pd_pcie_phy); in imx_pcie_attach_pd()
647 link = device_link_add(dev, imx_pcie->pd_pcie_phy, in imx_pcie_attach_pd()
653 return -EINVAL; in imx_pcie_attach_pd()
661 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6sx_pcie_enable_ref_clk()
671 regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); in imx6q_pcie_enable_ref_clk()
675 * reset time is too short, cannot meet the requirement. in imx6q_pcie_enable_ref_clk()
679 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); in imx6q_pcie_enable_ref_clk()
681 regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); in imx6q_pcie_enable_ref_clk()
682 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); in imx6q_pcie_enable_ref_clk()
692 regmap_update_bits(imx_pcie->iomuxc_gpr, offset, in imx8mm_pcie_enable_ref_clk()
695 regmap_update_bits(imx_pcie->iomuxc_gpr, offset, in imx8mm_pcie_enable_ref_clk()
703 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx7d_pcie_enable_ref_clk()
711 struct dw_pcie *pci = imx_pcie->pci; in imx_pcie_clk_enable()
712 struct device *dev = pci->dev; in imx_pcie_clk_enable()
715 ret = clk_bulk_prepare_enable(imx_pcie->num_clks, imx_pcie->clks); in imx_pcie_clk_enable()
719 if (imx_pcie->drvdata->enable_ref_clk) { in imx_pcie_clk_enable()
720 ret = imx_pcie->drvdata->enable_ref_clk(imx_pcie, true); in imx_pcie_clk_enable()
722 dev_err(dev, "Failed to enable PCIe REFCLK\n"); in imx_pcie_clk_enable()
732 clk_bulk_disable_unprepare(imx_pcie->num_clks, imx_pcie->clks); in imx_pcie_clk_enable()
739 if (imx_pcie->drvdata->enable_ref_clk) in imx_pcie_clk_disable()
740 imx_pcie->drvdata->enable_ref_clk(imx_pcie, false); in imx_pcie_clk_disable()
741 clk_bulk_disable_unprepare(imx_pcie->num_clks, imx_pcie->clks); in imx_pcie_clk_disable()
747 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6sx_pcie_core_reset()
750 /* Force PCIe PHY reset */ in imx6sx_pcie_core_reset()
751 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, in imx6sx_pcie_core_reset()
758 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST, in imx6qp_pcie_core_reset()
771 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); in imx6q_pcie_core_reset()
772 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); in imx6q_pcie_core_reset()
779 struct dw_pcie *pci = imx_pcie->pci; in imx7d_pcie_core_reset()
780 struct device *dev = pci->dev; in imx7d_pcie_core_reset()
788 * PCIe: PLL may fail to lock under corner conditions. in imx7d_pcie_core_reset()
791 * cold temperature which will cause the PCIe PLL fail to lock in the in imx7d_pcie_core_reset()
794 * The Duty-cycle Corrector calibration must be disabled. in imx7d_pcie_core_reset()
796 * 1. De-assert the G_RST signal by clearing in imx7d_pcie_core_reset()
798 * 2. De-assert DCC_FB_EN by writing data “0x29” to the register in imx7d_pcie_core_reset()
804 * 5. De-assert the CMN_RST signal by clearing register bit in imx7d_pcie_core_reset()
808 if (likely(imx_pcie->phy_base)) { in imx7d_pcie_core_reset()
809 /* De-assert DCC_FB_EN */ in imx7d_pcie_core_reset()
810 writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4); in imx7d_pcie_core_reset()
813 imx_pcie->phy_base + PCIE_PHY_CMN_REG24); in imx7d_pcie_core_reset()
815 writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26); in imx7d_pcie_core_reset()
817 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); in imx7d_pcie_core_reset()
829 * From i.MX95 PCIe PHY perspective, the COLD reset toggle in imx95_pcie_core_reset()
830 * should be complete after power-up by the following sequence. in imx95_pcie_core_reset()
831 * > 10us(at power-up) in imx95_pcie_core_reset()
833 * |<------------>| in imx95_pcie_core_reset()
838 * Toggle COLD reset aligned with this sequence for i.MX95 PCIe. in imx95_pcie_core_reset()
840 regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL, in imx95_pcie_core_reset()
843 * Make sure the write to IMX95_PCIE_RST_CTRL is flushed to the in imx95_pcie_core_reset()
844 * hardware by doing a read. Otherwise, there is no guarantee in imx95_pcie_core_reset()
847 regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL, in imx95_pcie_core_reset()
850 regmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL, in imx95_pcie_core_reset()
852 regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL, in imx95_pcie_core_reset()
862 reset_control_assert(imx_pcie->pciephy_reset); in imx_pcie_assert_core_reset()
864 if (imx_pcie->drvdata->core_reset) in imx_pcie_assert_core_reset()
865 imx_pcie->drvdata->core_reset(imx_pcie, true); in imx_pcie_assert_core_reset()
867 /* Some boards don't have PCIe reset GPIO. */ in imx_pcie_assert_core_reset()
868 gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1); in imx_pcie_assert_core_reset()
873 reset_control_deassert(imx_pcie->pciephy_reset); in imx_pcie_deassert_core_reset()
875 if (imx_pcie->drvdata->core_reset) in imx_pcie_deassert_core_reset()
876 imx_pcie->drvdata->core_reset(imx_pcie, false); in imx_pcie_deassert_core_reset()
878 /* Some boards don't have PCIe reset GPIO. */ in imx_pcie_deassert_core_reset()
879 if (imx_pcie->reset_gpiod) { in imx_pcie_deassert_core_reset()
881 gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0); in imx_pcie_deassert_core_reset()
882 /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ in imx_pcie_deassert_core_reset()
891 struct dw_pcie *pci = imx_pcie->pci; in imx_pcie_wait_for_speed_change()
892 struct device *dev = pci->dev; in imx_pcie_wait_for_speed_change()
905 return -ETIMEDOUT; in imx_pcie_wait_for_speed_change()
911 const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; in imx_pcie_ltssm_enable()
912 u8 offset = dw_pcie_find_capability(imx_pcie->pci, PCI_CAP_ID_EXP); in imx_pcie_ltssm_enable()
915 tmp = dw_pcie_readl_dbi(imx_pcie->pci, offset + PCI_EXP_LNKCAP); in imx_pcie_ltssm_enable()
916 phy_set_speed(imx_pcie->phy, FIELD_GET(PCI_EXP_LNKCAP_SLS, tmp)); in imx_pcie_ltssm_enable()
917 if (drvdata->ltssm_mask) in imx_pcie_ltssm_enable()
918 regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, in imx_pcie_ltssm_enable()
919 drvdata->ltssm_mask); in imx_pcie_ltssm_enable()
921 reset_control_deassert(imx_pcie->apps_reset); in imx_pcie_ltssm_enable()
927 const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; in imx_pcie_ltssm_disable()
929 phy_set_speed(imx_pcie->phy, 0); in imx_pcie_ltssm_disable()
930 if (drvdata->ltssm_mask) in imx_pcie_ltssm_disable()
931 regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, in imx_pcie_ltssm_disable()
932 drvdata->ltssm_mask, 0); in imx_pcie_ltssm_disable()
934 reset_control_assert(imx_pcie->apps_reset); in imx_pcie_ltssm_disable()
940 struct device *dev = pci->dev; in imx_pcie_start_link()
945 if (!(imx_pcie->drvdata->flags & in imx_pcie_start_link()
952 * Force Gen1 operation when starting the link. In case the link is in imx_pcie_start_link()
953 * started in Gen2 mode, there is a possibility the devices on the in imx_pcie_start_link()
954 * bus will not be detected at all. This happens with PCIe switches. in imx_pcie_start_link()
966 if (pci->max_link_speed > 1) { in imx_pcie_start_link()
971 /* Allow faster modes after the link is up */ in imx_pcie_start_link()
975 tmp |= pci->max_link_speed; in imx_pcie_start_link()
993 dev_info(dev, "Link: Only Gen1 is enabled\n"); in imx_pcie_start_link()
1008 struct device *dev = pci->dev; in imx_pcie_stop_link()
1010 /* Turn off PCIe LTSSM */ in imx_pcie_stop_link()
1016 struct dw_pcie *pci = imx_pcie->pci; in imx_pcie_add_lut()
1017 struct device *dev = pci->dev; in imx_pcie_add_lut()
1019 int free = -1; in imx_pcie_add_lut()
1024 return -EINVAL; in imx_pcie_add_lut()
1027 guard(mutex)(&imx_pcie->lock); in imx_pcie_add_lut()
1035 regmap_write(imx_pcie->iomuxc_gpr, in imx_pcie_add_lut()
1037 regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); in imx_pcie_add_lut()
1045 regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); in imx_pcie_add_lut()
1055 dev_err(dev, "LUT entry is not available\n"); in imx_pcie_add_lut()
1056 return -ENOSPC; in imx_pcie_add_lut()
1062 regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, data1); in imx_pcie_add_lut()
1064 if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) in imx_pcie_add_lut()
1065 data2 = 0x7; /* In the EP mode, only 'Device ID' is required */ in imx_pcie_add_lut()
1069 regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, data2); in imx_pcie_add_lut()
1071 regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, free); in imx_pcie_add_lut()
1081 guard(mutex)(&imx_pcie->lock); in imx_pcie_remove_lut()
1084 regmap_write(imx_pcie->iomuxc_gpr, in imx_pcie_remove_lut()
1086 regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); in imx_pcie_remove_lut()
1088 regmap_write(imx_pcie->iomuxc_gpr, in imx_pcie_remove_lut()
1090 regmap_write(imx_pcie->iomuxc_gpr, in imx_pcie_remove_lut()
1092 regmap_write(imx_pcie->iomuxc_gpr, in imx_pcie_remove_lut()
1102 struct device *dev = imx_pcie->pci->dev; in imx_pcie_add_lut_by_rid()
1109 err_i = of_map_id(dev->of_node, rid, "iommu-map", "iommu-map-mask", in imx_pcie_add_lut_by_rid()
1117 * because the streamID is only 6 bits in imx_pcie_add_lut_by_rid()
1119 err_i = -EINVAL; in imx_pcie_add_lut_by_rid()
1123 err_m = of_map_id(dev->of_node, rid, "msi-map", "msi-map-mask", in imx_pcie_add_lut_by_rid()
1130 * support it, so return -EINVAL. in imx_pcie_add_lut_by_rid()
1131 * != 0 NULL msi-map does not exist, use built-in MSI in imx_pcie_add_lut_by_rid()
1136 return -EINVAL; in imx_pcie_add_lut_by_rid()
1138 of_node_put(target); /* Find streamID map entry for RID in msi-map */ in imx_pcie_add_lut_by_rid()
1141 * msi-map iommu-map in imx_pcie_add_lut_by_rid()
1155 * │ LUT │ 6-bit streamID │ │ in imx_pcie_add_lut_by_rid()
1157 * └─────┘ 2-bit ctrl ID │ │ in imx_pcie_add_lut_by_rid()
1169 dev_err(dev, "iommu-map and msi-map entries mismatch!\n"); in imx_pcie_add_lut_by_rid()
1170 return -EINVAL; in imx_pcie_add_lut_by_rid()
1184 struct imx_pcie *imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); in imx_pcie_enable_device()
1194 imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); in imx_pcie_disable_device()
1201 struct device *dev = pci->dev; in imx_pcie_host_init()
1205 if (imx_pcie->vpcie) { in imx_pcie_host_init()
1206 ret = regulator_enable(imx_pcie->vpcie); in imx_pcie_host_init()
1214 if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) { in imx_pcie_host_init()
1215 pp->bridge->enable_device = imx_pcie_enable_device; in imx_pcie_host_init()
1216 pp->bridge->disable_device = imx_pcie_disable_device; in imx_pcie_host_init()
1221 if (imx_pcie->drvdata->init_phy) in imx_pcie_host_init()
1222 imx_pcie->drvdata->init_phy(imx_pcie); in imx_pcie_host_init()
1228 dev_err(dev, "unable to enable pcie clocks: %d\n", ret); in imx_pcie_host_init()
1232 if (imx_pcie->phy) { in imx_pcie_host_init()
1233 ret = phy_init(imx_pcie->phy); in imx_pcie_host_init()
1235 dev_err(dev, "pcie PHY power up failed\n"); in imx_pcie_host_init()
1239 ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, in imx_pcie_host_init()
1240 imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE ? in imx_pcie_host_init()
1243 dev_err(dev, "unable to set PCIe PHY mode\n"); in imx_pcie_host_init()
1247 ret = phy_power_on(imx_pcie->phy); in imx_pcie_host_init()
1254 /* Make sure that PCIe LTSSM is cleared */ in imx_pcie_host_init()
1259 dev_err(dev, "pcie deassert core reset failed: %d\n", ret); in imx_pcie_host_init()
1263 if (imx_pcie->drvdata->wait_pll_lock) { in imx_pcie_host_init()
1264 ret = imx_pcie->drvdata->wait_pll_lock(imx_pcie); in imx_pcie_host_init()
1274 phy_power_off(imx_pcie->phy); in imx_pcie_host_init()
1276 phy_exit(imx_pcie->phy); in imx_pcie_host_init()
1280 if (imx_pcie->vpcie) in imx_pcie_host_init()
1281 regulator_disable(imx_pcie->vpcie); in imx_pcie_host_init()
1290 if (imx_pcie->phy) { in imx_pcie_host_exit()
1291 if (phy_power_off(imx_pcie->phy)) in imx_pcie_host_exit()
1292 dev_err(pci->dev, "unable to power off PHY\n"); in imx_pcie_host_exit()
1293 phy_exit(imx_pcie->phy); in imx_pcie_host_exit()
1297 if (imx_pcie->vpcie) in imx_pcie_host_exit()
1298 regulator_disable(imx_pcie->vpcie); in imx_pcie_host_exit()
1307 if (imx_pcie->drvdata->flags & IMX_PCIE_FLAG_8GT_ECN_ERR051586) { in imx_pcie_host_post_init()
1312 * is 1 which makes receiver non-compliant with the ZRX-DC in imx_pcie_host_post_init()
1329 * register is reserved, so the generic DWC implementation of sending the
1337 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF); in imx_pcie_pme_turn_off()
1338 regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF); in imx_pcie_pme_turn_off()
1382 dev_err(pci->dev, "UNKNOWN IRQ type\n"); in imx_pcie_ep_raise_irq()
1383 return -EINVAL; in imx_pcie_ep_raise_irq()
1414 * BAR0 | Enable | 64-bit | 1 MB | Programmable Size
1415 * BAR1 | Disable | 32-bit | 64 KB | Fixed Size
1416 * (BAR1 should be disabled if BAR0 is 64-bit)
1417 * BAR2 | Enable | 32-bit | 1 MB | Programmable Size
1418 * BAR3 | Enable | 32-bit | 64 KB | Programmable Size
1419 * BAR4 | Enable | 32-bit | 1 MB | Programmable Size
1420 * BAR5 | Enable | 32-bit | 64 KB | Programmable Size
1434 return imx_pcie->drvdata->epc_features; in imx_pcie_ep_get_features()
1448 struct dw_pcie *pci = imx_pcie->pci; in imx_add_pcie_ep()
1449 struct dw_pcie_rp *pp = &pci->pp; in imx_add_pcie_ep()
1450 struct device *dev = pci->dev; in imx_add_pcie_ep()
1453 ep = &pci->ep; in imx_add_pcie_ep()
1454 ep->ops = &pcie_ep_ops; in imx_add_pcie_ep()
1459 ep->page_size = imx_pcie->drvdata->epc_features->align; in imx_add_pcie_ep()
1475 pci_epc_init_notify(ep->epc); in imx_add_pcie_ep()
1484 struct dw_pcie *pci = imx_pcie->pci; in imx_pcie_msi_save_restore()
1490 imx_pcie->msi_ctrl = val; in imx_pcie_msi_save_restore()
1493 val = imx_pcie->msi_ctrl; in imx_pcie_msi_save_restore()
1506 regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, in imx_pcie_lut_save()
1508 regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); in imx_pcie_lut_save()
1509 regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); in imx_pcie_lut_save()
1511 imx_pcie->luts[i].data1 = data1; in imx_pcie_lut_save()
1512 imx_pcie->luts[i].data2 = data2; in imx_pcie_lut_save()
1514 imx_pcie->luts[i].data1 = 0; in imx_pcie_lut_save()
1515 imx_pcie->luts[i].data2 = 0; in imx_pcie_lut_save()
1525 if ((imx_pcie->luts[i].data1 & IMX95_PE0_LUT_VLD) == 0) in imx_pcie_lut_restore()
1528 regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, in imx_pcie_lut_restore()
1529 imx_pcie->luts[i].data1); in imx_pcie_lut_restore()
1530 regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, in imx_pcie_lut_restore()
1531 imx_pcie->luts[i].data2); in imx_pcie_lut_restore()
1532 regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, i); in imx_pcie_lut_restore()
1540 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) in imx_pcie_suspend_noirq()
1553 imx_pcie->drvdata->enable_ref_clk(imx_pcie, false); in imx_pcie_suspend_noirq()
1555 return dw_pcie_suspend_noirq(imx_pcie->pci); in imx_pcie_suspend_noirq()
1566 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) in imx_pcie_resume_noirq()
1570 ret = imx_pcie->drvdata->enable_ref_clk(imx_pcie, true); in imx_pcie_resume_noirq()
1579 * root complex. This is why we have to setup the rc again and in imx_pcie_resume_noirq()
1582 ret = dw_pcie_setup_rc(&imx_pcie->pci->pp); in imx_pcie_resume_noirq()
1586 ret = dw_pcie_resume_noirq(imx_pcie->pci); in imx_pcie_resume_noirq()
1604 struct device *dev = &pdev->dev; in imx_pcie_probe()
1608 struct device_node *node = dev->of_node; in imx_pcie_probe()
1614 return -ENOMEM; in imx_pcie_probe()
1618 return -ENOMEM; in imx_pcie_probe()
1620 pci->dev = dev; in imx_pcie_probe()
1621 pci->ops = &dw_pcie_ops; in imx_pcie_probe()
1623 imx_pcie->pci = pci; in imx_pcie_probe()
1624 imx_pcie->drvdata = of_device_get_match_data(dev); in imx_pcie_probe()
1626 mutex_init(&imx_pcie->lock); in imx_pcie_probe()
1628 if (imx_pcie->drvdata->ops) in imx_pcie_probe()
1629 pci->pp.ops = imx_pcie->drvdata->ops; in imx_pcie_probe()
1631 pci->pp.ops = &imx_pcie_host_dw_pme_ops; in imx_pcie_probe()
1633 /* Find the PHY if one is defined, only imx7d uses it */ in imx_pcie_probe()
1634 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); in imx_pcie_probe()
1640 dev_err(dev, "Unable to map PCIe PHY\n"); in imx_pcie_probe()
1643 imx_pcie->phy_base = devm_ioremap_resource(dev, &res); in imx_pcie_probe()
1644 if (IS_ERR(imx_pcie->phy_base)) in imx_pcie_probe()
1645 return PTR_ERR(imx_pcie->phy_base); in imx_pcie_probe()
1649 imx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); in imx_pcie_probe()
1650 if (IS_ERR(imx_pcie->reset_gpiod)) in imx_pcie_probe()
1651 return dev_err_probe(dev, PTR_ERR(imx_pcie->reset_gpiod), in imx_pcie_probe()
1653 gpiod_set_consumer_name(imx_pcie->reset_gpiod, "PCIe reset"); in imx_pcie_probe()
1656 imx_pcie->num_clks = devm_clk_bulk_get_all(dev, &imx_pcie->clks); in imx_pcie_probe()
1657 if (imx_pcie->num_clks < 0) in imx_pcie_probe()
1658 return dev_err_probe(dev, imx_pcie->num_clks, in imx_pcie_probe()
1662 imx_pcie->phy = devm_phy_get(dev, "pcie-phy"); in imx_pcie_probe()
1663 if (IS_ERR(imx_pcie->phy)) in imx_pcie_probe()
1664 return dev_err_probe(dev, PTR_ERR(imx_pcie->phy), in imx_pcie_probe()
1665 "failed to get pcie phy\n"); in imx_pcie_probe()
1669 imx_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); in imx_pcie_probe()
1670 if (IS_ERR(imx_pcie->apps_reset)) in imx_pcie_probe()
1671 return dev_err_probe(dev, PTR_ERR(imx_pcie->apps_reset), in imx_pcie_probe()
1672 "failed to get pcie apps reset control\n"); in imx_pcie_probe()
1676 imx_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); in imx_pcie_probe()
1677 if (IS_ERR(imx_pcie->pciephy_reset)) in imx_pcie_probe()
1678 return dev_err_probe(dev, PTR_ERR(imx_pcie->pciephy_reset), in imx_pcie_probe()
1682 switch (imx_pcie->drvdata->variant) { in imx_pcie_probe()
1687 return dev_err_probe(dev, -ENODEV, "no \"linux,pci-domain\" property in devicetree\n"); in imx_pcie_probe()
1689 imx_pcie->controller_id = domain; in imx_pcie_probe()
1695 if (imx_pcie->drvdata->gpr) { in imx_pcie_probe()
1697 imx_pcie->iomuxc_gpr = in imx_pcie_probe()
1698 syscon_regmap_lookup_by_compatible(imx_pcie->drvdata->gpr); in imx_pcie_probe()
1699 if (IS_ERR(imx_pcie->iomuxc_gpr)) in imx_pcie_probe()
1700 return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr), in imx_pcie_probe()
1717 imx_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config); in imx_pcie_probe()
1718 if (IS_ERR(imx_pcie->iomuxc_gpr)) in imx_pcie_probe()
1719 return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr), in imx_pcie_probe()
1723 /* Grab PCIe PHY Tx Settings */ in imx_pcie_probe()
1724 if (of_property_read_u32(node, "fsl,tx-deemph-gen1", in imx_pcie_probe()
1725 &imx_pcie->tx_deemph_gen1)) in imx_pcie_probe()
1726 imx_pcie->tx_deemph_gen1 = 0; in imx_pcie_probe()
1728 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", in imx_pcie_probe()
1729 &imx_pcie->tx_deemph_gen2_3p5db)) in imx_pcie_probe()
1730 imx_pcie->tx_deemph_gen2_3p5db = 0; in imx_pcie_probe()
1732 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", in imx_pcie_probe()
1733 &imx_pcie->tx_deemph_gen2_6db)) in imx_pcie_probe()
1734 imx_pcie->tx_deemph_gen2_6db = 20; in imx_pcie_probe()
1736 if (of_property_read_u32(node, "fsl,tx-swing-full", in imx_pcie_probe()
1737 &imx_pcie->tx_swing_full)) in imx_pcie_probe()
1738 imx_pcie->tx_swing_full = 127; in imx_pcie_probe()
1740 if (of_property_read_u32(node, "fsl,tx-swing-low", in imx_pcie_probe()
1741 &imx_pcie->tx_swing_low)) in imx_pcie_probe()
1742 imx_pcie->tx_swing_low = 127; in imx_pcie_probe()
1745 pci->max_link_speed = 1; in imx_pcie_probe()
1746 of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed); in imx_pcie_probe()
1748 imx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); in imx_pcie_probe()
1749 if (IS_ERR(imx_pcie->vpcie)) { in imx_pcie_probe()
1750 if (PTR_ERR(imx_pcie->vpcie) != -ENODEV) in imx_pcie_probe()
1751 return PTR_ERR(imx_pcie->vpcie); in imx_pcie_probe()
1752 imx_pcie->vpcie = NULL; in imx_pcie_probe()
1755 imx_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); in imx_pcie_probe()
1756 if (IS_ERR(imx_pcie->vph)) { in imx_pcie_probe()
1757 if (PTR_ERR(imx_pcie->vph) != -ENODEV) in imx_pcie_probe()
1758 return PTR_ERR(imx_pcie->vph); in imx_pcie_probe()
1759 imx_pcie->vph = NULL; in imx_pcie_probe()
1768 pci->use_parent_dt_ranges = true; in imx_pcie_probe()
1769 if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { in imx_pcie_probe()
1775 * FIXME: Only single Device (EPF) is supported due to the in imx_pcie_probe()
1780 pci->pp.use_atu_msg = true; in imx_pcie_probe()
1781 ret = dw_pcie_host_init(&pci->pp); in imx_pcie_probe()
1813 .gpr = "fsl,imx6q-iomuxc-gpr",
1827 .gpr = "fsl,imx6q-iomuxc-gpr",
1843 .gpr = "fsl,imx6q-iomuxc-gpr",
1858 .gpr = "fsl,imx7d-iomuxc-gpr",
1869 .gpr = "fsl,imx8mq-iomuxc-gpr",
1882 .gpr = "fsl,imx8mm-iomuxc-gpr",
1892 .gpr = "fsl,imx8mp-iomuxc-gpr",
1922 .gpr = "fsl,imx8mq-iomuxc-gpr",
1936 .gpr = "fsl,imx8mm-iomuxc-gpr",
1947 .gpr = "fsl,imx8mp-iomuxc-gpr",
1977 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
1978 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1979 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1980 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
1981 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
1982 { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
1983 { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
1984 { .compatible = "fsl,imx8q-pcie", .data = &drvdata[IMX8Q], },
1985 { .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], },
1986 { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
1987 { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
1988 { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
1989 { .compatible = "fsl,imx8q-pcie-ep", .data = &drvdata[IMX8Q_EP], },
1990 { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], },
1996 .name = "imx6q-pcie",
2008 struct pci_bus *bus = dev->bus; in imx_pcie_quirk()
2009 struct dw_pcie_rp *pp = bus->sysdata; in imx_pcie_quirk()
2011 /* Bus parent is the PCI bridge, its parent is this platform driver */ in imx_pcie_quirk()
2012 if (!bus->dev.parent || !bus->dev.parent->parent) in imx_pcie_quirk()
2016 if (bus->dev.parent->parent->driver != &imx_pcie_driver.driver) in imx_pcie_quirk()
2027 if (imx_pcie->drvdata->dbi_length) { in imx_pcie_quirk()
2028 dev->cfg_size = imx_pcie->drvdata->dbi_length; in imx_pcie_quirk()
2029 dev_info(&dev->dev, "Limiting cfg_size to %d\n", in imx_pcie_quirk()
2030 dev->cfg_size); in imx_pcie_quirk()
2044 return -ENODEV; in imx_pcie_init()
2049 * hook_fault_code is not called after __init memory is freed in imx_pcie_init()
2050 * by kernel and since imx6q_pcie_abort_handler() is a no-op, in imx_pcie_init()
2055 "external abort on non-linefetch"); in imx_pcie_init()