| 4c290d4f | 13-Mar-2023 |
Thomas Richter <tmricht@linux.ibm.com> |
perf vendor events s390: Add metric for TLB and cache
Add metrics for tlb and cache statistics:
- finite_cpi: Cycles per Instructions from Finite cache/memory
- est_cpi: Estimated Instruction Compl
perf vendor events s390: Add metric for TLB and cache
Add metrics for tlb and cache statistics:
- finite_cpi: Cycles per Instructions from Finite cache/memory
- est_cpi: Estimated Instruction Complexity CPI infinite Level 1
- scpl1m: Estimated Sourcing Cycles per Level 1 Miss
- tlb_percent: Estimated TLB CPU percentage of Total CPU
- tlb_miss: Estimated Cycles per TLB Miss
For details about the formulas see this documentation:
https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf
Output after:
# ./perf stat -M tlb_miss -- dd if=/dev/zero of=/dev/null bs=1M count=10K
... dd output removed
Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=1M count=10K':
667,726 DTLB2_MISSES # 440.96 tlb_miss
198 ITLB2_WRITES
795,170,260 L1C_TLB2_MISSES
9,478 ITLB2_MISSES
820 DTLB2_WRITES
1,197,126,869 L1D_PENALTY_CYCLES
2,457,447 L1I_PENALTY_CYCLES
1.249342187 seconds time elapsed
0.001030000 seconds user
1.248105000 seconds sys
#
Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
Acked-by: Ian Rogers <irogers@google.com>
Acked-By: Sumanth Korikkar <sumanthk@linux.ibm.com>
Cc: Heiko Carstens <hca@linux.ibm.com>
Cc: Sven Schnelle <svens@linux.ibm.com>
Cc: Vasily Gorbik <gor@linux.ibm.com>
Link: https://lore.kernel.org/r/20230313080201.2440201-3-tmricht@linux.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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