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/linux/Documentation/devicetree/bindings/net/can/
H A Dxilinx,can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/xilinx,can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Xilinx CAN and CANFD controller
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
16 - xlnx,zynq-can-1.0
17 - xlnx,axi-can-1.00.a
18 - xlnx,canfd-1.0
19 - xlnx,canfd-2.0
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H A Dctu,ctucanfd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/ctu,ctucanfd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CTU CAN FD Open-source IP Core
10 Open-source CAN FD IP core developed at the Czech Technical University in Prague
13 [1] sources : https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core
16 Integration in Xilinx Zynq SoC based system together with
18 [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
21 …https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-…
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/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dxilinx-xadc.txt6 The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
8 frontends for the DRP interface exist. One that is only available on the ZYNQ
9 family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
16 communication. Xilinx provides a standard IP core that can be used to access the
22 - compatible: Should be one of
23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
27 * "xlnx,system-management-wiz-1.3": When using the
30 - reg: Address and length of the register set for the device
31 - interrupts: Interrupt for the XADC control interface.
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H A Dxlnx,zynqmp-ams.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/xlnx,zynqmp-ams.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq Ultrascale AMS controller
10 - Anand Ashok Dumbre <anand.ashok.dumbre@xilinx.com>
13 The AMS (Analog Monitoring System) includes an ADC as well as on-chip sensors
14 that can be used to sample external voltages and monitor on-die operating
19 AMS controller can work with only PS, only PL and both PS and PL
27 …--------------------------------------------------------------------------------------------------…
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dxlnx,pinctrl-zynq.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,pinctrl-zynq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq Pinctrl
10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13 Please refer to pinctrl-bindings.txt in this directory for details of the
17 Zynq's pin configuration nodes act as a container for an arbitrary number of
19 pin, a group, or a list of pins or groups. This configuration can include the
21 parameters, such as pull-up, slew rate, etc.
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/linux/arch/arm/mach-zynq/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk/zynq.h>
24 #include <linux/irqchip/arm-gic.h>
32 #include <asm/mach-types.h>
36 #include <asm/hardware/cache-l2x0.h>
47 * zynq_memory_init - Initialize special memory
49 * We need to stop things allocating the low memory as DMA can't work in
50 * the 1st 512K of memory.
59 .name = "cpuidle-zynq",
63 * zynq_get_revision - Get Zynq silicon revision
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H A Dslcr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
33 * zynq_slcr_write - Write to a register in SLCR block
46 * zynq_slcr_read - Read a register in SLCR block
59 * zynq_slcr_unlock - Unlock SLCR registers
71 * zynq_slcr_get_device_id - Read device code id
87 * zynq_slcr_system_restart - Restart the entire system.
103 * the FSBL not loading the bitstream after soft-reboot in zynq_slcr_system_restart()
108 zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET); in zynq_slcr_system_restart()
118 * zynq_slcr_cpu_start - Start cpu
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/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
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/linux/Documentation/networking/device_drivers/can/ctu/
H A Dctucanfd-driver.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 CTU CAN FD Driver
9 About CTU CAN FD IP Core
10 ------------------------
12 `CTU CAN FD <https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core>`_
18 The SocketCAN driver for Xilinx Zynq SoC based MicroZed board
19 `Vivado integration <https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top>`_
20 and Intel Cyclone V 5CSEMA4U23C6 based DE0-Nano-SoC Terasic board
21 `QSys integration <https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd>`_
23 `PCIe integration <https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd>`_ of the core.
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/linux/drivers/fpga/
H A Dzynq-fpga.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2015 Xilinx Inc.
6 * FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver
13 #include <linux/dma-mapping.h>
14 #include <linux/fpga/fpga-mgr.h>
106 #define DMA_SRC_LAST_TRANSFER 1
140 writel(val, priv->io_base + offset); in zynq_fpga_write()
146 return readl(priv->io_base + offset); in zynq_fpga_read()
150 readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
166 first = priv->dma_elm == 0; in zynq_step_dma()
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/linux/drivers/clk/zynq/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Zynq PLL driver
9 #include <linux/clk/zynq.h>
10 #include <linux/clk-provider.h>
15 * struct zynq_pll - pll clock
16 * @hw: Handle between common and hardware-specific interfaces
35 #define PLLCTRL_BPQUAL_MASK (1 << 3)
37 #define PLLCTRL_PWRDWN_SHIFT 1
38 #define PLLCTRL_RESET_MASK 1
45 * zynq_pll_round_rate() - Round a clock frequency
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/linux/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
18 - Supported Use Models
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/linux/drivers/spi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 protocol. Chips that support SPI can have data transfer rates
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
18 MMC and SD cards can be accessed using SPI protocol; and for
44 If your system has an master-capable SPI controller (which
45 provides the clock and chipselect), you can enable that
56 by providing a high-level interface to send memory-like commands.
66 This enables support for SPI-NAND mode on the Airoha NAND
68 is implemented as a SPI-MEM controller.
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H A Dspi-zynq-qspi.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/spi/spi-mem.h>
28 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */
29 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */
30 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */
31 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */
52 #define ZYNQ_QSPI_CONFIG_CPOL_MASK BIT(1) /* Clock Polarity Control */
57 * QSPI Configuration Register - Baud rate and target select
109 #define ZYNQ_QSPI_TX_THRESHOLD 1 /* Tx FIFO threshold level */
121 * struct zynq_qspi - Defines qspi driver instance
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/linux/drivers/iio/adc/
H A Dxilinx-xadc-core.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2013-2014 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
8 * Documentation for the parts can be found at:
9 * - XADC hardmacro: Xilinx UG480
10 * - ZYNQ XADC interface: Xilinx UG585
11 * - AXI XADC interface: Xilinx PG019
36 #include "xilinx-xadc.h"
40 /* ZYNQ register definitions */
111 #define XADC_FLAGS_IRQ_OPTIONAL BIT(1)
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/linux/arch/arm/
H A DKconfig.debug1 # SPDX-License-Identifier: GPL-2.0
44 once the kernel has booted up - it's a one time check.
96 When a user program crashes due to an exception, the kernel can
104 1 - undefined instruction events
105 2 - system calls
106 4 - invalid data aborts
107 8 - SIGSEGV faults
108 16 - SIGBUS faults
112 bool "Kernel low-level debugging functions (read help!)"
125 prompt "Kernel low-level debugging port"
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/linux/drivers/net/can/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 tristate "CAN Device Drivers"
6 depends on CAN
8 Controller Area Network (CAN) is serial communications protocol up to
9 1Mbit/s for its original release (now known as Classical CAN) and up
10 to 8Mbit/s for the more recent CAN with Flexible Data-Rate
11 (CAN-FD). The CAN bus was originally mainly for automotive, but is now
13 applications. More information on the CAN network protocol family
14 PF_CAN is contained in <Documentation/networking/can.rst>.
16 This section contains all the CAN(-FD) device drivers including the
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/linux/Documentation/devicetree/bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
15 can be used by any driver to communicate to PMUFW(Platform Management Unit).
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
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/linux/arch/microblaze/kernel/cpu/
H A Dcpuinfo.c2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2007-2009 PetaLogix
81 {"UltraScale+ Zynq", 0x15},
107 case 1: in setup_cpuinfo()
120 " - USERSPACE CAN LOCK THIS KERNEL!\n", __func__); in setup_cpuinfo()
132 /* take timebase-frequency from DTS */ in setup_cpuinfo_clk()
133 cpuinfo.cpu_clock_freq = fcpu(cpu, "timebase-frequency"); in setup_cpuinfo_clk()
/linux/include/uapi/linux/
H A Dserial_core.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
19 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
22 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
39 * we are merged can be easily merged here.
80 /* SH-SCI */
123 /* SH-SCI */
147 /* SH-SCI */
156 /* TI OMAP-UART */
162 /* Cadence (Xilinx Zynq) UART */
171 /* ARC (Synopsys) on-chip UART */
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/linux/drivers/pinctrl/
H A Dpinctrl-zynq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Zynq pin controller
18 #include <linux/pinctrl/pinconf-generic.h>
20 #include "pinctrl-utils.h"
28 #define ZYNQ_PINMUX_MUX_SHIFT 1
32 * struct zynq_pinctrl - driver data
58 * struct zynq_pinmux_function - a pinmux function
119 PINCTRL_PIN(1, "MIO1"),
185 static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6};
234 static const unsigned int smc0_nor_cs1_pins[] = {1};
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/linux/Documentation/devicetree/bindings/display/
H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
32 - xylon,logicvc-3.02.a-display
33 - xylon,logicvc-4.01.a-display
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/linux/drivers/clk/zynqmp/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC PLL driver
5 * Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
35 PLL_MODE_FRAC = 1,
44 * zynqmp_pll_get_mode() - Get mode of PLL
45 * @hw: Handle between common and hardware-specific interfaces
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/linux/drivers/tty/serial/
H A Dxilinx_uartps.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence UART driver (found in Xilinx Zynq)
5 * Copyright (c) 2011 - 2014 Xilinx, Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
42 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
47 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
90 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
96 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
114 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
151 #define CDNS_UART_RXBS_SUPPORT BIT(1)
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