Lines Matching +full:zynq +full:- +full:can +full:- +full:1
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
15 can be used by any driver to communicate to PMUFW(Platform Management Unit).
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
27 const: xlnx,versal-firmware
29 - description: For implementations complying for Versal NET.
31 - enum:
32 - xlnx,versal-net-firmware
33 - const: xlnx,versal-firmware
37 The method of calling the PM-API firmware layer.
39 - "smc" : SMC #0, following the SMCCC
40 - "hvc" : HVC #0, following the SMCCC
42 $ref: /schemas/types.yaml#/definitions/string-array
44 - smc
45 - hvc
47 "#power-domain-cells":
48 const: 1
50 clock-controller:
51 $ref: /schemas/clock/xlnx,versal-clk.yaml#
60 $ref: /schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
65 soc-nvmem:
66 $ref: /schemas/nvmem/xlnx,zynqmp-nvmem.yaml#
72 $ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml
79 $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
84 power-management:
85 $ref: /schemas/power/reset/xlnx,zynqmp-power.yaml#
86 description: The zynqmp-power node describes the power management
90 reset-controller:
91 $ref: /schemas/reset/xlnx,zynqmp-reset.yaml#
92 description: The reset-controller node describes connection to the reset
96 versal-fpga:
97 $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
101 zynqmp-aes:
102 $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
103 description: The ZynqMP AES-GCM hardened cryptographic accelerator is
109 - compatible
114 - |
115 #include <dt-bindings/power/xlnx-zynqmp-power.h>
117 zynqmp_firmware: zynqmp-firmware {
118 #power-domain-cells = <1>;
119 soc-nvmem {
120 compatible = "xlnx,zynqmp-nvmem-fw";
121 nvmem-layout {
122 compatible = "fixed-layout";
123 #address-cells = <1>;
124 #size-cells = <1>;
126 soc_revision: soc-revision@0 {
132 compatible = "xlnx,zynqmp-gpio-modepin";
133 gpio-controller;
134 #gpio-cells = <2>;
137 compatible = "xlnx,zynqmp-pcap-fpga";
140 compatible = "xlnx,zynqmp-pinctrl";
142 power-management {
143 compatible = "xlnx,zynqmp-power";
146 reset-controller {
147 compatible = "xlnx,zynqmp-reset";
148 #reset-cells = <1>;
154 power-domains = <&zynqmp_firmware PD_SATA>;
157 versal-firmware {
158 compatible = "xlnx,versal-firmware";
161 versal_fpga: versal-fpga {
162 compatible = "xlnx,versal-fpga";
165 xlnx_aes: zynqmp-aes {
166 compatible = "xlnx,zynqmp-aes";
169 versal_clk: clock-controller {
170 #clock-cells = <1>;
171 compatible = "xlnx,versal-clk";
173 clock-names = "ref", "pl_alt_ref";