1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (c) 2011-2015 Xilinx Inc.
6  * FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver
13 #include <linux/dma-mapping.h>
14 #include <linux/fpga/fpga-mgr.h>
106 #define DMA_SRC_LAST_TRANSFER		1
140 	writel(val, priv->io_base + offset);  in zynq_fpga_write()
146 	return readl(priv->io_base + offset);  in zynq_fpga_read()
150 	readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
166 	first = priv->dma_elm == 0;  in zynq_step_dma()
167 	while (priv->cur_sg) {  in zynq_step_dma()
172 		addr = sg_dma_address(priv->cur_sg);  in zynq_step_dma()
173 		len = sg_dma_len(priv->cur_sg);  in zynq_step_dma()
174 		if (priv->dma_elm + 1 == priv->dma_nelms) {  in zynq_step_dma()
181 			priv->cur_sg = NULL;  in zynq_step_dma()
183 			priv->cur_sg = sg_next(priv->cur_sg);  in zynq_step_dma()
184 			priv->dma_elm++;  in zynq_step_dma()
193 	/* Once the first transfer is queued we can turn on the ISR, future  in zynq_step_dma()
199 	if (first && priv->cur_sg) {  in zynq_step_dma()
202 	} else if (!priv->cur_sg) {  in zynq_step_dma()
221 	spin_lock(&priv->dma_lock);  in zynq_fpga_isr()
224 	    (intr_status & IXR_DMA_DONE_MASK) && priv->cur_sg) {  in zynq_fpga_isr()
227 		spin_unlock(&priv->dma_lock);  in zynq_fpga_isr()
230 	spin_unlock(&priv->dma_lock);  in zynq_fpga_isr()
233 	complete(&priv->dma_done);  in zynq_fpga_isr()
244 	for (; count >= 4; buf += 4, count -= 4)  in zynq_fpga_has_sync()
245 		if (buf[0] == 0x66 && buf[1] == 0x55 && buf[2] == 0x99 &&  in zynq_fpga_has_sync()
259 	priv = mgr->priv;  in zynq_fpga_ops_write_init()
261 	err = clk_enable(priv->clk);  in zynq_fpga_ops_write_init()
266 	if (info->flags & FPGA_MGR_ENCRYPTED_BITSTREAM) {  in zynq_fpga_ops_write_init()
269 			dev_err(&mgr->dev,  in zynq_fpga_ops_write_init()
270 				"System not secure, can't use encrypted bitstreams\n");  in zynq_fpga_ops_write_init()
271 			err = -EINVAL;  in zynq_fpga_ops_write_init()
277 	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {  in zynq_fpga_ops_write_init()
279 			dev_err(&mgr->dev,  in zynq_fpga_ops_write_init()
281 			err = -EINVAL;  in zynq_fpga_ops_write_init()
286 		regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,  in zynq_fpga_ops_write_init()
290 		regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,  in zynq_fpga_ops_write_init()
293 		regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,  in zynq_fpga_ops_write_init()
312 			dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");  in zynq_fpga_ops_write_init()
326 			dev_err(&mgr->dev, "Timeout waiting for !PCFG_INIT\n");  in zynq_fpga_ops_write_init()
340 			dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");  in zynq_fpga_ops_write_init()
346 	 * - enable PCAP interface  in zynq_fpga_ops_write_init()
347 	 * - set throughput for maximum speed (if bistream not encrypted)  in zynq_fpga_ops_write_init()
348 	 * - set CPU in user mode  in zynq_fpga_ops_write_init()
351 	if (info->flags & FPGA_MGR_ENCRYPTED_BITSTREAM)  in zynq_fpga_ops_write_init()
365 		dev_err(&mgr->dev, "DMA command queue not right\n");  in zynq_fpga_ops_write_init()
366 		err = -EBUSY;  in zynq_fpga_ops_write_init()
374 	clk_disable(priv->clk);  in zynq_fpga_ops_write_init()
379 	clk_disable(priv->clk);  in zynq_fpga_ops_write_init()
395 	priv = mgr->priv;  in zynq_fpga_ops_write()
397 	/* The hardware can only DMA multiples of 4 bytes, and it requires the  in zynq_fpga_ops_write()
400 	for_each_sg(sgt->sgl, sg, sgt->nents, i) {  in zynq_fpga_ops_write()
401 		if ((sg->offset % 8) || (sg->length % 4)) {  in zynq_fpga_ops_write()
402 			dev_err(&mgr->dev,  in zynq_fpga_ops_write()
404 			return -EINVAL;  in zynq_fpga_ops_write()
408 	priv->dma_nelms =  in zynq_fpga_ops_write()
409 	    dma_map_sg(mgr->dev.parent, sgt->sgl, sgt->nents, DMA_TO_DEVICE);  in zynq_fpga_ops_write()
410 	if (priv->dma_nelms == 0) {  in zynq_fpga_ops_write()
411 		dev_err(&mgr->dev, "Unable to DMA map (TO_DEVICE)\n");  in zynq_fpga_ops_write()
412 		return -ENOMEM;  in zynq_fpga_ops_write()
416 	err = clk_enable(priv->clk);  in zynq_fpga_ops_write()
421 	reinit_completion(&priv->dma_done);  in zynq_fpga_ops_write()
424 	spin_lock_irqsave(&priv->dma_lock, flags);  in zynq_fpga_ops_write()
425 	priv->dma_elm = 0;  in zynq_fpga_ops_write()
426 	priv->cur_sg = sgt->sgl;  in zynq_fpga_ops_write()
428 	spin_unlock_irqrestore(&priv->dma_lock, flags);  in zynq_fpga_ops_write()
430 	time_left = wait_for_completion_timeout(&priv->dma_done,  in zynq_fpga_ops_write()
433 	spin_lock_irqsave(&priv->dma_lock, flags);  in zynq_fpga_ops_write()
435 	priv->cur_sg = NULL;  in zynq_fpga_ops_write()
436 	spin_unlock_irqrestore(&priv->dma_lock, flags);  in zynq_fpga_ops_write()
449 		err = -EIO;  in zynq_fpga_ops_write()
453 	if (priv->cur_sg ||  in zynq_fpga_ops_write()
459 		err = -EIO;  in zynq_fpga_ops_write()
467 	dev_err(&mgr->dev,  in zynq_fpga_ops_write()
478 	clk_disable(priv->clk);  in zynq_fpga_ops_write()
481 	dma_unmap_sg(mgr->dev.parent, sgt->sgl, sgt->nents, DMA_TO_DEVICE);  in zynq_fpga_ops_write()
488 	struct zynq_fpga_priv *priv = mgr->priv;  in zynq_fpga_ops_write_complete()
492 	err = clk_enable(priv->clk);  in zynq_fpga_ops_write_complete()
505 	clk_disable(priv->clk);  in zynq_fpga_ops_write_complete()
511 	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {  in zynq_fpga_ops_write_complete()
513 		regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,  in zynq_fpga_ops_write_complete()
517 		regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,  in zynq_fpga_ops_write_complete()
530 	priv = mgr->priv;  in zynq_fpga_ops_state()
532 	err = clk_enable(priv->clk);  in zynq_fpga_ops_state()
537 	clk_disable(priv->clk);  in zynq_fpga_ops_state()
555 	struct device *dev = &pdev->dev;  in zynq_fpga_probe()
562 		return -ENOMEM;  in zynq_fpga_probe()
563 	spin_lock_init(&priv->dma_lock);  in zynq_fpga_probe()
565 	priv->io_base = devm_platform_ioremap_resource(pdev, 0);  in zynq_fpga_probe()
566 	if (IS_ERR(priv->io_base))  in zynq_fpga_probe()
567 		return PTR_ERR(priv->io_base);  in zynq_fpga_probe()
569 	priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node,  in zynq_fpga_probe()
571 	if (IS_ERR(priv->slcr)) {  in zynq_fpga_probe()
572 		dev_err(dev, "unable to get zynq-slcr regmap\n");  in zynq_fpga_probe()
573 		return PTR_ERR(priv->slcr);  in zynq_fpga_probe()
576 	init_completion(&priv->dma_done);  in zynq_fpga_probe()
578 	priv->irq = platform_get_irq(pdev, 0);  in zynq_fpga_probe()
579 	if (priv->irq < 0)  in zynq_fpga_probe()
580 		return priv->irq;  in zynq_fpga_probe()
582 	priv->clk = devm_clk_get(dev, "ref_clk");  in zynq_fpga_probe()
583 	if (IS_ERR(priv->clk))  in zynq_fpga_probe()
584 		return dev_err_probe(dev, PTR_ERR(priv->clk),  in zynq_fpga_probe()
587 	err = clk_prepare_enable(priv->clk);  in zynq_fpga_probe()
598 	err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, dev_name(dev),  in zynq_fpga_probe()
602 		clk_disable_unprepare(priv->clk);  in zynq_fpga_probe()
606 	clk_disable(priv->clk);  in zynq_fpga_probe()
608 	mgr = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager",  in zynq_fpga_probe()
612 		clk_unprepare(priv->clk);  in zynq_fpga_probe()
627 	priv = mgr->priv;  in zynq_fpga_remove()
631 	clk_unprepare(priv->clk);  in zynq_fpga_remove()
636 	{ .compatible = "xlnx,zynq-devcfg-1.0", },
656 MODULE_DESCRIPTION("Xilinx Zynq FPGA Manager");