Lines Matching +full:zynq +full:- +full:can +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
33 * zynq_slcr_write - Write to a register in SLCR block
46 * zynq_slcr_read - Read a register in SLCR block
59 * zynq_slcr_unlock - Unlock SLCR registers
71 * zynq_slcr_get_device_id - Read device code id
87 * zynq_slcr_system_restart - Restart the entire system.
103 * the FSBL not loading the bitstream after soft-reboot in zynq_slcr_system_restart()
108 zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET); in zynq_slcr_system_restart()
118 * zynq_slcr_cpu_start - Start cpu
135 * zynq_slcr_cpu_stop - Stop cpu
148 * zynq_slcr_cpu_state_read - Read cpu state
152 * 0 means cpu is running, 1 cpu is going to die.
161 state &= 1 << (31 - cpu); in zynq_slcr_cpu_state_read()
167 * zynq_slcr_cpu_state_write - Write cpu state
169 * @die: cpu state - true if cpu is going to die
172 * 0 means cpu is running, 1 cpu is going to die.
179 mask = 1 << (31 - cpu); in zynq_slcr_cpu_state_write()
188 * zynq_early_slcr_init - Early slcr init function
198 np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); in zynq_early_slcr_init()
210 np->data = (__force void *)zynq_slcr_base; in zynq_early_slcr_init()
212 zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr"); in zynq_early_slcr_init()
214 pr_err("%s: failed to find zynq-slcr\n", __func__); in zynq_early_slcr_init()
216 return -ENODEV; in zynq_early_slcr_init()
219 /* unlock the SLCR so that registers can be changed */ in zynq_early_slcr_init()