Lines Matching +full:zynq +full:- +full:can +full:- +full:1

6 The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
8 frontends for the DRP interface exist. One that is only available on the ZYNQ
9 family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
16 communication. Xilinx provides a standard IP core that can be used to access the
22 	- compatible: Should be one of
23 		* "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
25 		* "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
27 		* "xlnx,system-management-wiz-1.3": When using the
30 	- reg: Address and length of the register set for the device
31 	- interrupts: Interrupt for the XADC control interface.
32 	- clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
33 	  when using the axi-xadc or the axi-system-management-wizard this must be
37 	- xlnx,external-mux:
44 	- xlnx,external-mux-channel: Configures which pair of pins is used to
48 		1: VAUXP[0]/VAUXN[0]
49 		2: VAUXP[1]/VAUXN[1]
53 		1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
54 		2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
56 		8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
61 	- xnlx,channels: List of external channels that are connected to the ADC
63 		* #address-cells: Should be 1.
64 		* #size-cells: Should be 0.
75 				1: VAUXP[0]/VAUXN[0]
76 				2: VAUXP[1]/VAUXN[1]
88 		compatible = "xlnx,zynq-xadc-1.00.a";
91 		interrupt-parent = <&gic>;
95 			#address-cells = <1>;
96 			#size-cells = <0>;
100 			channel@1 {
101 				reg = <1>;
110 		compatible = "xlnx,axi-xadc-1.00.a";
113 		interrupt-parent = <&gic>;
117 			#address-cells = <1>;
118 			#size-cells = <0>;
127 		compatible = "xlnx,system-management-wiz-1.3";
130 		interrupt-parent = <&gic>;
134 			#address-cells = <1>;
135 			#size-cells = <0>;