spi: atcspi200: enable compile testing

There seems to be nothing preventing this driver from being compile
tested so enable that for wider build coverage.

Signed-off-by: Johan Hovold <johan@kernel.

spi: atcspi200: enable compile testing

There seems to be nothing preventing this driver from being compile
tested so enable that for wider build coverage.

Signed-off-by: Johan Hovold <johan@kernel.org>
Link: https://patch.msgid.link/20260409145618.466701-1-johan@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: pl022: enable compile testing

There seems to be nothing preventing this driver from being compile
tested so enable that for wider build coverage.

Signed-off-by: Johan Hovold <johan@kernel.org>

spi: pl022: enable compile testing

There seems to be nothing preventing this driver from being compile
tested so enable that for wider build coverage.

Signed-off-by: Johan Hovold <johan@kernel.org>
Link: https://patch.msgid.link/20260408084407.107416-1-johan@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: dw: Remove not-going-to-be-supported code for Baikal SoC

As noticed in the discussion [1] the Baikal SoC and platforms
are not going to be finalized, hence remove stale code.

Link: https://lor

spi: dw: Remove not-going-to-be-supported code for Baikal SoC

As noticed in the discussion [1] the Baikal SoC and platforms
are not going to be finalized, hence remove stale code.

Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1]
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/20260127210541.4068379-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: SPI_AXIADO should depend on ARCH_AXIADO

The Axiado DB-H SPI controller is only present on Axiado AX3000 SoCs.
Hence add a dependency on ARCH_AXIADO, to prevent asking the user about
this driver

spi: SPI_AXIADO should depend on ARCH_AXIADO

The Axiado DB-H SPI controller is only present on Axiado AX3000 SoCs.
Hence add a dependency on ARCH_AXIADO, to prevent asking the user about
this driver when configuring a kernel without Axiado SoC Family support.

Fixes: e75a6b00ad7962a7 ("spi: axiado: Add driver for Axiado SPI DB controller")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/386273d50fb3c51cccdba4b3101a0705208abd4d.1769540444.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>

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Axiado AX3000 SoC SPI DB controller driver

Merge series from Vladimir Moravcevic <vmoravcevic@axiado.com>:

This series introduces new SPI controller driver for Axiado AX3000 SoC
and its evaluation

Axiado AX3000 SoC SPI DB controller driver

Merge series from Vladimir Moravcevic <vmoravcevic@axiado.com>:

This series introduces new SPI controller driver for Axiado AX3000 SoC
and its evaluation board.

The SPI controller provides:
- Full-duplex and half-duplex transfer support
- Configurable clock polarity and phase
- Interrupt-driven

Functionality has been verified using the `jedec,spi-nor` interface to
access onboard flash memory. This ensures compatibility with common NOR
flash devices used in boot and storage subsystem.

Further improvements, including performance tuning and extended hardware
feature support, will be submitted in follow-up patches.

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spi: axiado: Add driver for Axiado SPI DB controller

The Axiado SPI controller is present in AX3000 SoC and Evaluation Board.
This controller is operating in Host only mode.

Co-developed-by: Prasad

spi: axiado: Add driver for Axiado SPI DB controller

The Axiado SPI controller is present in AX3000 SoC and Evaluation Board.
This controller is operating in Host only mode.

Co-developed-by: Prasad Bolisetty <pbolisetty@axiado.com>
Signed-off-by: Prasad Bolisetty <pbolisetty@axiado.com>
Signed-off-by: Vladimir Moravcevic <vmoravcevic@axiado.com>
Link: https://patch.msgid.link/20260107-axiado-ax3000-soc-spi-db-controller-driver-v3-2-726e70cf19ad@axiado.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: atcspi200: Add support for Andes ATCSPI200 SPI

Merge series from CL Wang <cl634@andestech.com>:

This series adds support for the Andes ATCSPI200 SPI controller.

spi: atcspi200: Add ATCSPI200 SPI controller driver

Add driver for the Andes ATCSPI200 SPI controller.

Signed-off-by: CL Wang <cl634@andestech.com>
Link: https://patch.msgid.link/20251215132349.513

spi: atcspi200: Add ATCSPI200 SPI controller driver

Add driver for the Andes ATCSPI200 SPI controller.

Signed-off-by: CL Wang <cl634@andestech.com>
Link: https://patch.msgid.link/20251215132349.513843-3-cl634@andestech.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: add driver for NXP XSPI controller

Add driver support for NXP XSPI controller.

XSPI is a flexible SPI host controller which supports up to
2 external devices (2 CS). It support Single/Dual/Qua

spi: add driver for NXP XSPI controller

Add driver support for NXP XSPI controller.

XSPI is a flexible SPI host controller which supports up to
2 external devices (2 CS). It support Single/Dual/Quad/Octal
mode data transfer.

The difference between XSPI and Flexspi:
1.the register layout is total different.
2.XSPI support multiple independent execution environments
(EENVs) for HW virtualization with some limitations. Each EENV
has its own interrupt and its own set of programming registers
that exists in a specific offset range in the XSPI memory map.
The main environment (EENV0) address space contains all of the
registers for controlling EENV0 plus all of the general XSPI
control and programming registers. The register mnemonics for
the user environments (EENV1 to EENV4) have "_SUB_n" appended
to the mnemonic for the corresponding main-environment register.

Current driver based on EENV0, which means system already give
EENV0 right to linux.

This driver use SPI memory interface of the SPI framework to
issue flash memory operations. Tested this driver with UBIFS
and mtd_debug on NXP i.MX943 EVK board which has one spi nor
MT35XU512ABA flash. Now this driver has the following key
features:
- Support up to OCT DDR mode
- Support AHB read
- Support IP read and IP write
- Support two CS

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://patch.msgid.link/20251216-xspi-v7-2-282525220979@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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Merge tag 'spi-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi updates from Mark Brown:
"This release is almost entirely new drivers, with a couple of small
changes i

Merge tag 'spi-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi updates from Mark Brown:
"This release is almost entirely new drivers, with a couple of small
changes in generic code.

The biggest individual update is a rename of the existing Microchip
driver and the addition of a new driver for the silicon SPI controller
in their PolarFire SoCs. The overlap between the soft IP supported by
the current driver and this new one is regrettably all in the IP and
not in the register interface offered to software.

- Add a time offset parameter for offloads, allowing them to be
defined in relation to each other. This is useful for IIO type
applcations where you trigger an operation then read the result
after a delay.

- Add a tracepoint for flash exec_ops, bringing the flash support
more in line with the debuggability of vanilla SPI.

- Support for Airoha EN7523, Arduino MCUs, Aspeed AST2700, Microchip
PolarFire SPI controllers, NXP i.MX51 ECSPI target mode, Qualcomm
IPQ5414 and IPQ5332, Renesas RZ/T2H, RZ/V2N and RZ/2NH and SpacemiT
K1 QuadSPI.

There's also a small set of ASoC cleanups that I mistakenly applied to
the SPI tree and then put more stuff on top of before it was brought
to my attention, sorry about that"

* tag 'spi-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (80 commits)
spi: microchip-core: Refactor FIFO read and write handlers
spi: ch341: fix out-of-bounds memory access in ch341_transfer_one
spi: microchip-core: Remove unneeded PM related macro
spi: microchip-core: Use SPI_MODE_X_MASK
spi: microchip-core: Utilise temporary variable for struct device
spi: microchip-core: Replace dead code (-ENOMEM error message)
spi: microchip-core: use min() instead of min_t()
spi: dt-bindings: airoha: add compatible for EN7523
spi: airoha-snfi: en7523: workaround flash damaging if UART_TXD was short to GND
spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support
spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support
spi: microchip: Enable compile-testing for FPGA SPI controllers
spi: Fix potential uninitialized variable in probe()
spi: rzv2h-rspi: add support for RZ/T2H and RZ/N2H
spi: dt-bindings: renesas,rzv2h-rspi: document RZ/T2H and RZ/N2H
spi: rzv2h-rspi: add support for loopback mode
spi: rzv2h-rspi: add support for variable transfer clock
spi: rzv2h-rspi: add support for using PCLK for transfer clock
spi: rzv2h-rspi: make transfer clock rate finding chip-specific
spi: rzv2h-rspi: avoid recomputing transfer frequency
...

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spi: tegra114: remove Kconfig dependency on TEGRA20_APB_DMA

This driver runs also on Tegra SoCs without a Tegra20 APB DMA controller
(e.g. Tegra234).
Remove the Kconfig dependency on TEGRA20_APB_DMA

spi: tegra114: remove Kconfig dependency on TEGRA20_APB_DMA

This driver runs also on Tegra SoCs without a Tegra20 APB DMA controller
(e.g. Tegra234).
Remove the Kconfig dependency on TEGRA20_APB_DMA; in addition, amend the
help text to reflect the fact that this driver works on SoCs different from
Tegra114.

Fixes: bb9667d8187b ("arm64: tegra: Add SPI device tree nodes for Tegra234")
Signed-off-by: Francesco Lavra <flavra@baylibre.com>
Link: https://patch.msgid.link/20251126095027.4102004-1-flavra@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: microchip: Enable compile-testing for FPGA SPI controllers

The Microchip FPGA SPI controller driver builds fine on other platforms.

While at it, drop a superfluous empty line.

Signed-off-by:

spi: microchip: Enable compile-testing for FPGA SPI controllers

The Microchip FPGA SPI controller driver builds fine on other platforms.

While at it, drop a superfluous empty line.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/6f96848b026f9a343b80d48179149b30c6b76d1d.1764086805.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>

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Add support for Microchip CoreSPI Controller

Merge series from Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>:

This patch series adds support for the Microchip FPGA CoreSPI "soft" IP
an

Add support for Microchip CoreSPI Controller

Merge series from Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>:

This patch series adds support for the Microchip FPGA CoreSPI "soft" IP
and documents its device tree bindings.

As preparation, the existing Microchip SPI driver is renamed to clearly
indicate that it supports only the Microchip PolarFire SoC "hard" controller.
Although it was originally named with the expectation that it might also
cover the FPGA CoreSPI "soft" IP, the register layouts differ significantly,
so separate drivers are required.

show more ...

spi: add support for microchip "soft" spi controller

Introduce driver support for the Microchip FPGA CoreSPI IP.

This driver supports only Motorola SPI mode and frame size of 8-bits.
TI/NSC modes a

spi: add support for microchip "soft" spi controller

Introduce driver support for the Microchip FPGA CoreSPI IP.

This driver supports only Motorola SPI mode and frame size of 8-bits.
TI/NSC modes and wider frame sizes are not currently supported.

Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251114104545.284765-4-prajna.rajendrakumar@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: microchip: rename driver file and internal identifiers

The spi-microchip-core.c driver provides support for the Microchip
PolarFire SoC (MPFS) "hard" SPI controller. It was originally named
"co

spi: microchip: rename driver file and internal identifiers

The spi-microchip-core.c driver provides support for the Microchip
PolarFire SoC (MPFS) "hard" SPI controller. It was originally named
"core" with the expectation that it might also cover Microchip's
CoreSPI "soft" IP, but that never materialized.

The CoreSPI IP cannot be supported by this driver because its register
layout differs substantially from the MPFS SPI controller. In practice
most of the code would need to be replaced to handle those differences
so keeping the drivers separate is the simpler approach.

The file and internal symbols are renamed to reflect MPFS support and
to free up "spi-microchip-core.c" for CoreSPI driver.

Fixes: 9ac8d17694b6 ("spi: add support for microchip fpga spi controllers")
Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251114104545.284765-2-prajna.rajendrakumar@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: fsl-qspi: support the SpacemiT K1 SoC

Allow the SPI_FSL_QUADSPI Kconfig option to be selected if ARCH_SPACEMIT
enabled.

Add support for the SpacemiT K1 SoC in the Freescale QSPI driver by
defi

spi: fsl-qspi: support the SpacemiT K1 SoC

Allow the SPI_FSL_QUADSPI Kconfig option to be selected if ARCH_SPACEMIT
enabled.

Add support for the SpacemiT K1 SoC in the Freescale QSPI driver by
defining the device type data for its QSPI implementation.

Signed-off-by: Alex Elder <elder@riscstar.com>
Link: https://patch.msgid.link/20251027133008.360237-8-elder@riscstar.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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Merge tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC driver updates from Arnd Bergmann:
"Lots of platform specific updates for Qualcomm SoCs, including a n

Merge tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC driver updates from Arnd Bergmann:
"Lots of platform specific updates for Qualcomm SoCs, including a new
TEE subsystem driver for the Qualcomm QTEE firmware interface.

Added support for the Apple A11 SoC in drivers that are shared with
the M1/M2 series, among more updates for those.

Smaller platform specific driver updates for Renesas, ASpeed,
Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale
SoCs.

Driver updates in the cache controller, memory controller and reset
controller subsystems.

SCMI firmware updates to add more features and improve robustness.
This includes support for having multiple SCMI providers in a single
system.

TEE subsystem support for protected DMA-bufs, allowing hardware to
access memory areas that managed by the kernel but remain inaccessible
from the CPU in EL1/EL0"

* tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits)
soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu()
soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
soc: fsl: qe: Change GPIO driver to a proper platform driver
tee: fix register_shm_helper()
pmdomain: apple: Add "apple,t8103-pmgr-pwrstate"
dt-bindings: spmi: Add Apple A11 and T2 compatible
serial: qcom-geni: Load UART qup Firmware from linux side
spi: geni-qcom: Load spi qup Firmware from linux side
i2c: qcom-geni: Load i2c qup Firmware from linux side
soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
soc: qcom: geni-se: Cleanup register defines and update copyright
dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus
Documentation: tee: Add Qualcomm TEE driver
tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl
tee: qcom: add primordial object
tee: add Qualcomm TEE driver
tee: increase TEE_MAX_ARG_SIZE to 4096
tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF
tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF
tee: add close_context to TEE driver operation
...

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SPI: Add virtio SPI driver

This is the virtio SPI Linux kernel driver.

Signed-off-by: Haixu Cui <quic_haixcui@quicinc.com>
Link: https://patch.msgid.link/20250908092348.1283552-4-quic_haixcui@quici

SPI: Add virtio SPI driver

This is the virtio SPI Linux kernel driver.

Signed-off-by: Haixu Cui <quic_haixcui@quicinc.com>
Link: https://patch.msgid.link/20250908092348.1283552-4-quic_haixcui@quicinc.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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support for Amlogic SPI Flash Controller IP

Merge series from Xianwei Zhao <xianwei.zhao@amlogic.com>:

This Flash Controller is derived by adding an SPI path to the original
raw NAND controller. Th

support for Amlogic SPI Flash Controller IP

Merge series from Xianwei Zhao <xianwei.zhao@amlogic.com>:

This Flash Controller is derived by adding an SPI path to the original
raw NAND controller. This controller supports two modes: raw mode and
SPI mode. The raw mode has already been implemented in the community
(drivers/mtd/nand/raw/meson_nand.c).
This submission supports the SPI mode.

Add the drivers and bindings corresponding to the SPI Flash Controller.

show more ...

spi: amlogic: add driver for Amlogic SPI Flash Controller

This driver provides support for the SPI mode of the Amlogic
Flash Controller. It supports both SPI NOR flash and SPI NAND
flash. For SPI NA

spi: amlogic: add driver for Amlogic SPI Flash Controller

This driver provides support for the SPI mode of the Amlogic
Flash Controller. It supports both SPI NOR flash and SPI NAND
flash. For SPI NAND, the Host ECC hardware engine can be enabled.

The controller implements the SPI-MEM interface and does not
support generic SPI.

Signed-off-by: Feng Chen <feng.chen@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://patch.msgid.link/20250910-spifc-v6-2-1574aa9baebd@amlogic.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: atmel: make it selectable for ARCH_MICROCHIP

LAN969x uses the Atmel SPI, so make it selectable for ARCH_MICROCHIP to
avoid needing to update depends in future if other Microchip SoC-s use it
as

spi: atmel: make it selectable for ARCH_MICROCHIP

LAN969x uses the Atmel SPI, so make it selectable for ARCH_MICROCHIP to
avoid needing to update depends in future if other Microchip SoC-s use it
as well.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Daniel Machon <daniel.machon@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>

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spi: rb4xx: add COMPILE_TEST support

Copy macros from ath79 SPI driver to allow compilation on all platforms
and remove ath79 specific header.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
Message-

spi: rb4xx: add COMPILE_TEST support

Copy macros from ath79 SPI driver to allow compilation on all platforms
and remove ath79 specific header.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
Message-ID: <20250826212413.15065-3-rosenp@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

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spi: rb4xx: depend on OF

There's no support for non OF platforms. Better to depend on OF
explicitly.

Also fixes a warning/error about the dt table being unused because of
of_match_ptr on non OF pla

spi: rb4xx: depend on OF

There's no support for non OF platforms. Better to depend on OF
explicitly.

Also fixes a warning/error about the dt table being unused because of
of_match_ptr on non OF platforms.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
Message-ID: <20250826212413.15065-2-rosenp@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

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Add RSPI support for RZ/V2H

Merge series from Fabrizio Castro <fabrizio.castro.jz@renesas.com>:

This series adds support for the Renesas RZ/V2H RSPI IP.

support for amlogic the new SPI IP

Merge series from Xianwei Zhao <xianwei.zhao@amlogic.com>:

Introduced support for the new SPI IP (SPISG). The SPISG is
a communication-oriented SPI controller fro

support for amlogic the new SPI IP

Merge series from Xianwei Zhao <xianwei.zhao@amlogic.com>:

Introduced support for the new SPI IP (SPISG). The SPISG is
a communication-oriented SPI controller from Amlogic,supporting
three operation modes: PIO, block DMA, and scatter-gather DMA.

Add the drivers and device tree bindings corresponding to the SPISG.

show more ...