xref: /linux/include/uapi/linux/serial_core.h (revision ab1c247094e323177a578b38f0325bf79f0317ac)
1e2be04c7SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
2607ca46eSDavid Howells /*
3607ca46eSDavid Howells  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
4607ca46eSDavid Howells  */
5607ca46eSDavid Howells #ifndef _UAPILINUX_SERIAL_CORE_H
6607ca46eSDavid Howells #define _UAPILINUX_SERIAL_CORE_H
7607ca46eSDavid Howells 
8607ca46eSDavid Howells #include <linux/serial.h>
9607ca46eSDavid Howells 
10607ca46eSDavid Howells /*
11607ca46eSDavid Howells  * The type definitions.  These are from Ted Ts'o's serial.h
1254b45ee8SAndy Shevchenko  * By historical reasons the values from 0 to 13 are defined
1354b45ee8SAndy Shevchenko  * in the include/uapi/linux/serial.h, do not define them here.
1400c77bcfSWolfram Sang  * Values 0 to 19 are used by setserial from busybox and must never
1500c77bcfSWolfram Sang  * be modified.
16607ca46eSDavid Howells  */
17607ca46eSDavid Howells #define PORT_NS16550A	14
18607ca46eSDavid Howells #define PORT_XSCALE	15
19607ca46eSDavid Howells #define PORT_RM9000	16	/* PMC-Sierra RM9xxx internal UART */
20607ca46eSDavid Howells #define PORT_OCTEON	17	/* Cavium OCTEON internal UART */
21607ca46eSDavid Howells #define PORT_AR7	18	/* Texas Instruments AR7 internal UART */
22607ca46eSDavid Howells #define PORT_U6_16550A	19	/* ST-Ericsson U6xxx internal UART */
23607ca46eSDavid Howells #define PORT_TEGRA	20	/* NVIDIA Tegra internal UART */
24607ca46eSDavid Howells #define PORT_XR17D15X	21	/* Exar XR17D15x UART */
25607ca46eSDavid Howells #define PORT_LPC3220	22	/* NXP LPC32xx SoC "Standard" UART */
26607ca46eSDavid Howells #define PORT_8250_CIR	23	/* CIR infrared port, has its own driver */
27dc96efb7SMatt Schulte #define PORT_XR17V35X	24	/* Exar XR17V35x UARTs */
2885f02440SMichael Chan #define PORT_BRCM_TRUMANAGE	25
29e06c93caSLey Foon Tan #define PORT_ALTR_16550_F32 26	/* Altera 16550 UART with 32 FIFOs */
30e06c93caSLey Foon Tan #define PORT_ALTR_16550_F64 27	/* Altera 16550 UART with 64 FIFOs */
31e06c93caSLey Foon Tan #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
329b8777e3SJohn Crispin #define PORT_RT2880	29	/* Ralink RT2880 internal UART */
33fddceb8bSVijay Rai #define PORT_16550A_FSL64 30	/* Freescale 16550 UART with 64 FIFOs */
34607ca46eSDavid Howells 
35607ca46eSDavid Howells /*
36607ca46eSDavid Howells  * ARM specific type numbers.  These are not currently guaranteed
37607ca46eSDavid Howells  * to be implemented, and will change in the future.  These are
38607ca46eSDavid Howells  * separate so any additions to the old serial.c that occur before
39607ca46eSDavid Howells  * we are merged can be easily merged here.
40607ca46eSDavid Howells  */
41607ca46eSDavid Howells #define PORT_PXA	31
42607ca46eSDavid Howells #define PORT_AMBA	32
43607ca46eSDavid Howells #define PORT_CLPS711X	33
44607ca46eSDavid Howells #define PORT_SA1100	34
45607ca46eSDavid Howells #define PORT_UART00	35
46fc60a8b6SAndreas Färber #define PORT_OWL	36
47607ca46eSDavid Howells #define PORT_21285	37
48607ca46eSDavid Howells 
49607ca46eSDavid Howells /* Sparc type numbers.  */
50607ca46eSDavid Howells #define PORT_SUNZILOG	38
51607ca46eSDavid Howells #define PORT_SUNSAB	39
52607ca46eSDavid Howells 
53f597fbceSJoel Stanley /* Nuvoton UART */
54f597fbceSJoel Stanley #define PORT_NPCM	40
55f597fbceSJoel Stanley 
562d908b38SThierry Reding /* NVIDIA Tegra Combined UART */
572d908b38SThierry Reding #define PORT_TEGRA_TCU	41
582d908b38SThierry Reding 
59a603ca60SZev Weiss /* ASPEED AST2x00 virtual UART */
60a603ca60SZev Weiss #define PORT_ASPEED_VUART	42
61a603ca60SZev Weiss 
6263e8d439SAndy Shevchenko /* Intel EG20 */
6363e8d439SAndy Shevchenko #define PORT_PCH_8LINE	44
6463e8d439SAndy Shevchenko #define PORT_PCH_2LINE	45
6563e8d439SAndy Shevchenko 
66607ca46eSDavid Howells /* DEC */
67607ca46eSDavid Howells #define PORT_DZ		46
68607ca46eSDavid Howells #define PORT_ZS		47
69607ca46eSDavid Howells 
70607ca46eSDavid Howells /* Parisc type numbers. */
71607ca46eSDavid Howells #define PORT_MUX	48
72607ca46eSDavid Howells 
7372ce5732SAndy Shevchenko /* Atmel AT91 SoC */
74607ca46eSDavid Howells #define PORT_ATMEL	49
75607ca46eSDavid Howells 
76607ca46eSDavid Howells /* Macintosh Zilog type numbers */
77607ca46eSDavid Howells #define PORT_MAC_ZILOG	50	/* m68k : not yet implemented */
78607ca46eSDavid Howells #define PORT_PMAC_ZILOG	51
79607ca46eSDavid Howells 
80607ca46eSDavid Howells /* SH-SCI */
81607ca46eSDavid Howells #define PORT_SCI	52
82607ca46eSDavid Howells #define PORT_SCIF	53
83607ca46eSDavid Howells #define PORT_IRDA	54
84607ca46eSDavid Howells 
85607ca46eSDavid Howells /* SGI IP22 aka Indy / Challenge S / Indigo 2 */
86607ca46eSDavid Howells #define PORT_IP22ZILOG	56
87607ca46eSDavid Howells 
88607ca46eSDavid Howells /* PPC CPM type number */
89607ca46eSDavid Howells #define PORT_CPM        58
90607ca46eSDavid Howells 
91607ca46eSDavid Howells /* MPC52xx (and MPC512x) type numbers */
92607ca46eSDavid Howells #define PORT_MPC52xx	59
93607ca46eSDavid Howells 
94607ca46eSDavid Howells /* IBM icom */
95607ca46eSDavid Howells #define PORT_ICOM	60
96607ca46eSDavid Howells 
97607ca46eSDavid Howells /* Motorola i.MX SoC */
98607ca46eSDavid Howells #define PORT_IMX	62
99607ca46eSDavid Howells 
100607ca46eSDavid Howells /* TXX9 type number */
101607ca46eSDavid Howells #define PORT_TXX9	64
102607ca46eSDavid Howells 
103607ca46eSDavid Howells /*Digi jsm */
104607ca46eSDavid Howells #define PORT_JSM        69
105607ca46eSDavid Howells 
106607ca46eSDavid Howells /* SUN4V Hypervisor Console */
107607ca46eSDavid Howells #define PORT_SUNHV	72
108607ca46eSDavid Howells 
109607ca46eSDavid Howells /* Xilinx uartlite */
110607ca46eSDavid Howells #define PORT_UARTLITE	74
111607ca46eSDavid Howells 
11242a569cdSJustin Chen /* Broadcom BCM7271 UART */
11342a569cdSJustin Chen #define PORT_BCM7271	76
11442a569cdSJustin Chen 
115607ca46eSDavid Howells /* Broadcom SB1250, etc. SOC */
116607ca46eSDavid Howells #define PORT_SB1250_DUART	77
117607ca46eSDavid Howells 
118607ca46eSDavid Howells /* Freescale ColdFire */
119607ca46eSDavid Howells #define PORT_MCF	78
120607ca46eSDavid Howells 
121607ca46eSDavid Howells #define PORT_SC26XX	82
122607ca46eSDavid Howells 
123607ca46eSDavid Howells /* SH-SCI */
124607ca46eSDavid Howells #define PORT_SCIFA	83
125607ca46eSDavid Howells 
126607ca46eSDavid Howells #define PORT_S3C6400	84
127607ca46eSDavid Howells 
128607ca46eSDavid Howells /* MAX3100 */
129607ca46eSDavid Howells #define PORT_MAX3100    86
130607ca46eSDavid Howells 
131607ca46eSDavid Howells /* Timberdale UART */
132607ca46eSDavid Howells #define PORT_TIMBUART	87
133607ca46eSDavid Howells 
134607ca46eSDavid Howells /* Qualcomm MSM SoCs */
135607ca46eSDavid Howells #define PORT_MSM	88
136607ca46eSDavid Howells 
137607ca46eSDavid Howells /* BCM63xx family SoCs */
138607ca46eSDavid Howells #define PORT_BCM63XX	89
139607ca46eSDavid Howells 
140607ca46eSDavid Howells /* Aeroflex Gaisler GRLIB APBUART */
141607ca46eSDavid Howells #define PORT_APBUART    90
142607ca46eSDavid Howells 
143607ca46eSDavid Howells /* Altera UARTs */
144607ca46eSDavid Howells #define PORT_ALTERA_JTAGUART	91
145607ca46eSDavid Howells #define PORT_ALTERA_UART	92
146607ca46eSDavid Howells 
147607ca46eSDavid Howells /* SH-SCI */
148607ca46eSDavid Howells #define PORT_SCIFB	93
149607ca46eSDavid Howells 
150607ca46eSDavid Howells /* MAX310X */
151607ca46eSDavid Howells #define PORT_MAX310X	94
152607ca46eSDavid Howells 
153ee1c90ccSAndy Shevchenko /* TI DA8xx/66AK2x */
154ee1c90ccSAndy Shevchenko #define PORT_DA830	95
155ee1c90ccSAndy Shevchenko 
156607ca46eSDavid Howells /* TI OMAP-UART */
157607ca46eSDavid Howells #define PORT_OMAP	96
158607ca46eSDavid Howells 
159607ca46eSDavid Howells /* VIA VT8500 SoC */
160607ca46eSDavid Howells #define PORT_VT8500	97
161607ca46eSDavid Howells 
162d9bb3fb1SSoren Brinkmann /* Cadence (Xilinx Zynq) UART */
163607ca46eSDavid Howells #define PORT_XUARTPS	98
164607ca46eSDavid Howells 
165607ca46eSDavid Howells /* Atheros AR933X SoC */
166607ca46eSDavid Howells #define PORT_AR933X	99
167607ca46eSDavid Howells 
16832bb477fSKumaravel Thiagarajan /* MCHP 16550A UART with 256 byte FIFOs */
16932bb477fSKumaravel Thiagarajan #define PORT_MCHP16550A	100
17032bb477fSKumaravel Thiagarajan 
1712ac4ad2aSVineet Gupta /* ARC (Synopsys) on-chip UART */
1722ac4ad2aSVineet Gupta #define PORT_ARC       101
173607ca46eSDavid Howells 
1747d9f49afSKevin Cernekee /* Rocketport EXPRESS/INFINITY */
1757d9f49afSKevin Cernekee #define PORT_RP2	102
1767d9f49afSKevin Cernekee 
177c9e2e946SJingchang Lu /* Freescale lpuart */
178c9e2e946SJingchang Lu #define PORT_LPUART	103
179c9e2e946SJingchang Lu 
180f303b364SUlrich Hecht /* SH-SCI */
18142daabf6SLinus Torvalds #define PORT_HSCIF	104
182f303b364SUlrich Hecht 
183c4b05856SSrinivas Kandagatla /* ST ASC type numbers */
184c4b05856SSrinivas Kandagatla #define PORT_ASC       105
185c4b05856SSrinivas Kandagatla 
186e264ebf4SJohannes Thumshirn /* MEN 16z135 UART */
187e264ebf4SJohannes Thumshirn #define PORT_MEN_Z135	107
188e264ebf4SJohannes Thumshirn 
18954b45ee8SAndy Shevchenko /* SC16IS7xx */
190dfeae619SJon Ringle #define PORT_SC16IS7XX   108
191dfeae619SJon Ringle 
192ff7693d0SCarlo Caione /* MESON */
193ff7693d0SCarlo Caione #define PORT_MESON	109
194ff7693d0SCarlo Caione 
1955930cb35SBaruch Siach /* Conexant Digicolor */
1965930cb35SBaruch Siach #define PORT_DIGICOLOR	110
1975930cb35SBaruch Siach 
198b7396a38SChunyan Zhang /* SPRD SERIAL  */
199b7396a38SChunyan Zhang #define PORT_SPRD	111
200b7396a38SChunyan Zhang 
20148a6092fSMaxime Coquelin /* STM32 USART */
20248a6092fSMaxime Coquelin #define PORT_STM32	113
20348a6092fSMaxime Coquelin 
20430530791SWilson Ding /* MVEBU UART */
20530530791SWilson Ding #define PORT_MVEBU	114
20630530791SWilson Ding 
207157b9394SAndrei Pistirica /* Microchip PIC32 UART */
20807b75260SLinus Torvalds #define PORT_PIC32	115
209157b9394SAndrei Pistirica 
210041f031dSVladimir Murzin /* MPS2 UART */
211e10abc62SLinus Torvalds #define PORT_MPS2UART	116
212041f031dSVladimir Murzin 
2131c16ae65SSean Wang /* MediaTek BTIF */
2141c16ae65SSean Wang #define PORT_MTK_BTIF	117
2151c16ae65SSean Wang 
216c10b1332SManivannan Sadhasivam /* RDA UART */
217c10b1332SManivannan Sadhasivam #define PORT_RDA	118
218c10b1332SManivannan Sadhasivam 
219ba44dc04SSugaya Taichi /* Socionext Milbeaut UART */
220ba44dc04SSugaya Taichi #define PORT_MLB_USIO	119
221ba44dc04SSugaya Taichi 
22245c054d0SPaul Walmsley /* SiFive UART */
22345c054d0SPaul Walmsley #define PORT_SIFIVE_V0	120
22445c054d0SPaul Walmsley 
2258515dbc1SKai-Heng Feng /* Sunix UART */
2268515dbc1SKai-Heng Feng #define PORT_SUNIX	121
2278515dbc1SKai-Heng Feng 
2289905f32aSStefan-Gabriel Mirea /* Freescale LINFlexD UART */
22947934ef7SStefan-gabriel Mirea #define PORT_LINFLEXUART	122
23009864c1cSStefan-gabriel Mirea 
2319e8d5470SHammer Hsieh /* Sunplus UART */
2329e8d5470SHammer Hsieh #define PORT_SUNPLUS	123
2339e8d5470SHammer Hsieh 
234*c7c5be58SMax Filippov /* Generic type identifier for ports which type is not important to userspace. */
235*c7c5be58SMax Filippov #define PORT_GENERIC	(-1)
236*c7c5be58SMax Filippov 
237607ca46eSDavid Howells #endif /* _UAPILINUX_SERIAL_CORE_H */
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