1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Zynq pin controller
18 #include <linux/pinctrl/pinconf-generic.h>
20 #include "pinctrl-utils.h"
28 #define ZYNQ_PINMUX_MUX_SHIFT	1
32  * struct zynq_pinctrl - driver data
58  * struct zynq_pinmux_function - a pinmux function
119 	PINCTRL_PIN(1,  "MIO1"),
185 static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6};
234 static const unsigned int smc0_nor_cs1_pins[] = {1};
235 static const unsigned int smc0_nor_addr25_pins[] = {1};
241 /* Note: CAN MIO clock inputs are modeled in the clock framework */
322 static const unsigned int gpio0_1_pins[] = {1};
781 	DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet0, 1),
782 	DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet1, 1),
787 	DEFINE_ZYNQ_PINMUX_FUNCTION(qspi0, 1),
788 	DEFINE_ZYNQ_PINMUX_FUNCTION(qspi1, 1),
789 	DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_fbclk, 1),
790 	DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1),
829 	return pctrl->ngroups;  in zynq_pctrl_get_groups_count()
837 	return pctrl->groups[selector].name;  in zynq_pctrl_get_group_name()
847 	*pins = pctrl->groups[selector].pins;  in zynq_pctrl_get_group_pins()
848 	*num_pins = pctrl->groups[selector].npins;  in zynq_pctrl_get_group_pins()
866 	return pctrl->nfuncs;  in zynq_pmux_get_functions_count()
874 	return pctrl->funcs[selector].name;  in zynq_pmux_get_function_name()
884 	*groups = pctrl->funcs[selector].groups;  in zynq_pmux_get_function_groups()
885 	*num_groups = pctrl->funcs[selector].ngroups;  in zynq_pmux_get_function_groups()
895 	const struct zynq_pctrl_group *pgrp = &pctrl->groups[group];  in zynq_pinmux_set_mux()
896 	const struct zynq_pinmux_function *func = &pctrl->funcs[function];  in zynq_pinmux_set_mux()
907 		ret = regmap_read(pctrl->syscon,  in zynq_pinmux_set_mux()
908 				  pctrl->pctrl_offset + func->mux, &reg);  in zynq_pinmux_set_mux()
912 		reg &= ~func->mux_mask;  in zynq_pinmux_set_mux()
913 		reg |= pgrp->pins[0] << func->mux_shift;  in zynq_pinmux_set_mux()
914 		ret = regmap_write(pctrl->syscon,  in zynq_pinmux_set_mux()
915 				   pctrl->pctrl_offset + func->mux, reg);  in zynq_pinmux_set_mux()
919 		for (i = 0; i < pgrp->npins; i++) {  in zynq_pinmux_set_mux()
920 			unsigned int pin = pgrp->pins[i];  in zynq_pinmux_set_mux()
921 			u32 reg, addr = pctrl->pctrl_offset + (4 * pin);  in zynq_pinmux_set_mux()
923 			ret = regmap_read(pctrl->syscon, addr, &reg);  in zynq_pinmux_set_mux()
928 			reg |= func->mux_val << ZYNQ_PINMUX_MUX_SHIFT;  in zynq_pinmux_set_mux()
929 			ret = regmap_write(pctrl->syscon, addr, reg);  in zynq_pinmux_set_mux()
964  * PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to
968 #define PIN_CONFIG_IOSTANDARD		(PIN_CONFIG_END + 1)
971 	{"io-standard", PIN_CONFIG_IOSTANDARD, zynq_iostd_lvcmos18},
976 	= { PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true),
996 		return -ENOTSUPP;  in zynq_pinconf_cfg_get()
998 	ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), &reg);  in zynq_pinconf_cfg_get()
1000 		return -EIO;  in zynq_pinconf_cfg_get()
1005 			return -EINVAL;  in zynq_pinconf_cfg_get()
1006 		arg = 1;  in zynq_pinconf_cfg_get()
1010 			return -EINVAL;  in zynq_pinconf_cfg_get()
1011 		arg = 1;  in zynq_pinconf_cfg_get()
1015 			return -EINVAL;  in zynq_pinconf_cfg_get()
1025 			return -EINVAL;  in zynq_pinconf_cfg_get()
1027 			return -EINVAL;  in zynq_pinconf_cfg_get()
1036 		return -ENOTSUPP;  in zynq_pinconf_cfg_get()
1055 		return -ENOTSUPP;  in zynq_pinconf_cfg_set()
1057 	ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), &reg);  in zynq_pinconf_cfg_set()
1059 		return -EIO;  in zynq_pinconf_cfg_set()
1085 				dev_warn(pctldev->dev,  in zynq_pinconf_cfg_set()
1101 			dev_warn(pctldev->dev,  in zynq_pinconf_cfg_set()
1113 	ret = regmap_write(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), reg);  in zynq_pinconf_cfg_set()
1115 		return -EIO;  in zynq_pinconf_cfg_set()
1127 	const struct zynq_pctrl_group *pgrp = &pctrl->groups[selector];  in zynq_pinconf_group_set()
1129 	for (i = 0; i < pgrp->npins; i++) {  in zynq_pinconf_group_set()
1130 		ret = zynq_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,  in zynq_pinconf_group_set()
1167 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);  in zynq_pinctrl_probe()
1169 		return -ENOMEM;  in zynq_pinctrl_probe()
1171 	pctrl->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,  in zynq_pinctrl_probe()
1173 	if (IS_ERR(pctrl->syscon)) {  in zynq_pinctrl_probe()
1174 		dev_err(&pdev->dev, "unable to get syscon\n");  in zynq_pinctrl_probe()
1175 		return PTR_ERR(pctrl->syscon);  in zynq_pinctrl_probe()
1180 		dev_err(&pdev->dev, "missing IO resource\n");  in zynq_pinctrl_probe()
1181 		return -ENODEV;  in zynq_pinctrl_probe()
1183 	pctrl->pctrl_offset = res->start;  in zynq_pinctrl_probe()
1185 	pctrl->groups = zynq_pctrl_groups;  in zynq_pinctrl_probe()
1186 	pctrl->ngroups = ARRAY_SIZE(zynq_pctrl_groups);  in zynq_pinctrl_probe()
1187 	pctrl->funcs = zynq_pmux_functions;  in zynq_pinctrl_probe()
1188 	pctrl->nfuncs = ARRAY_SIZE(zynq_pmux_functions);  in zynq_pinctrl_probe()
1190 	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &zynq_desc, pctrl);  in zynq_pinctrl_probe()
1191 	if (IS_ERR(pctrl->pctrl))  in zynq_pinctrl_probe()
1192 		return PTR_ERR(pctrl->pctrl);  in zynq_pinctrl_probe()
1196 	dev_info(&pdev->dev, "zynq pinctrl initialized\n");  in zynq_pinctrl_probe()
1202 	{ .compatible = "xlnx,pinctrl-zynq" },
1209 		.name = "zynq-pinctrl",