11da9d6e3SPavel Pisa# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 21da9d6e3SPavel Pisa%YAML 1.2 31da9d6e3SPavel Pisa--- 41da9d6e3SPavel Pisa$id: http://devicetree.org/schemas/net/can/ctu,ctucanfd.yaml# 51da9d6e3SPavel Pisa$schema: http://devicetree.org/meta-schemas/core.yaml# 61da9d6e3SPavel Pisa 7*a612130cSKrzysztof Kozlowskititle: CTU CAN FD Open-source IP Core 81da9d6e3SPavel Pisa 91da9d6e3SPavel Pisadescription: | 101da9d6e3SPavel Pisa Open-source CAN FD IP core developed at the Czech Technical University in Prague 111da9d6e3SPavel Pisa 121da9d6e3SPavel Pisa The core sources and documentation on project page 131da9d6e3SPavel Pisa [1] sources : https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core 141da9d6e3SPavel Pisa [2] datasheet : https://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/Datasheet.pdf 151da9d6e3SPavel Pisa 161da9d6e3SPavel Pisa Integration in Xilinx Zynq SoC based system together with 171da9d6e3SPavel Pisa OpenCores SJA1000 compatible controllers 181da9d6e3SPavel Pisa [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top 191da9d6e3SPavel Pisa Martin Jerabek dimploma thesis with integration and testing 201da9d6e3SPavel Pisa framework description 211da9d6e3SPavel Pisa [4] PDF : https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-canfd.pdf 221da9d6e3SPavel Pisa 231da9d6e3SPavel Pisamaintainers: 241da9d6e3SPavel Pisa - Pavel Pisa <pisa@cmp.felk.cvut.cz> 251da9d6e3SPavel Pisa - Ondrej Ille <ondrej.ille@gmail.com> 261da9d6e3SPavel Pisa - Martin Jerabek <martin.jerabek01@gmail.com> 271da9d6e3SPavel Pisa 2814e1e933SMarc Kleine-BuddeallOf: 2914e1e933SMarc Kleine-Budde - $ref: can-controller.yaml# 3014e1e933SMarc Kleine-Budde 311da9d6e3SPavel Pisaproperties: 321da9d6e3SPavel Pisa compatible: 331da9d6e3SPavel Pisa oneOf: 341da9d6e3SPavel Pisa - items: 351da9d6e3SPavel Pisa - const: ctu,ctucanfd-2 361da9d6e3SPavel Pisa - const: ctu,ctucanfd 371da9d6e3SPavel Pisa - const: ctu,ctucanfd 381da9d6e3SPavel Pisa 391da9d6e3SPavel Pisa reg: 401da9d6e3SPavel Pisa maxItems: 1 411da9d6e3SPavel Pisa 421da9d6e3SPavel Pisa interrupts: 431da9d6e3SPavel Pisa maxItems: 1 441da9d6e3SPavel Pisa 451da9d6e3SPavel Pisa clocks: 461da9d6e3SPavel Pisa description: | 471da9d6e3SPavel Pisa phandle of reference clock (100 MHz is appropriate 481da9d6e3SPavel Pisa for FPGA implementation on Zynq-7000 system). 491da9d6e3SPavel Pisa maxItems: 1 501da9d6e3SPavel Pisa 511da9d6e3SPavel Pisarequired: 521da9d6e3SPavel Pisa - compatible 531da9d6e3SPavel Pisa - reg 541da9d6e3SPavel Pisa - interrupts 551da9d6e3SPavel Pisa - clocks 561da9d6e3SPavel Pisa 571da9d6e3SPavel PisaadditionalProperties: false 581da9d6e3SPavel Pisa 591da9d6e3SPavel Pisaexamples: 601da9d6e3SPavel Pisa - | 611da9d6e3SPavel Pisa ctu_can_fd_0: can@43c30000 { 621da9d6e3SPavel Pisa compatible = "ctu,ctucanfd"; 631da9d6e3SPavel Pisa interrupts = <0 30 4>; 641da9d6e3SPavel Pisa clocks = <&clkc 15>; 651da9d6e3SPavel Pisa reg = <0x43c30000 0x10000>; 661da9d6e3SPavel Pisa }; 67