| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | qcom,mmcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniy
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| H A D | silabs,si5351.txt | 5 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
20 - reg: i2c device address, shall be 0x60 or 0x61.
21 - #clock-cells: from common clock binding; shall be set to 1.
22 - clocks: from common clock binding; list of parent clock
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| H A D | brcm,iproc-clocks.txt | 4 Documentation/devicetree/bindings/clock/clock-bindings.txt
8 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
11 Required properties for a PLL and its leaf clocks:
13 - compatible:
14 Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
15 Cygnus has a compatible string of "brcm,cygnus-genpll"
17 - #clock-cells:
18 Have a value of <1> since there are more than 1 leaf clock of a given PLL
20 - reg:
22 clock control registers required for the PLL
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| H A D | brcm,iproc-clocks.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <rjui@broadcom.com>
11 - Scott Branden <sbranden@broadcom.com>
16 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
25 - brcm,bcm63138-armpll
26 - brcm,cygnus-armpll
27 - brcm,cygnus-genpll
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| H A D | brcm,bcm2835-cprman.txt | 4 Documentation/devicetree/bindings/clock/clock-bindings.txt
8 oscillator, a level of PLL dividers that produce channels off of the
9 few PLLs, and a level of mostly-generic clock generators sourcing from
10 the PLL channels. Most other hardware components source from the
11 clock generators, but a few (like the ARM or HDMI) will source from
12 the PLL dividers directly.
15 - compatible: should be one of the following,
16 "brcm,bcm2711-cprman"
17 "brcm,bcm2835-cprman"
18 - #clock-cells: Should be <1>. The permitted clock-specifier values can be
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| H A D | cirrus,cs2000-cp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
13 The CS2000-CP is an extremely versatile system clocking device that
21 - cirrus,cs2000-cp
28 clock-names:
30 - const: clk_in
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | nvidia,tegra124-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
20 - description: NVIDIA Tegra124
21 const: nvidia,tegra124-xusb
23 - description: NVIDIA Tegra132
25 - const: nvidia,tegra132-xusb
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| H A D | nvidia,tegra210-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 const: nvidia,tegra210-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
24 - description: base and length of the XUSB IPFS registers
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| H A D | nvidia,tegra194-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 const: nvidia,tegra194-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
25 reg-names:
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| H A D | nvidia,tegra186-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra186-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 const: nvidia,tegra186-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
25 reg-names:
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| /freebsd/sys/arm/nvidia/tegra124/ |
| H A D | tegra124_clk_pll.c | 1 /*-
5 * Redistribution and use in source and binary forms, with or without
8 * 1. Redistributions of source code must retain the above copyright
38 #include <dt-bindings/clock/tegra124-car.h>
88 /* Post divider <-> register value mapping. */
116 #define PLL(_id, cname, pname) \ macro
124 PLLM: Clock source for EMC 2x clock
125 PLLX: Clock source for the fast CPU cluster and the shadow CPU
126 PLLC: Clock source for general use
127 PLLC2: Clock source for engine scaling
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| /freebsd/contrib/bc/tests/ |
| H A D | all.sh | 3 # SPDX-License-Identifier: BSD-2-Clause
5 # Copyright (c) 2018-2024 Gavin D. Howard and contributors.
7 # Redistribution and use in source and binary forms, with or without
10 # * Redistributions of source code must retain the above copyright notice, this
39 if [ $# -eq 1 ]; then
42 print 'usage: %s [-n] dir [run_extra_tests] [run_stack_tests] [gen_tests] [run_problematic_tests] [time_tests] [exec args...]\n' \
48 pll
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| H A D | scripts.sh | 3 # SPDX-License-Identifier: BSD-2-Clause
5 # Copyright (c) 2018-2024 Gavin D. Howard and contributors.
7 # Redistribution and use in source and binary forms, with or without
10 # * Redistributions of source code must retain the above copyright notice, this
40 if [ $# -eq 1 ]; then
43 printf 'usage: %s [-n] dir [run_extra_tests] [run_stack_tests] [generate_tests] [time_tests] [exec args...]\n' "$script"
50 pll
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| /freebsd/sys/arm64/nvidia/tegra210/ |
| H A D | tegra210_clk_pll.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Redistribution and use in source and binary forms, with or without
9 * 1. Redistributions of source code must retain the above copyright
42 #include <dt-bindings/clock/tegra210-car.h>
113 /* Post divider <-> register value mapping. */
144 #define PLL(_id, cname, pname) \ macro
151 /* multiplexer for pll sources. */
164 /* Fractional divider (7.1) for PLL branch. */
179 /* P divider (2^n). for PLL branch. */
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| /freebsd/sys/dev/firmware/xilinx/ |
| H A D | pm_defs.h | 2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
117 /* PLL control API functions */
325 * @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL
326 * @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL
327 * @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL
328 * @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input
329 * @PM_PLL_PARAM_POST_SRC: Clock source for PLL Bypass mode
332 * @PM_PLL_PARAM_LFHF: PLL loop filter high frequency capacitor control
333 * @PM_PLL_PARAM_CP: PLL charge pump control
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| /freebsd/sys/arm64/qoriq/clk/ |
| H A D | lx2160a_clkgen.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Redistribution and use in source and binary forms, with or without
9 * 1. Redistributions of source code must retain the above copyright
49 #define PLL(_id1, _id2, cname, o, d) \ macro
67 PLL(QORIQ_TYPE_PLATFORM_PLL, 0, "platform_pll", 0x60080, plt_divs);
69 PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll1", 0x80, cga_divs);
71 PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll2", 0xA0, cga_divs);
73 PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll1", 0x10080, cgb_divs);
75 PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll2", 0x100A0, cgb_divs);
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| /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | tegra186-clock.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
419 * appropriate clock source, program the source rate and execute a
420 * specific sequence to switch to the new clock source for both memory
751 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
809 …DQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
813 /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enab…
818 * @brief GPC2CLK-div-2
827 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
829 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
831 /** Fixed 408MHz PLL for use by peripheral clocks */
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| H A D | tegra234-clock.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
66 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
75 * appropriate clock source, program the source rate and execute a
76 * specific sequence to switch to the new clock source for both memory
196 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
198 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain …
200 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
206 /** Fixed frequency 960MHz PLL for USB and EAVB */
382 /** @brief NAFLL clock source for BPMP */
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| /freebsd/sys/arm/xilinx/ |
| H A D | zy7_slcr.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
7 * Redistribution and use in source and binary forms, with or without
10 * 1. Redistributions of source code must retain the above copyright
30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff.
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
66 #define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
67 #define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
69 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
71 #define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
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| /freebsd/sys/dev/bhnd/cores/chipc/pwrctl/ |
| H A D | bhnd_pwrctl_subr.c | 1 /*-
6 * This file is derived from the siutils.c source distributed with the
7 * Asus RT-N16 firmware source code release.
21 * $Id: siutils.c,v 1.821.2.48 2011-02-11 20:59:28 Exp $
73 * Return the backplane clock's chipc 'M' register offset for a given PLL type,
77 * @param pll_type PLL type (CHIPC_PLL_TYPE*)
100 * @param pll_type PLL type (CHIPC_PLL_TYPE*)
121 * Return the CPU clock's chipc 'M' register offset for a given PLL type,
125 * @param pll_type PLL type (CHIPC_PLL_TYPE*)
147 if (cid->chip_id == BHND_CHIPID_BCM5365) { in bhnd_pwrctl_cpu_clkreg_m()
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| /freebsd/sys/dev/clk/allwinner/ |
| H A D | ccu_a13.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Redistribution and use in source and binary forms, with or without
9 * 1. Redistributions of source code must retain the above copyright
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/reset/sun5i-ccu.h>
50 /* Non-exported clocks */
101 CCU_GATE(CLK_DRAM_AXI, "axi-dram", "axi", 0x5c, 0)
103 CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0)
104 CCU_GATE(CLK_AHB_EHCI, "ahb-ehci", "ahb", 0x60, 1)
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xus
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| H A D | qcom,qmp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Vinod Koul <vkoul@kernel.org>
20 - qcom,ipq6018-qmp-pcie-phy
21 - qcom,ipq6018-qmp-usb3-phy
22 - qcom,ipq8074-qmp-gen3-pcie-phy
23 - qcom,ipq8074-qmp-pcie-phy
24 - qcom,ipq8074-qmp-usb3-phy
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| /freebsd/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | dove-cubox.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
20 compatible = "gpio-leds";
21 pinctrl-0 = <&pmx_gpio_18>;
22 pinctrl-names = "default";
24 led-power {
27 default-state = "keep";
31 usb_power: regulator-
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| /freebsd/sys/riscv/sifive/ |
| H A D | sifive_prci.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
11 * Redistribution and use in source and binary forms, with or without
14 * 1. Redistributions of source code must retain the above copyright
85 #define PRCI_LOCK(sc) mtx_lock(&(sc)->mtx)
86 #define PRCI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
87 #define PRCI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
88 #define PRCI_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
101 bus_space_read_4((_sc)->bst, (_sc)->bsh, (_reg))
103 bus_space_write_4((_sc)->bst, (_sc)->bsh, (_reg), (_val))
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