Lines Matching +full:pll +full:- +full:source

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
66 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
75  * appropriate clock source, program the source rate and execute a
76  * specific sequence to switch to the new clock source for both memory
196 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
198 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain …
200 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
206 /** Fixed frequency 960MHz PLL for USB and EAVB */
382 /** @brief NAFLL clock source for BPMP */
384 /** @brief NAFLL clock source for SCE */
386 /** @brief NAFLL clock source for NVDEC */
388 /** @brief NAFLL clock source for NVJPG */
390 /** @brief NAFLL clock source for TSEC */
392 /** @brief NAFLL clock source for VI */
394 /** @brief NAFLL clock source for SE */
396 /** @brief NAFLL clock source for NVENC */
398 /** @brief NAFLL clock source for ISP */
400 /** @brief NAFLL clock source for VIC */
402 /** @brief NAFLL clock source for AXICBB */
404 /** @brief NAFLL clock source for NVJPG1 */
406 /** @brief NAFLL clock source for PVA core */
408 /** @brief NAFLL clock source for PVA VPS */
412 /** @brief NAFLL clock source for RCE */
450 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
460 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVHS_BASE */
518 /** @brief NAFLL clock source for CPU cluster 0 */
521 /** @brief NAFLL clock source for CPU cluster 1 */
524 /** @brief NAFLL clock source for CPU cluster 2 */
533 /** @brief NVHS PLL hardware power sequencer (overrides 'manual' programming of PLL) */
535 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE */
543 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE  */
571 /** @brief output of mem pll A sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMC */
573 /** @brief output of mem pll B sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB */
575 /** @brief output of mem pll C sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC */
577 /** @brief output of mem pll D sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD */
579 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
581 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
587 /** @brief GBE PLL */
589 /** @brief GBE PLL hardware power sequencer */
599 /** @brief PLLE hardware power sequencer (overrides 'manual' programming of PLL) */
603 /** @brief TEGRA234_CLK_SOR_SAFE clk source (PLLP_OUT0 divided by 17) */
611 /** @brief NAFLL clock source for OFA */
615 /** @brief NAFLL clock source for SEU1 */
627 /** @brief NAFLL clock source for DCE */
795 /** @brief NAFLL clock source for GPU GPC0 */
797 /** @brief NAFLL clock source for GPU GPC1 */
799 /** @brief NAFLL clock source for GPU SYSCLK */
801 /** @brief NAFLL clock source for CPU cluster 0 DSUCLK */
804 /** @brief NAFLL clock source for CPU cluster 1 DSUCLK */
807 /** @brief NAFLL clock source for CPU cluster 2 DSUCLK */
874 /** @brief Link clock input from DP macro brick PLL */