Lines Matching +full:pll +full:- +full:source
1 /*-
5 * Redistribution and use in source and binary forms, with or without
8 * 1. Redistributions of source code must retain the above copyright
38 #include <dt-bindings/clock/tegra124-car.h>
88 /* Post divider <-> register value mapping. */
116 #define PLL(_id, cname, pname) \ macro
124 PLLM: Clock source for EMC 2x clock
125 PLLX: Clock source for the fast CPU cluster and the shadow CPU
126 PLLC: Clock source for general use
127 PLLC2: Clock source for engine scaling
128 PLLC3: Clock source for engine scaling
129 PLLC4: Clock source for ISP/VI units
130 PLLP: Clock source for most peripherals
132 PLLU: Clock source for USB PHY, provides 12/60/480 MHz
137 PLLDP: Clock source for eDP/LVDS (spread spectrum)
139 DFLLCPU: DFLL clock source for the fast CPU cluster
140 GPCPLL: Clock source for the GPU
216 /* PLLM: 880 MHz Clock source for EMC 2x clock */
218 PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"),
227 /* PLLX: 1GHz Clock source for the fast CPU cluster and the shadow CPU */
229 PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"),
240 /* PLLC: 600 MHz Clock source for general use */
242 PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
253 /* PLLC2: 600 MHz Clock source for engine scaling */
255 PLL(TEGRA124_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),
264 /* PLLC3: 600 MHz Clock source for engine scaling */
266 PLL(TEGRA124_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),
275 /* PLLC4: 600 MHz Clock source for ISP/VI units */
277 PLL(TEGRA124_CLK_PLL_C4, "pllC4_out0", "pllC4_src"),
288 /* PLLP: 408 MHz Clock source for most peripherals */
290 PLL(TEGRA124_CLK_PLL_P, "pllP_out0", "osc_div_clk"),
300 PLL(TEGRA124_CLK_PLL_A, "pllA_out", "pllP_out1"),
308 /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */
310 PLL(TEGRA124_CLK_PLL_U, "pllU_out", "osc_div_clk"),
321 PLL(TEGRA124_CLK_PLL_D, "pllD_out", "osc_div_clk"),
331 PLL(TEGRA124_CLK_PLL_D2, "pllD2_out", "pllD2_src"),
344 PLL(0, "pllREFE_out", "osc_div_clk"),
357 PLL(TEGRA124_CLK_PLL_E, "pllE_out0", "pllE_src"),
365 /* PLLDP: 600 MHz Clock source for eDP/LVDS (spread spectrum) */
367 PLL(0, "pllDP_out0", "pllDP_src"),
417 RD4(sc, sc->base_reg, ®); in pll_enable()
418 if (sc->type != PLL_E) in pll_enable()
421 WR4(sc, sc->base_reg, reg); in pll_enable()
430 RD4(sc, sc->base_reg, ®); in pll_disable()
431 if (sc->type != PLL_E) in pll_disable()
434 WR4(sc, sc->base_reg, reg); in pll_disable()
443 tbl = sc->pdiv_table; in pdiv_to_reg()
445 return (ffs(p_div) - 1); in pdiv_to_reg()
447 while (tbl->divider != 0) { in pdiv_to_reg()
448 if (p_div <= tbl->divider) in pdiv_to_reg()
449 return (tbl->value); in pdiv_to_reg()
460 tbl = sc->pdiv_table; in reg_to_pdiv()
464 while (tbl->divider) { in reg_to_pdiv()
465 if (reg == tbl->value) in reg_to_pdiv()
466 return (tbl->divider); in reg_to_pdiv()
476 return ((val >> shift) & ((1 << width) - 1)); in get_masked()
483 val &= ~(((1 << width) - 1) << shift); in set_masked()
484 val |= (v & ((1 << width) - 1)) << shift; in set_masked()
494 mnp_bits = &sc->mnp_bits; in get_divisors()
495 RD4(sc, sc->base_reg, &val); in get_divisors()
496 *m = get_masked(val, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in get_divisors()
497 *n = get_masked(val, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in get_divisors()
498 *p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width); in get_divisors()
507 mnp_bits = &sc->mnp_bits; in set_divisors()
508 val = set_masked(val, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in set_divisors()
509 val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in set_divisors()
510 val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width); in set_divisors()
519 switch (sc->type) { in is_locked()
521 RD4(sc, sc->misc_reg, ®); in is_locked()
526 RD4(sc, sc->misc_reg, ®); in is_locked()
531 RD4(sc, sc->base_reg, ®); in is_locked()
543 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) { in wait_for_lock()
549 printf("PLL lock timeout\n"); in wait_for_lock()
566 RD4(sc, sc->base_reg, ®); in plle_enable()
568 WR4(sc, sc->base_reg, reg); in plle_enable()
576 RD4(sc, sc->misc_reg, ®); in plle_enable()
583 WR4(sc, sc->misc_reg, reg); in plle_enable()
590 RD4(sc, sc->base_reg, ®); in plle_enable()
594 WR4(sc, sc->base_reg, reg); in plle_enable()
617 /* HW control of brick pll. */ in plle_enable()
618 RD4(sc, sc->misc_reg, ®); in plle_enable()
620 WR4(sc, sc->misc_reg, reg); in plle_enable()
644 /* Enable HW control and unreset SATA PLL. */ in plle_enable()
660 /* Enable HW control of PCIe PLL. */ in plle_enable()
680 if (sc->type == PLL_E) in tegra124_pll_set_gate()
694 RD4(sc, sc->base_reg, ®); in tegra124_pll_get_gate()
696 WR4(sc, sc->base_reg, reg); in tegra124_pll_get_gate()
708 mnp_bits = &sc->mnp_bits; in pll_set_std()
709 if (m >= (1 << mnp_bits->m_width)) in pll_set_std()
711 if (n >= (1 << mnp_bits->n_width)) in pll_set_std()
713 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) in pll_set_std()
728 /* take pll out of IDDQ */ in pll_set_std()
729 if (sc->iddq_reg != 0) in pll_set_std()
730 MD4(sc, sc->iddq_reg, sc->iddq_mask, 0); in pll_set_std()
732 RD4(sc, sc->base_reg, ®); in pll_set_std()
733 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in pll_set_std()
734 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in pll_set_std()
735 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pll_set_std()
736 mnp_bits->p_width); in pll_set_std()
737 WR4(sc, sc->base_reg, reg); in pll_set_std()
739 /* Enable PLL. */ in pll_set_std()
740 RD4(sc, sc->base_reg, ®); in pll_set_std()
742 WR4(sc, sc->base_reg, reg); in pll_set_std()
745 RD4(sc, sc->misc_reg, ®); in pll_set_std()
746 reg |= sc->lock_enable; in pll_set_std()
747 WR4(sc, sc->misc_reg, reg); in pll_set_std()
751 /* Disable PLL */ in pll_set_std()
752 RD4(sc, sc->base_reg, ®); in pll_set_std()
754 WR4(sc, sc->base_reg, reg); in pll_set_std()
757 RD4(sc, sc->misc_reg, ®); in pll_set_std()
789 * PLLD2 is used as source for pixel clock for HDMI.
813 mnp_bits = &sc->mnp_bits; in plld2_set_freq()
814 tbl = sc->pdiv_table; in plld2_set_freq()
827 for (m = 1; m < (1 << mnp_bits->m_width); m++) { in plld2_set_freq()
833 if (n >= (1 << mnp_bits->n_width)) in plld2_set_freq()
843 err = *fout - vco / p; in plld2_set_freq()
845 err = -err; in plld2_set_freq()
891 mnp_bits = &sc->mnp_bits; in pllx_set_freq()
898 if (m >= (1 << mnp_bits->m_width)) in pllx_set_freq()
900 if (n >= (1 << mnp_bits->n_width)) in pllx_set_freq()
902 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) in pllx_set_freq()
914 RD4(sc, sc->base_reg, ®); in pllx_set_freq()
916 WR4(sc, sc->base_reg, reg); in pllx_set_freq()
918 /* Set PLL. */ in pllx_set_freq()
919 RD4(sc, sc->base_reg, ®); in pllx_set_freq()
920 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in pllx_set_freq()
921 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in pllx_set_freq()
922 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pllx_set_freq()
923 mnp_bits->p_width); in pllx_set_freq()
924 WR4(sc, sc->base_reg, reg); in pllx_set_freq()
925 RD4(sc, sc->base_reg, ®); in pllx_set_freq()
929 RD4(sc, sc->misc_reg, ®); in pllx_set_freq()
930 reg |= sc->lock_enable; in pllx_set_freq()
931 WR4(sc, sc->misc_reg, reg); in pllx_set_freq()
933 /* Enable PLL. */ in pllx_set_freq()
934 RD4(sc, sc->base_reg, ®); in pllx_set_freq()
936 WR4(sc, sc->base_reg, reg); in pllx_set_freq()
940 /* Disable PLL */ in pllx_set_freq()
941 RD4(sc, sc->base_reg, ®); in pllx_set_freq()
943 WR4(sc, sc->base_reg, reg); in pllx_set_freq()
946 RD4(sc, sc->misc_reg, ®); in pllx_set_freq()
963 switch (sc->type) { in tegra124_pll_set_freq()
1004 /* If PLL is enabled, enable lock detect too. */ in tegra124_pll_init()
1005 RD4(sc, sc->base_reg, ®); in tegra124_pll_init()
1007 RD4(sc, sc->misc_reg, ®); in tegra124_pll_init()
1008 reg |= sc->lock_enable; in tegra124_pll_init()
1009 WR4(sc, sc->misc_reg, reg); in tegra124_pll_init()
1011 if (sc->type == PLL_REFE) { in tegra124_pll_init()
1012 RD4(sc, sc->misc_reg, ®); in tegra124_pll_init()
1014 WR4(sc, sc->misc_reg, reg); in tegra124_pll_init()
1030 RD4(sc, sc->base_reg, ®); in tegra124_pll_recalc()
1031 RD4(sc, sc->misc_reg, &misc_reg); in tegra124_pll_recalc()
1034 if (sc->type != PLL_E) in tegra124_pll_recalc()
1037 p = 2 * (pr - 1); in tegra124_pll_recalc()
1039 dprintf("%s: %s (0x%08x, 0x%08x) - m: %d, n: %d, p: %d (%d): " in tegra124_pll_recalc()
1040 "e: %d, r: %d, o: %d - %s\n", __func__, in tegra124_pll_recalc()
1059 clk = clknode_create(clkdom, &tegra124_pll_class, &clkdef->clkdef); in pll_register()
1064 sc->clkdev = clknode_get_device(clk); in pll_register()
1065 sc->type = clkdef->type; in pll_register()
1066 sc->base_reg = clkdef->base_reg; in pll_register()
1067 sc->misc_reg = clkdef->misc_reg; in pll_register()
1068 sc->lock_mask = clkdef->lock_mask; in pll_register()
1069 sc->lock_enable = clkdef->lock_enable; in pll_register()
1070 sc->iddq_reg = clkdef->iddq_reg; in pll_register()
1071 sc->iddq_mask = clkdef->iddq_mask; in pll_register()
1072 sc->flags = clkdef->flags; in pll_register()
1073 sc->pdiv_table = clkdef->pdiv_table; in pll_register()
1074 sc->mnp_bits = clkdef->mnp_bits; in pll_register()
1090 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®); in config_utmi_pll()
1098 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg); in config_utmi_pll()
1100 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); in config_utmi_pll()
1109 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); in config_utmi_pll()
1112 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); in config_utmi_pll()
1116 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); in config_utmi_pll()
1119 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); in config_utmi_pll()
1122 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); in config_utmi_pll()
1126 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); in config_utmi_pll()
1129 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); in config_utmi_pll()
1133 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); in config_utmi_pll()
1135 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); in config_utmi_pll()
1144 rv = pll_register(sc->clkdom, pll_clks + i); in tegra124_init_plls()