1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
7  * Redistribution and use in source and binary forms, with or without
10  * 1. Redistributions of source code must retain the above copyright
30  * Zynq-700 SLCR driver.  Provides hooks for cpu_reset and PL control stuff.
33  * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
66 #define ZSLCR_LOCK(sc)		mtx_lock(&(sc)->sc_mtx)
67 #define	ZSLCR_UNLOCK(sc)		mtx_unlock(&(sc)->sc_mtx)
69 	mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev),	\
71 #define ZSLCR_LOCK_DESTROY(_sc)	mtx_destroy(&_sc->sc_mtx);
73 #define RD4(sc, off) 		(bus_read_4((sc)->mem_res, (off)))
74 #define WR4(sc, off, val) 	(bus_write_4((sc)->mem_res, (off), (val)))
79     "Xilinx Zynq-7000");
99 	   0, "Zynq IO PLL Frequency");
103 	   &arm_pll_frequency, 0, "Zynq ARM PLL Frequency");
107 	   &ddr_pll_frequency, 0, "Zynq DDR PLL Frequency");
133 	/* This has something to do with a work-around so the fsbl will load  in zy7_slcr_cpu_reset()
134 	 * the bitstream after soft-reboot.  It's very important.  in zy7_slcr_cpu_reset()
174 /* After PL configuration, enable level shifters and deassert top-level
216 		return (-1);  in cgem_set_ref_clk()
231 		return (-1);  in cgem_set_ref_clk()
257 zy7_pl_fclk_set_source(int unit, int source)  in zy7_pl_fclk_set_source()  argument
263 		return (-1);  in zy7_pl_fclk_set_source()
270 	/* Modify FPGAx source. */  in zy7_pl_fclk_set_source()
273 	reg |= (source << ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT);  in zy7_pl_fclk_set_source()
289 	int source;  in zy7_pl_fclk_get_source()  local
292 		return (-1);  in zy7_pl_fclk_get_source()
298 	source = (reg & ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK) >>   in zy7_pl_fclk_get_source()
302 	if ((source & 2) == 0)  in zy7_pl_fclk_get_source()
303 		source = ZY7_PL_FCLK_SRC_IO;  in zy7_pl_fclk_get_source()
307 	return (source);  in zy7_pl_fclk_get_source()
317 	int source;  in zy7_pl_fclk_set_freq()  local
320 		return (-1);  in zy7_pl_fclk_set_freq()
322 	source = zy7_pl_fclk_get_source(unit);  in zy7_pl_fclk_set_freq()
323 	switch (source) {  in zy7_pl_fclk_set_freq()
337 			return (-1);  in zy7_pl_fclk_set_freq()
353 		return (-1);  in zy7_pl_fclk_set_freq()
384 	int source;  in zy7_pl_fclk_get_freq()  local
387 		return (-1);  in zy7_pl_fclk_get_freq()
389 	source = zy7_pl_fclk_get_source(unit);  in zy7_pl_fclk_get_freq()
390 	switch (source) {  in zy7_pl_fclk_get_freq()
404 			return (-1);  in zy7_pl_fclk_get_freq()
438 		return (-1);  in zy7_pl_fclk_enable()
462 		return (-1);  in zy7_pl_fclk_disable()
487 		return (-1);  in zy7_pl_fclk_enabled()
504 		return (-1);  in zy7_pl_level_shifters_enabled()
553 	device_set_desc(dev, "Zynq-7000 slcr block");  in zy7_slcr_probe()
570 		"JTAG", "Quad-SPI", "NOR", "(3?)",  in zy7_slcr_attach()
578 	sc->dev = dev;  in zy7_slcr_attach()
584 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,  in zy7_slcr_attach()
586 	if (sc->mem_res == NULL) {  in zy7_slcr_attach()
604 		 "family: 0x%x sub-family: 0x%x rev: 0x%x",  in zy7_slcr_attach()
619 	/* Derive PLL frequencies from PS_CLK. */  in zy7_slcr_attach()
621 	if (OF_getencprop(node, "clock-frequency", &cell, sizeof(cell)) > 0)  in zy7_slcr_attach()
630 	/* Determine ARM PLL frequency. */  in zy7_slcr_attach()
635 		/* PLL is bypassed. */  in zy7_slcr_attach()
642 	/* Determine DDR PLL frequency. */  in zy7_slcr_attach()
647 		/* PLL is bypassed. */  in zy7_slcr_attach()
654 	/* Determine IO PLL frequency. */  in zy7_slcr_attach()
659 		/* PLL is bypassed. */  in zy7_slcr_attach()
680 	if (sc->mem_res != NULL)  in zy7_slcr_detach()
682 			     rman_get_rid(sc->mem_res), sc->mem_res);  in zy7_slcr_detach()