Lines Matching +full:pll +full:- +full:source

1 /* SPDX-License-Identifier: GPL-2.0 */
419  * appropriate clock source, program the source rate and execute a
420  * specific sequence to switch to the new clock source for both memory
751 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
809 …DQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
813 /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enab…
818  * @brief GPC2CLK-div-2
827 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
829 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
831 /** Fixed 408MHz PLL for use by peripheral clocks */
835 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */
837 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */
840  * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE.
842  * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
846 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
848 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */
850 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
852 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
854 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
856 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */
858 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */
860 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */
862 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */
864 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain …
866 /** Fixed frequency 960MHz PLL for USB and EAVB */
870 /** @brief NAFLL clock source for AXI_CBB */
872 /** @brief NAFLL clock source for BPMP */
874 /** @brief NAFLL clock source for ISP */
876 /** @brief NAFLL clock source for NVDEC */
878 /** @brief NAFLL clock source for NVENC */
880 /** @brief NAFLL clock source for NVJPG */
882 /** @brief NAFLL clock source for SCE */
884 /** @brief NAFLL clock source for SE */
886 /** @brief NAFLL clock source for TSEC */
888 /** @brief NAFLL clock source for TSECB */
890 /** @brief NAFLL clock source for VI */
892 /** @brief NAFLL clock source for VIC */
894 /** @brief NAFLL clock source for DISP */
896 /** @brief NAFLL clock source for GPU */
898 /** @brief NAFLL clock source for M-CPU cluster */
900 /** @brief NAFLL clock source for B-CPU cluster */