Lines Matching +full:pll +full:- +full:source
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
13 The CS2000-CP is an extremely versatile system clocking device that
21 - cirrus,cs2000-cp
28 clock-names:
30 - const: clk_in
31 - const: ref_clk
33 '#clock-cells':
39 cirrus,aux-output-source:
44 - 0 # CS2000CP_AUX_OUTPUT_REF_CLK: ref_clk input
45 - 1 # CS2000CP_AUX_OUTPUT_CLK_IN: clk_in input
46 - 2 # CS2000CP_AUX_OUTPUT_CLK_OUT: clk_out output
47 - 3 # CS2000CP_AUX_OUTPUT_PLL_LOCK: pll lock status
50 cirrus,clock-skip:
52 This mode allows the PLL to maintain lock even when CLK_IN
56 cirrus,dynamic-mode:
59 digital PLL of the silicon.
65 - compatible
66 - reg
67 - clocks
68 - clock-names
69 - '#clock-cells'
74 - |
75 #include <dt-bindings/clock/cirrus,cs2000-cp.h>
79 #address-cells = <1>;
80 #size-cells = <0>;
82 clock-controller@4f {
83 #clock-cells = <0>;
84 compatible = "cirrus,cs2000-cp";
87 clock-names = "clk_in", "ref_clk";
88 cirrus,aux-output-source = <CS2000CP_AUX_OUTPUT_CLK_OUT>;