Lines Matching +full:pll +full:- +full:source
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Redistribution and use in source and binary forms, with or without
9 * 1. Redistributions of source code must retain the above copyright
42 #include <dt-bindings/clock/tegra210-car.h>
113 /* Post divider <-> register value mapping. */
144 #define PLL(_id, cname, pname) \ macro
151 /* multiplexer for pll sources. */
164 /* Fractional divider (7.1) for PLL branch. */
179 /* P divider (2^n). for PLL branch. */
192 /* P divider (2^n). for PLL branch. */
221 /* Gate for PLL branch. */
270 /* PLLM: 880 MHz Clock source for EMC 2x clock */
272 PLL(TEGRA210_CLK_PLL_M, "pllM_out0", "osc"),
282 /* PLLMB: 880 MHz Clock source for EMC 2x clock */
284 PLL(TEGRA210_CLK_PLL_M, "pllMB_out0", "osc"),
294 /* PLLX: 1GHz Clock source for the fast CPU cluster and the shadow CPU */
296 PLL(TEGRA210_CLK_PLL_X, "pllX_out0", "osc_div_clk"),
306 /* PLLC: 510 MHz Clock source for camera use */
308 PLL(TEGRA210_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
317 /* PLLC2: 510 MHz Clock source for SE, VIC, TSECB, NVJPG scaling */
319 PLL(TEGRA210_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),
328 /* PLLC3: 510 MHz Clock source for NVENC, NVDEC scaling */
330 PLL(TEGRA210_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),
339 /* PLLC4: 600 MHz Clock source for SD/eMMC ans system busses */
341 PLL(TEGRA210_CLK_PLL_C4, "pllC4", "pllC4_src"),
352 /* PLLP: 408 MHz Clock source for most peripherals */
358 PLL(TEGRA210_CLK_PLL_P, "pllP_out0", "osc_div_clk"),
370 PLL(TEGRA210_CLK_PLL_A, "pllA", "osc_div_clk"),
382 PLL(TEGRA210_CLK_PLL_A1, "pllA1_out0", "osc_div_clk"),
391 /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */
393 PLL(TEGRA210_CLK_PLL_U, "pllU", "osc_div_clk"),
406 PLL(TEGRA210_CLK_PLL_D, "pllD_out", "osc_div_clk"),
418 PLL(TEGRA210_CLK_PLL_D2, "pllD2_out", "pllD2_src"),
431 PLL(0, "pllREFE", "osc_div_clk"),
444 PLL(TEGRA210_CLK_PLL_E, "pllE_out0", "pllE_src"),
452 /* PLLDP: 270 MHz Clock source fordisplay SOR (spread spectrum) */
454 PLL(0, "pllDP_out0", "pllDP_src"),
485 /* MUXes for PLL sources. */
498 /* Gates for PLL branches. */
540 /* Dividers for PLL branches. */
603 RD4(sc, sc->base_reg, ®); in pll_enable()
604 if (sc->type != PLL_E) in pll_enable()
607 WR4(sc, sc->base_reg, reg); in pll_enable()
616 RD4(sc, sc->base_reg, ®); in pll_disable()
617 if (sc->type != PLL_E) in pll_disable()
620 WR4(sc, sc->base_reg, reg); in pll_disable()
629 tbl = sc->pdiv_table; in pdiv_to_reg()
631 if (sc->flags & PLL_FLAG_PDIV_POWER2) in pdiv_to_reg()
632 return (ffs(p_div) - 1); in pdiv_to_reg()
637 while (tbl->divider != 0) { in pdiv_to_reg()
638 if (p_div <= tbl->divider) in pdiv_to_reg()
639 return (tbl->value); in pdiv_to_reg()
650 tbl = sc->pdiv_table; in reg_to_pdiv()
652 if (sc->flags & PLL_FLAG_PDIV_POWER2) in reg_to_pdiv()
657 while (tbl->divider) { in reg_to_pdiv()
658 if (reg == tbl->value) in reg_to_pdiv()
659 return (tbl->divider); in reg_to_pdiv()
669 return ((val >> shift) & ((1 << width) - 1)); in get_masked()
676 val &= ~(((1 << width) - 1) << shift); in set_masked()
677 val |= (v & ((1 << width) - 1)) << shift; in set_masked()
687 mnp_bits = &sc->mnp_bits; in get_divisors()
688 RD4(sc, sc->base_reg, &val); in get_divisors()
689 *m = get_masked(val, mnp_bits->m_shift, mnp_bits->m_width); in get_divisors()
690 *n = get_masked(val, mnp_bits->n_shift, mnp_bits->n_width); in get_divisors()
691 *p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width); in get_divisors()
700 mnp_bits = &sc->mnp_bits; in set_divisors()
701 val = set_masked(val, m, mnp_bits->m_shift, mnp_bits->m_width); in set_divisors()
702 val = set_masked(val, n, mnp_bits->n_shift, mnp_bits->n_width); in set_divisors()
703 val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width); in set_divisors()
712 switch (sc->type) { in is_locked()
714 RD4(sc, sc->misc_reg, ®); in is_locked()
719 RD4(sc, sc->misc_reg, ®); in is_locked()
724 RD4(sc, sc->base_reg, ®); in is_locked()
736 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) { in wait_for_lock()
742 printf("PLL lock timeout\n"); in wait_for_lock()
758 RD4(sc, sc->base_reg, ®); in plle_enable()
760 WR4(sc, sc->base_reg, reg); in plle_enable()
769 RD4(sc, sc->misc_reg, ®); in plle_enable()
776 WR4(sc, sc->misc_reg, reg); in plle_enable()
783 RD4(sc, sc->base_reg, ®); in plle_enable()
785 WR4(sc, sc->base_reg, reg); in plle_enable()
812 /* HW control of brick pll. */ in plle_enable()
813 RD4(sc, sc->misc_reg, ®); in plle_enable()
815 WR4(sc, sc->misc_reg, reg); in plle_enable()
828 /* Enable and start XUSBIO PLL HW control*/ in plle_enable()
842 /* Enable and start SATA PLL HW control */ in plle_enable()
858 /* Enable HW control of PCIe PLL. */ in plle_enable()
878 if (sc->type == PLL_E) in tegra210_pll_set_gate()
892 RD4(sc, sc->base_reg, ®); in tegra210_pll_get_gate()
894 WR4(sc, sc->base_reg, reg); in tegra210_pll_get_gate()
906 mnp_bits = &sc->mnp_bits; in pll_set_std()
907 if (m >= (1 << mnp_bits->m_width)) in pll_set_std()
909 if (n >= (1 << mnp_bits->n_width)) in pll_set_std()
911 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) in pll_set_std()
926 /* take pll out of IDDQ */ in pll_set_std()
927 if (sc->iddq_reg != 0) in pll_set_std()
928 MD4(sc, sc->iddq_reg, sc->iddq_mask, 0); in pll_set_std()
930 RD4(sc, sc->base_reg, ®); in pll_set_std()
931 reg = set_masked(reg, m, mnp_bits->m_shift, mnp_bits->m_width); in pll_set_std()
932 reg = set_masked(reg, n, mnp_bits->n_shift, mnp_bits->n_width); in pll_set_std()
933 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pll_set_std()
934 mnp_bits->p_width); in pll_set_std()
935 WR4(sc, sc->base_reg, reg); in pll_set_std()
937 /* Enable PLL. */ in pll_set_std()
938 RD4(sc, sc->base_reg, ®); in pll_set_std()
940 WR4(sc, sc->base_reg, reg); in pll_set_std()
943 RD4(sc, sc->misc_reg, ®); in pll_set_std()
944 reg |= sc->lock_enable; in pll_set_std()
945 WR4(sc, sc->misc_reg, reg); in pll_set_std()
949 /* Disable PLL */ in pll_set_std()
950 RD4(sc, sc->base_reg, ®); in pll_set_std()
952 WR4(sc, sc->base_reg, reg); in pll_set_std()
955 RD4(sc, sc->misc_reg, ®); in pll_set_std()
1012 * PLLD2 is used as source for pixel clock for HDMI.
1036 mnp_bits = &sc->mnp_bits; in plld2_set_freq()
1037 tbl = sc->pdiv_table; in plld2_set_freq()
1050 for (m = 1; m < (1 << mnp_bits->m_width); m++) { in plld2_set_freq()
1056 if (n >= (1 << mnp_bits->n_width)) in plld2_set_freq()
1066 err = *fout - vco / p; in plld2_set_freq()
1068 err = -err; in plld2_set_freq()
1120 mnp_bits = &sc->mnp_bits; in pllx_set_freq()
1125 /* Pre-divider is fixed, Compute post-divider */ in pllx_set_freq()
1136 if (m >= (1 << mnp_bits->m_width)) in pllx_set_freq()
1138 if (n >= (1 << mnp_bits->n_width)) in pllx_set_freq()
1140 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) in pllx_set_freq()
1151 /* If new post-divider is bigger that original, set it now. */ in pllx_set_freq()
1153 RD4(sc, sc->base_reg, ®); in pllx_set_freq()
1154 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pllx_set_freq()
1155 mnp_bits->p_width); in pllx_set_freq()
1156 WR4(sc, sc->base_reg, reg); in pllx_set_freq()
1161 /* 1 - disable dynamic ramp mode. */ in pllx_set_freq()
1166 /* 2 - Setup new ndiv. */ in pllx_set_freq()
1172 /* 3 - enable dynamic ramp. */ in pllx_set_freq()
1177 /* 4 - wait for done. */ in pllx_set_freq()
1178 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) { in pllx_set_freq()
1185 printf("PLL X dynamic ramp timedout\n"); in pllx_set_freq()
1189 /* 5 - copy new ndiv to base register. */ in pllx_set_freq()
1190 RD4(sc, sc->base_reg, ®); in pllx_set_freq()
1191 reg = set_masked(reg, n, mnp_bits->n_shift, in pllx_set_freq()
1192 mnp_bits->n_width); in pllx_set_freq()
1193 WR4(sc, sc->base_reg, reg); in pllx_set_freq()
1195 /* 6 - disable dynamic ramp mode. */ in pllx_set_freq()
1202 printf("PLL X is not locked !!\n"); in pllx_set_freq()
1206 /* If new post-divider is smaller that original, set it. */ in pllx_set_freq()
1208 RD4(sc, sc->base_reg, ®); in pllx_set_freq()
1209 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pllx_set_freq()
1210 mnp_bits->p_width); in pllx_set_freq()
1211 WR4(sc, sc->base_reg, reg); in pllx_set_freq()
1255 switch (sc->type) { in tegra210_pll_set_freq()
1309 if (sc->type == PLL_X) { in tegra210_pll_init()
1315 /* If PLL is enabled, enable lock detect too. */ in tegra210_pll_init()
1316 RD4(sc, sc->base_reg, ®); in tegra210_pll_init()
1318 RD4(sc, sc->misc_reg, ®); in tegra210_pll_init()
1319 reg |= sc->lock_enable; in tegra210_pll_init()
1320 WR4(sc, sc->misc_reg, reg); in tegra210_pll_init()
1322 if (sc->type == PLL_REFE) { in tegra210_pll_init()
1323 RD4(sc, sc->misc_reg, ®); in tegra210_pll_init()
1325 WR4(sc, sc->misc_reg, reg); in tegra210_pll_init()
1341 RD4(sc, sc->base_reg, ®); in tegra210_pll_recalc()
1342 RD4(sc, sc->misc_reg, &misc_reg); in tegra210_pll_recalc()
1347 if (sc->flags & PLL_FLAG_VCO_OUT) in tegra210_pll_recalc()
1354 dprintf("%s: %s (0x%08x, 0x%08x) - m: %d, n: %d, p: %d (%d): " in tegra210_pll_recalc()
1355 "e: %d, r: %d, o: %d - %s\n", __func__, in tegra210_pll_recalc()
1378 clk = clknode_create(clkdom, &tegra210_pll_class, &clkdef->clkdef); in pll_register()
1383 sc->clkdev = clknode_get_device(clk); in pll_register()
1384 sc->type = clkdef->type; in pll_register()
1385 sc->base_reg = clkdef->base_reg; in pll_register()
1386 sc->misc_reg = clkdef->misc_reg; in pll_register()
1387 sc->lock_enable = clkdef->lock_enable; in pll_register()
1388 sc->iddq_reg = clkdef->iddq_reg; in pll_register()
1389 sc->iddq_mask = clkdef->iddq_mask; in pll_register()
1390 sc->flags = clkdef->flags; in pll_register()
1391 sc->pdiv_table = clkdef->pdiv_table; in pll_register()
1392 sc->mnp_bits = clkdef->mnp_bits; in pll_register()
1408 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); in config_utmi_pll()
1410 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); in config_utmi_pll()
1412 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®); in config_utmi_pll()
1417 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg); in config_utmi_pll()
1419 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); in config_utmi_pll()
1425 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); in config_utmi_pll()
1429 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); in config_utmi_pll()
1433 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®); in config_utmi_pll()
1440 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg); in config_utmi_pll()
1443 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); in config_utmi_pll()
1446 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); in config_utmi_pll()
1450 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); in config_utmi_pll()
1453 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); in config_utmi_pll()
1456 CLKDEV_READ_4(sc->dev, XUSB_PLL_CFG0, ®); in config_utmi_pll()
1458 CLKDEV_WRITE_4(sc->dev, XUSB_PLL_CFG0, reg); in config_utmi_pll()
1462 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); in config_utmi_pll()
1464 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); in config_utmi_pll()
1473 rv = clknode_mux_register(sc->clkdom, tegra210_pll_sources + i); in tegra210_init_plls()
1479 rv = pll_register(sc->clkdom, pll_clks + i); in tegra210_init_plls()
1487 rv = clknode_fixed_register(sc->clkdom, tegra210_pll_fdivs + i); in tegra210_init_plls()
1493 rv = clknode_gate_register(sc->clkdom, tegra210_pll_gates + i); in tegra210_init_plls()
1499 rv = clknode_div_register(sc->clkdom, tegra210_pll_divs + i); in tegra210_init_plls()