1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
11  * Redistribution and use in source and binary forms, with or without
14  * 1. Redistributions of source code must retain the above copyright
85 #define	PRCI_LOCK(sc)			mtx_lock(&(sc)->mtx)
86 #define	PRCI_UNLOCK(sc)			mtx_unlock(&(sc)->mtx)
87 #define	PRCI_ASSERT_LOCKED(sc)		mtx_assert(&(sc)->mtx, MA_OWNED);
88 #define	PRCI_ASSERT_UNLOCKED(sc)	mtx_assert(&(sc)->mtx, MA_NOTOWNED);
101     bus_space_read_4((_sc)->bst, (_sc)->bsh, (_reg))
103     bus_space_write_4((_sc)->bst, (_sc)->bsh, (_reg), (_val))
111 #define PLL(_id, _name, _base)					\  macro
118 #define PLL_END	PLL(0, NULL, 0)
175 /* FU540 PLL clocks */
177 	PLL(FU540_PRCI_CORECLK, "coreclk", FU540_PRCI_COREPLL_CFG0),
178 	PLL(FU540_PRCI_DDRCLK, "ddrclk", FU540_PRCI_DDRPLL_CFG0),
179 	PLL(FU540_PRCI_GEMGXLCLK, "gemgxlclk", FU540_PRCI_GEMGXLPLL_CFG0),
222 /* FU740 PLL clocks */
224 	PLL(FU740_PRCI_CORECLK, "coreclk", FU740_PRCI_COREPLL_CFG0),
225 	PLL(FU740_PRCI_DDRCLK, "ddrclk", FU740_PRCI_DDRPLL_CFG0),
226 	PLL(FU740_PRCI_GEMGXLCLK, "gemgxlclk", FU740_PRCI_GEMGXLPLL_CFG0),
227 	PLL(FU740_PRCI_DVFSCORECLK, "dvfscoreclk", FU740_PRCI_DVFSCOREPLL_CFG0),
228 	PLL(FU740_PRCI_HFPCLK, "hfpclk", FU740_PRCI_HFPCLKPLL_CFG0),
229 	PLL(FU740_PRCI_CLTXCLK, "cltxclk", FU740_PRCI_CLTXPLL_CFG0),
268 	{ "sifive,fu540-c000-prci",	(uintptr_t)&fu540_prci_config },
269 	{ "sifive,fu740-c000-prci",	(uintptr_t)&fu740_prci_config },
295 	PRCI_LOCK(sc->parent_sc);  in prci_clk_pll_recalc()
301 		device_printf(sc->parent_sc->dev,  in prci_clk_pll_recalc()
303 		PRCI_UNLOCK(sc->parent_sc);  in prci_clk_pll_recalc()
307 	/* Calculate the PLL output */  in prci_clk_pll_recalc()
308 	val = PRCI_READ(sc->parent_sc, sc->reg);  in prci_clk_pll_recalc()
316 	PRCI_UNLOCK(sc->parent_sc);  in prci_clk_pll_recalc()
353 	PRCI_LOCK(sc->parent_sc);  in prci_clk_div_recalc()
359 		device_printf(sc->parent_sc->dev,  in prci_clk_div_recalc()
361 		PRCI_UNLOCK(sc->parent_sc);  in prci_clk_div_recalc()
366 	div = PRCI_READ(sc->parent_sc, sc->reg);  in prci_clk_div_recalc()
368 	*freq = refclk / (div + sc->bias);  in prci_clk_div_recalc()
370 	PRCI_UNLOCK(sc->parent_sc);  in prci_clk_div_recalc()
392 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)  in prci_probe()
407 	clk = clknode_create(parent_sc->clkdom, &prci_clk_pll_clknode_class,  in prci_pll_register()
413 	sc->parent_sc = parent_sc;  in prci_pll_register()
414 	sc->reg = reg;  in prci_pll_register()
416 	clknode_register(parent_sc->clkdom, clk);  in prci_pll_register()
426 	clk = clknode_create(parent_sc->clkdom, &prci_clk_div_clknode_class,  in prci_div_register()
432 	sc->parent_sc = parent_sc;  in prci_div_register()
433 	sc->reg = reg;  in prci_div_register()
434 	sc->bias = bias;  in prci_div_register()
436 	clknode_register(parent_sc->clkdom, clk);  in prci_div_register()
454 	sc->dev = dev;  in prci_attach()
457 	    compat_data)->ocd_data;  in prci_attach()
459 	mtx_init(&sc->mtx, device_get_nameunit(sc->dev), NULL, MTX_DEF);  in prci_attach()
461 	error = bus_alloc_resources(dev, prci_spec, &sc->res);  in prci_attach()
466 	sc->bst = rman_get_bustag(sc->res);  in prci_attach()
467 	sc->bsh = rman_get_bushandle(sc->res);  in prci_attach()
471 	    "#clock-cells", &ncells);  in prci_attach()
494 	sc->clkdom = clkdom_create(dev);  in prci_attach()
495 	if (sc->clkdom == NULL) {  in prci_attach()
501 	for (pll_clk = cfg->pll_clks; pll_clk->name; pll_clk++) {  in prci_attach()
502 		clkdef.id = pll_clk->id;  in prci_attach()
503 		clkdef.name = pll_clk->name;  in prci_attach()
504 		prci_pll_register(sc, &clkdef, pll_clk->reg);  in prci_attach()
507 	if (cfg->div_clks != NULL) {  in prci_attach()
509 		for (div_clk = cfg->div_clks; div_clk->name; div_clk++) {  in prci_attach()
510 			clkdef_div.id = div_clk->id;  in prci_attach()
511 			clkdef_div.name = div_clk->name;  in prci_attach()
512 			clkdef_div.parent_names = &div_clk->parent_name;  in prci_attach()
514 			prci_div_register(sc, &clkdef_div, div_clk->reg,  in prci_attach()
515 			    div_clk->bias);  in prci_attach()
519 	if (cfg->gate_clks != NULL) {  in prci_attach()
521 		for (gate_clk = cfg->gate_clks; gate_clk->name; gate_clk++) {  in prci_attach()
522 			clkdef_gate.clkdef.id = gate_clk->id;  in prci_attach()
523 			clkdef_gate.clkdef.name = gate_clk->name;  in prci_attach()
524 			clkdef_gate.clkdef.parent_names = &gate_clk->parent_name;  in prci_attach()
526 			clkdef_gate.offset = gate_clk->reg;  in prci_attach()
531 			error = clknode_gate_register(sc->clkdom,  in prci_attach()
536 				    gate_clk->name, error);  in prci_attach()
550 	clknode_fixed_register(sc->clkdom, cfg->tlclk_def);  in prci_attach()
552 	error = clkdom_finit(sc->clkdom);  in prci_attach()
556 	sc->nresets = cfg->nresets;  in prci_attach()
564 	bus_release_resources(dev, prci_spec, &sc->res);  in prci_attach()
565 	mtx_destroy(&sc->mtx);  in prci_attach()
635 	if (id >= sc->nresets)  in prci_reset_assert()
658 	if (id >= sc->nresets)  in prci_reset_is_asserted()