Lines Matching +full:pll +full:- +full:source
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Redistribution and use in source and binary forms, with or without
9 * 1. Redistributions of source code must retain the above copyright
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/reset/sun5i-ccu.h>
50 /* Non-exported clocks */
101 CCU_GATE(CLK_DRAM_AXI, "axi-dram", "axi", 0x5c, 0)
103 CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0)
104 CCU_GATE(CLK_AHB_EHCI, "ahb-ehci", "ahb", 0x60, 1)
105 CCU_GATE(CLK_AHB_OHCI, "ahb-ohci", "ahb", 0x60, 2)
106 CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5)
107 CCU_GATE(CLK_AHB_DMA, "ahb-dma", "ahb", 0x60, 6)
108 CCU_GATE(CLK_AHB_BIST, "ahb-bist", "ahb", 0x60, 7)
109 CCU_GATE(CLK_AHB_MMC0, "ahb-mmc0", "ahb", 0x60, 8)
110 CCU_GATE(CLK_AHB_MMC1, "ahb-mmc1", "ahb", 0x60, 9)
111 CCU_GATE(CLK_AHB_MMC2, "ahb-mmc2", "ahb", 0x60, 10)
112 CCU_GATE(CLK_AHB_NAND, "ahb-nand", "ahb", 0x60, 13)
113 CCU_GATE(CLK_AHB_SDRAM, "ahb-sdram", "ahb", 0x60, 14)
114 CCU_GATE(CLK_AHB_SPI0, "ahb-spi0", "ahb", 0x60, 20)
115 CCU_GATE(CLK_AHB_SPI1, "ahb-spi1", "ahb", 0x60, 21)
116 CCU_GATE(CLK_AHB_SPI2, "ahb-spi2", "ahb", 0x60, 22)
117 CCU_GATE(CLK_AHB_GPS, "ahb-gps", "ahb", 0x60, 26)
118 CCU_GATE(CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", 0x60, 28)
120 CCU_GATE(CLK_AHB_VE, "ahb-ve", "ahb", 0x64, 0)
121 CCU_GATE(CLK_AHB_LCD, "ahb-lcd", "ahb", 0x64, 4)
122 CCU_GATE(CLK_AHB_CSI, "ahb-csi", "ahb", 0x64, 8)
123 CCU_GATE(CLK_AHB_DE_BE, "ahb-de-be", "ahb", 0x64, 12)
124 CCU_GATE(CLK_AHB_DE_FE, "ahb-de-fe", "ahb", 0x64, 14)
125 CCU_GATE(CLK_AHB_IEP, "ahb-iep", "ahb", 0x64, 19)
126 CCU_GATE(CLK_AHB_GPU, "ahb-gpu", "ahb", 0x64, 20)
128 CCU_GATE(CLK_APB0_CODEC, "apb0-codec", "apb0", 0x68, 0)
129 CCU_GATE(CLK_APB0_PIO, "apb0-pio", "apb0", 0x68, 5)
130 CCU_GATE(CLK_APB0_IR, "apb0-ir", "apb0", 0x68, 6)
132 CCU_GATE(CLK_APB1_I2C0, "apb1-i2c0", "apb1", 0x6c, 0)
133 CCU_GATE(CLK_APB1_I2C1, "apb1-i2c1", "apb1", 0x6c, 1)
134 CCU_GATE(CLK_APB1_I2C2, "apb1-i2c2", "apb1", 0x6c, 2)
135 CCU_GATE(CLK_APB1_UART1, "apb1-uart1", "apb1", 0x6c, 17)
136 CCU_GATE(CLK_APB1_UART3, "apb1-uart3", "apb1", 0x6c, 19)
138 CCU_GATE(CLK_DRAM_VE, "dram-ve", "pll-ddr", 0x100, 0)
139 CCU_GATE(CLK_DRAM_CSI, "dram-csi", "pll-ddr", 0x100, 1)
140 CCU_GATE(CLK_DRAM_DE_FE, "dram-de-fe", "pll-ddr", 0x100, 25)
141 CCU_GATE(CLK_DRAM_DE_BE, "dram-de-be", "pll-ddr", 0x100, 26)
142 CCU_GATE(CLK_DRAM_ACE, "dram-ace", "pll-ddr", 0x100, 29)
143 CCU_GATE(CLK_DRAM_IEP, "dram-iep", "pll-ddr", 0x100, 31)
145 CCU_GATE(CLK_CODEC, "codec", "pll-audio", 0x140, 31)
154 .name = "pll-core",
168 * We only implement pll-audio for now
169 * For pll-audio-2/4/8 x we need a way to change the frequency
175 .name = "pll-audio",
188 /* Missing PLL3-Video */
189 /* Missing PLL4-VE */
194 .name = "pll-ddr-base",
207 static const char *pll_ddr_parents[] = {"pll-ddr-base"};
211 .name = "pll-ddr",
220 static const char *pll_ddr_other_parents[] = {"pll-ddr-base"};
224 .name = "pll-ddr-other",
236 .name = "pll-periph",
249 /* Missing PLL7-VIDEO1 */
251 static const char *cpu_parents[] = {"osc32k", "hosc", "pll-core", "pll-periph"};
282 static const char *ahb_parents[] = {"axi", "cpu", "pll-periph"};
328 static const char *apb1_parents[] = {"hosc", "pll-periph", "osc32k"};
344 static const char *mod_parents[] = {"hosc", "pll-periph", "pll-ddr-other"};
490 /* Missing DE-BE clock */
491 /* Missing DE-FE clock */
527 if (!ofw_bus_is_compatible(dev, "allwinner,sun5i-a13-ccu")) in ccu_a13_probe()
541 sc->resets = a13_ccu_resets; in ccu_a13_attach()
542 sc->nresets = nitems(a13_ccu_resets); in ccu_a13_attach()
543 sc->gates = a13_ccu_gates; in ccu_a13_attach()
544 sc->ngates = nitems(a13_ccu_gates); in ccu_a13_attach()
545 sc->clks = a13_ccu_clks; in ccu_a13_attach()
546 sc->nclks = nitems(a13_ccu_clks); in ccu_a13_attach()