Lines Matching +full:pll +full:- +full:source

2  * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
4  * SPDX-License-Identifier: BSD-3-Clause
117 	/* PLL control API functions */
325  * @PM_PLL_PARAM_DIV2:		Enable for divide by 2 function inside the PLL
326  * @PM_PLL_PARAM_FBDIV:		Feedback divisor integer portion for the PLL
327  * @PM_PLL_PARAM_DATA:		Feedback divisor fractional portion for the PLL
328  * @PM_PLL_PARAM_PRE_SRC:	Clock source for PLL input
329  * @PM_PLL_PARAM_POST_SRC:	Clock source for PLL Bypass mode
332  * @PM_PLL_PARAM_LFHF:		PLL loop filter high frequency capacitor control
333  * @PM_PLL_PARAM_CP:		PLL charge pump control
334  * @PM_PLL_PARAM_RES:		PLL loop filter resistor control
351  * @PM_PLL_MODE_RESET:		PLL is in reset (not locked)
352  * @PM_PLL_MODE_INTEGER:	PLL is locked in integer mode
353  * @PM_PLL_MODE_FRACTIONAL:	PLL is locked in fractional mode