micro\-TLB (full) in projects: freebsd - OpenGrok search results

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Searched +full:micro +full:- +full:tlb (Results 1 – 25 of 36) sorted by relevance

/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a65/
H A D	ifu.json	3 "PublicDescription": "I-Cache miss on an access from the prefetch block", 6 "BriefDescription": "I-Cache miss on an access from the prefetch block" 9 …"PublicDescription": "Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l… 12 …"BriefDescription": "Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l … 15 …"PublicDescription": "Micro-predictor conditional/direction mispredict, with respect to. if3/if4 p… 18 …"BriefDescription": "Micro-predictor conditional/direction mispredict, with respect to. if3/if4 pr… 21 … "PublicDescription": "Micro-predictor address mispredict, with respect to if3/if4 predictor", 24 "BriefDescription": "Micro-predictor address mispredict, with respect to if3/if4 predictor" 27 "PublicDescription": "Micro-predictor hit with immediate redirect", 30 "BriefDescription": "Micro-predictor hit with immediate redirect" [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a75/
H A D	cache.json	111 "PublicDescription": "Number of ways read in the instruction cache - Tag RAM", 114 "BriefDescription": "Number of ways read in the instruction cache - Tag RAM" 117 "PublicDescription": "Number of ways read in the instruction cache - Data RAM", 120 "BriefDescription": "Number of ways read in the instruction cache - Data RAM" 129 "PublicDescription": "Level 1 PLD TLB refill", 132 "BriefDescription": "Level 1 PLD TLB refill" 135 …"PublicDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwa… 138 …"BriefDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwar… 141 "PublicDescription": "Level 1 TLB flush", 144 "BriefDescription": "Level 1 TLB flush" [all …]
/freebsd/lib/libpmc/
H A D	pmc.atom.3	`44 .Bl -tag -width "Li PMC_CLASS_IAP" 46 Fixed-function counters that count only one hardware event per counter. 58 .%B "IA-32 Intel(R) Architecture Software Developer's Manual" 60 .%N "Order Number 253669-027US" 69 .Bl -column "PMC_CAP_INTERRUPT" "Support" 86 .Bl -tag -width indent 94 Configure the PMC to count the number of de-asserted to asserted 120 Events that require core-specificity to be specified use a 126 .Bl -tag -width indent 142 .Bl -tag -width indent [all …]`
H A D	pmc.core2.3	44 .Bl -tag -width "Li PMC_CLASS_IAP" 46 Fixed-function counters that count only one hardware event per counter. 58 .%B "IA-32 Intel(R) Architecture Software Developer's Manual" 60 .%N "Order Number 253669-027US" 67 Not all CPUs in this family implement fixed-function counters. 70 .Bl -column "PMC_CAP_INTERRUPT" "Support" 87 .Bl -tag -width indent 93 Configure the PMC to count the number of de-asserted to asserted 119 Events that require core-specificity to be specified use a 125 .Bl -tag -width indent [all …]
H A D	pmc.atomsilvermont.3	`45 .Bl -tag -width "Li PMC_CLASS_IAP" 47 Fixed-function counters that count only one hardware event per counter. 59 .%B "Intel 64 and IA-32 Intel(R) Architecture Software Developer's Manual" 61 .%N "Order Number 325462-050US" 70 .Bl -column "PMC_CAP_INTERRUPT" "Support" 87 .Bl -tag -width indent 95 Configure the PMC to count the number of de-asserted to asserted 121 Events that require core-specificity to be specified use a 127 .Bl -tag -width indent 143 .Bl -tag -width indent [all …]`
H A D	pmc.corei7.3	44 .Bl -tag -width "Li PMC_CLASS_IAP" 46 Fixed-function counters that count only one hardware event per counter. 58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" 60 .%N "Order Number: 253669-033US" 67 Not all CPUs in this family implement fixed-function counters. 70 .Bl -column "PMC_CAP_INTERRUPT" "Support" 87 .Bl -tag -width indent 89 Configure the Off-core Response bits. 90 .Bl -tag -width indent 113 I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, [all …]
H A D	pmc.haswell.3	`45 .Bl -tag -width "Li PMC_CLASS_IAP" 47 Fixed-function counters that count only one hardware event per counter. 59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 61 .%N "Order Number: 325462-045US" 70 .Bl -column "PMC_CAP_INTERRUPT" "Support" 87 .Bl -tag -width indent 89 Configure the Off-core Response bits. 90 .Bl -tag -width indent 128 M-state initial lookup stat in L3. 130 E-state. [all …]`
H A D	pmc.haswellxeon.3	`46 .Bl -tag -width "Li PMC_CLASS_IAP" 48 Fixed-function counters that count only one hardware event per counter. 60 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 62 .%N "Order Number: 325462-052US" 71 .Bl -column "PMC_CAP_INTERRUPT" "Support" 88 .Bl -tag -width indent 90 Configure the Off-core Response bits. 91 .Bl -tag -width indent 129 M-state initial lookup stat in L3. 131 E-state. [all …]`
H A D	pmc.amd.3	`1 .\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved. 49 .%Q "Advanced Micro Devices, Inc." 54 .Bl -column "PMC_CAP_INTERRUPT" "Support" 71 .Bl -tag -width indent 77 Configure the counter to only count negated-to-asserted transitions 93 These additional qualifiers are event-specific and are documented 109 .Bl -tag -widt [all...]`
H A D	pmc.westmere.3	`44 .Bl -tag -width "Li PMC_CLASS_IAP" 46 Fixed-function counters that count only one hardware event per counter. 58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" 60 .%N "Order Number: 253669-033US" 69 .Bl -column "PMC_CAP_INTERRUPT" "Support" 86 .Bl -tag -width indent 88 Configure the Off-core Response bits. 89 .Bl -tag -width indent 114 I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, 138 Non-DRAM requests that were serviced by IOH. [all …]`
H A D	pmc.ivybridgexeon.3	`45 .Bl -tag -width "Li PMC_CLASS_IAP" 47 Fixed-function counters that count only one hardware event per counter. 59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 60 .%N "Order Number: 325462-045US" 69 .Bl -column "PMC_CAP_INTERRUPT" "Support" 86 .Bl -tag -width indent 88 Configure the Off-core Response bits. 89 .Bl -tag -width indent 126 M-state initial lookup stat in L3. 128 E-state. [all …]`
H A D	pmc.ivybridge.3	`44 .Bl -tag -width "Li PMC_CLASS_IAP" 46 Fixed-function counters that count only one hardware event per counter. 58 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 60 .%N "Order Number: 253669-043US" 69 .Bl -column "PMC_CAP_INTERRUPT" "Support" 86 .Bl -tag -width indent 88 Configure the Off-core Response bits. 89 .Bl -tag -width indent 126 M-state initial lookup stat in L3. 128 E-state. [all …]`
H A D	pmc.sandybridge.3	`45 .Bl -tag -width "Li PMC_CLASS_IAP" 47 Fixed-function counters that count only one hardware event per counter. 62 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" 64 .%N "Order Number: 253669-039US" 73 .Bl -column "PMC_CAP_INTERRUPT" "Support" 90 .Bl -tag -width indent 92 Configure the Off-core Response bits. 93 .Bl -tag -width indent 130 M-state initial lookup stat in L3. 132 E-state. [all …]`
H A D	pmc.sandybridgexeon.3	`45 .Bl -tag -width "Li PMC_CLASS_IAP" 47 Fixed-function counters that count only one hardware event per counter. 59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 61 .%N "Order Number: 253669-043US" 70 .Bl -column "PMC_CAP_INTERRUPT" "Support" 87 .Bl -tag -width indent 89 Configure the Off-core Response bits. 90 .Bl -tag -width indent 127 M-state initial lookup stat in L3. 129 E-state. [all …]`
H A D	pmc.core.3	`50 .%B IA-32 Intel\(rg Architecture Software Developer's Manual 52 .%N Order Number 253669-027US 63 .Bl -column "PMC_CAP_INTERRUPT" "Support" 80 .Bl -tag -width indent 86 Configure the PMC to count the number of de-asserted to asserted 112 Events that require core-specificity to be specified use a 118 .Bl -tag -width indent -compact 133 .Bl -tag -width indent -compact 148 .Bl -tag -width "exclude" -compact 165 .Bl -tag -width indent -compact [all …]`
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a53/
H A D	pipeline.json	10 … DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre… 20 …"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being p… 25 "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed" 30 …"BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instruc… 40 … "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
/freebsd/lib/libpmc/pmu-events/arch/arm64/
H A D	common-and-microarch.json	15 "PublicDescription": "Attributable Level 1 instruction TLB refill", 18 "BriefDescription": "Attributable Level 1 instruction TLB refill" 33 "PublicDescription": "Attributable Level 1 data TLB refill", 36 "BriefDescription": "Attributable Level 1 data TLB refill" 129 "PublicDescription": "Attributable Level 1 data cache write-back", 132 "BriefDescription": "Attributable Level 1 data cache write-back" 147 "PublicDescription": "Attributable Level 2 data cache write-back", 150 "BriefDescription": "Attributable Level 2 data cache write-back" 219 "PublicDescription": "Attributable Level 1 data or unified TLB access", 222 "BriefDescription": "Attributable Level 1 data or unified TLB access" [all …]
/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A D	renesas,ipmmu-vmsa.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas VMSA-Compatible IOMMU 10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 15 connected to the IPMMU through a port called micro-TLB. 20 - items: 21 - enum: 22 - renesas,ipmmu-r8a73a4 # R-Mobile APE6 [all …]`
H A D	msm,iommu-v0.txt	5 of the CPU, each connected to the IOMMU through a port called micro-TLB. 9 - compatible: Must contain "qcom,apq8064-iommu". 10 - reg: Base address and size of the IOMMU registers. 11 - interrupts: Specifiers for the MMU fault interrupts. For instances that 12 support secure mode two interrupts must be specified, for non-secure and 15 - #iommu-cells: The number of cells needed to specify the stream id. This 17 - qcom,ncb: The total number of context banks in the IOMMU. 18 - clocks : List of clocks to be used during SMMU register access. See 19 Documentation/devicetree/bindings/clock/clock-bindings.txt 21 here, there must be a corresponding entry in clock-names [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen1/
H A D	recommended.json	`4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)", 119 "MetricGroup": "tlb" 148 "BriefDescription": "Micro-ops Dispatched", 160 "BriefDescription": "Micro-ops Retired" 168 "ScaleUnit": "3e-5MiB" 172 …roximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)", 176 "ScaleUnit": "6.1e-5MiB"`
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen2/
H A D	recommended.json	`4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)", 119 "MetricGroup": "tlb" 148 "BriefDescription": "Micro-ops Dispatched", 160 "BriefDescription": "Micro-ops Retired" 168 "ScaleUnit": "3e-5MiB" 172 …roximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)", 176 "ScaleUnit": "6.1e-5MiB"`
/freebsd/lib/libpmc/pmu-events/arch/x86/goldmont/
H A D	pipeline.json	263 …ocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g.… 273 …ource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), r… 328 …nts loads blocked because they are unable to find their physical address in the micro TLB (UTLB).", 352 "BriefDescription": "Self-Modifying Code detected", 357 …ction and has to perform a machine clear because of that modification. Self-modifying code (SMC) … 367 …ed includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, tho… 371 "BriefDescription": "Uops requested but not-delivered to the back-end per cycle", 376 …-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and… 407 …ssued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the u…
/freebsd/lib/libpmc/pmu-events/arch/x86/goldmontplus/
H A D	pipeline.json	284 "BriefDescription": "Instructions retired - using Reduced Skid PEBS feature", 312 …ocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g.… 324 …ource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), r… 384 …nts loads blocked because they are unable to find their physical address in the micro TLB (UTLB).", 419 …r of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Store… 424 "BriefDescription": "Self-Modifying Code detected", 431 …ction and has to perform a machine clear because of that modification. Self-modifying code (SMC) … 443 …ed includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, tho… 447 "BriefDescription": "Uops requested but not-delivered to the back-end per cycle", 454 …-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sandybridge/
H A D	pipeline.json	42 "BriefDescription": "Speculative and retired macro-conditional branches.", 51 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi… 87 "BriefDescription": "Not taken macro-conditional branches.", 96 "BriefDescription": "Taken speculative and retired macro-conditional branches.", 105 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding… 158 "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).", 168 "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS).", 187 … "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS).", 197 …t and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS).", 207 "BriefDescription": "Return instructions retired. (Precise Event - PEBS).", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/jaketown/
H A D	pipeline.json	42 "BriefDescription": "Speculative and retired macro-conditional branches.", 51 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi… 87 "BriefDescription": "Not taken macro-conditional branches.", 96 "BriefDescription": "Taken speculative and retired macro-conditional branches.", 105 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding… 158 "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).", 324 … "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).", 330 … "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", 476 …miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1… 486 …"BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-com… [all …]