Lines Matching +full:micro +full:- +full:tlb

44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "IA-32 Intel(R) Architecture Software Developer's Manual"
60 .%N "Order Number 253669-027US"
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
94 Configure the PMC to count the number of de-asserted to asserted
120 Events that require core-specificity to be specified use a
126 .Bl -tag -width indent
142 .Bl -tag -width indent
158 .Bl -tag -width "exclude"
176 .Bl -tag -width indent
198 .Bl -tag -width indent
214 .Bl -tag -width indent
224 .Bl -tag -width indent
331 This event is thread-independent.
335 This event is thread-independent.
340 This event is thread-independent.
346 This event is thread-independent.
352 This event is thread-independent.
449 The number explicit write-back bus transactions due to dirty line
487 The number of memory access that missed the Data TLB
490 The number of loads that missed the Data TLB.
493 The number of stores that missed the Data TLB.
507 was generated by a non-SIMD execution unit.
520 The number of Data TLB misses, including misses that result from
527 The number of Data TLB misses due to load operations.
530 The number of Data TLB misses due to store operations.
565 The number of floating point computational micro-ops executed.
905 The number of micro-ops dispatched for execution.
908 The number of cycles micro-ops were dispatched for execution on port
912 The number of cycles micro-ops were dispatched for execution on port
916 The number of cycles micro-ops were dispatched for execution on port
920 The number of cycles micro-ops were dispatched for execution on port
924 The number of cycles micro-ops were dispatched for execution on port
928 The number of cycles micro-ops were dispatched for execution on port
1028 The number of SIMD saturated arithmetic micro-ops retired.
1031 The number of SIMD saturated arithmetic micro-ops executed.
1034 The number of SIMD micro-ops retired.
1037 The number of SIMD micro-ops executed.
1040 The number of SIMD packed arithmetic micro-ops executed.
1043 The number of SIMD packed arithmetic micro-ops executed.
1046 The number of SIMD packed logical micro-ops executed.
1049 The number of SIMD packed logical micro-ops executed.
1052 The number of SIMD packed multiply micro-ops retired.
1055 The number of SIMD packed multiply micro-ops executed.
1058 The number of SIMD pack micro-ops retired.
1061 The number of SIMD pack micro-ops executed.
1064 The number of SIMD packed shift micro-ops retired.
1067 The number of SIMD packed shift micro-ops executed.
1070 The number of SIMD unpack micro-ops executed.
1073 The number of SIMD unpack micro-ops executed.
1080 This event is thread-independent.
1088 The number of times SSE non-temporal store instructions were executed.
1120 The number of micro-ops retired that fused a load with another
1124 The number of store address calculations that fused into one micro-op.
1128 micro-op.
1131 The number of fused micro-ops retired.
1134 The number of non-fused micro-ops retired.
1137 The number of micro-ops retired.
1140 The number of x87 floating-point computational micro-ops retired.
1143 The number of x87 floating-point computational micro-ops executed.
1154 The following table shows the mapping between the PMC-independent
1158 .Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" "PMC Class"
1161 .It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED Ta Li PMC_CLASS_IAP
1162 .It Li ic-misses Ta Li ICACHE.MISSES Ta Li PMC_CLASS_IAP
1165 .It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P Ta Li PMC_CLASS_IAF