Lines Matching +full:micro +full:- +full:tlb

45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
59 .%B "Intel 64 and IA-32 Intel(R) Architecture Software Developer's Manual"
61 .%N "Order Number 325462-050US"
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
95 Configure the PMC to count the number of de-asserted to asserted
121 Events that require core-specificity to be specified use a
127 .Bl -tag -width indent
143 .Bl -tag -width indent
159 .Bl -tag -width "exclude"
177 .Bl -tag -width indent
199 .Bl -tag -width indent
215 .Bl -tag -width indent
225 .Bl -tag -width indent
267 The number of load micro-ops retired that hit L2.
270 The number of load micro-ops retired that missed L2.
289 Every cycle when a D-side (walks due to a load) page walk is in progress.
291 page-walks.
296 Every cycle when a I-side (walks due to an instruction fetch) page walk is in
299 page-walks.
304 Since a page walk implies a TLB miss, the number of TLB misses can be counted
321 The XQ may reject transactions from the L2Q (non-cacheable
322 requests), BBS (L2 misses) and WOB (L2 write-back victims)
376 For instructions that consist of multiple micro-ops, this event counts the
377 retirement of the last micro-op of the instruction.
382 The number of micro-ops retired that were supplied from MSROM.
385 The number of micro-ops retired.
389 Self-modifying code causes a severe penalty in all Intel
475 The number of cycles when the front-end does not provide any
479 The number of cycles when the front-end does not provide any
523 .An -nosplit