1b2934971SMitchell Horne.\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved. 2b2934971SMitchell Horne.\" 3b2934971SMitchell Horne.\" Redistribution and use in source and binary forms, with or without 4b2934971SMitchell Horne.\" modification, are permitted provided that the following conditions 5b2934971SMitchell Horne.\" are met: 6b2934971SMitchell Horne.\" 1. Redistributions of source code must retain the above copyright 7b2934971SMitchell Horne.\" notice, this list of conditions and the following disclaimer. 8b2934971SMitchell Horne.\" 2. Redistributions in binary form must reproduce the above copyright 9b2934971SMitchell Horne.\" notice, this list of conditions and the following disclaimer in the 10b2934971SMitchell Horne.\" documentation and/or other materials provided with the distribution. 11b2934971SMitchell Horne.\" 12b2934971SMitchell Horne.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13b2934971SMitchell Horne.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14b2934971SMitchell Horne.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15b2934971SMitchell Horne.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16b2934971SMitchell Horne.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17b2934971SMitchell Horne.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18b2934971SMitchell Horne.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19b2934971SMitchell Horne.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20b2934971SMitchell Horne.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21b2934971SMitchell Horne.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22b2934971SMitchell Horne.\" SUCH DAMAGE. 23b2934971SMitchell Horne.\" 24*b74aaa1aSGraham Percival.Dd June 24, 2023 25b2934971SMitchell Horne.Dt PMC.AMD 3 26b2934971SMitchell Horne.Os 27b2934971SMitchell Horne.Sh NAME 28b2934971SMitchell Horne.Nm pmc.amd 29b2934971SMitchell Horne.Nm pmc.k8 30b2934971SMitchell Horne.Nd measurement events for 31b2934971SMitchell Horne.Tn AMD 32b2934971SMitchell Horne.Tn Athlon 64 33b2934971SMitchell Horne(K8 family) CPUs 34b2934971SMitchell Horne.Sh LIBRARY 35b2934971SMitchell Horne.Lb libpmc 36b2934971SMitchell Horne.Sh SYNOPSIS 37b2934971SMitchell Horne.In pmc.h 38b2934971SMitchell Horne.Sh DESCRIPTION 39b2934971SMitchell HorneAMD K8 PMCs are present in the 40b2934971SMitchell Horne.Tn "AMD Athlon64" 41b2934971SMitchell Horneand 42b2934971SMitchell Horne.Tn "AMD Opteron" 43b2934971SMitchell Horneseries of CPUs. 44b2934971SMitchell HorneThey are documented in the 45b2934971SMitchell Horne.Rs 46b2934971SMitchell Horne.%B "BIOS and Kernel Developer's Guide for the AMD Athlon(tm) 64 and AMD Opteron Processors" 47b2934971SMitchell Horne.%N "Publication No. 26094" 48b2934971SMitchell Horne.%D "April 2004" 49b2934971SMitchell Horne.%Q "Advanced Micro Devices, Inc." 50b2934971SMitchell Horne.Re 51b2934971SMitchell Horne.Ss PMC Features 52b2934971SMitchell HorneAMD K8 PMCs are 48 bits wide. 53b2934971SMitchell HorneEach CPU contains 4 PMCs with the following capabilities: 54b2934971SMitchell Horne.Bl -column "PMC_CAP_INTERRUPT" "Support" 55b2934971SMitchell Horne.It Em Capability Ta Em Support 56b2934971SMitchell Horne.It PMC_CAP_CASCADE Ta \&No 57b2934971SMitchell Horne.It PMC_CAP_EDGE Ta Yes 58b2934971SMitchell Horne.It PMC_CAP_INTERRUPT Ta Yes 59b2934971SMitchell Horne.It PMC_CAP_INVERT Ta Yes 60b2934971SMitchell Horne.It PMC_CAP_READ Ta Yes 61b2934971SMitchell Horne.It PMC_CAP_PRECISE Ta \&No 62b2934971SMitchell Horne.It PMC_CAP_SYSTEM Ta Yes 63b2934971SMitchell Horne.It PMC_CAP_TAGGING Ta \&No 64b2934971SMitchell Horne.It PMC_CAP_THRESHOLD Ta Yes 65b2934971SMitchell Horne.It PMC_CAP_USER Ta Yes 66b2934971SMitchell Horne.It PMC_CAP_WRITE Ta Yes 67b2934971SMitchell Horne.El 68b2934971SMitchell Horne.Ss Event Qualifiers 69b2934971SMitchell HorneEvent specifiers for AMD K8 PMCs can have the following optional 70b2934971SMitchell Hornequalifiers: 71b2934971SMitchell Horne.Bl -tag -width indent 72b2934971SMitchell Horne.It Li count= Ns Ar value 73b2934971SMitchell HorneConfigure the counter to increment only if the number of configured 74b2934971SMitchell Horneevents measured in a cycle is greater than or equal to 75b2934971SMitchell Horne.Ar value . 76b2934971SMitchell Horne.It Li edge 77b2934971SMitchell HorneConfigure the counter to only count negated-to-asserted transitions 78b2934971SMitchell Horneof the conditions expressed by the other fields. 79b2934971SMitchell HorneIn other words, the counter will increment only once whenever a given 80b2934971SMitchell Hornecondition becomes true, irrespective of the number of clocks during 81b2934971SMitchell Hornewhich the condition remains true. 82b2934971SMitchell Horne.It Li inv 83b2934971SMitchell HorneInvert the sense of comparison when the 84b2934971SMitchell Horne.Dq Li count 85b2934971SMitchell Hornequalifier is present, making the counter to increment when the 86b2934971SMitchell Hornenumber of events per cycle is less than the value specified by 87b2934971SMitchell Hornethe 88b2934971SMitchell Horne.Dq Li count 89b2934971SMitchell Hornequalifier. 90b2934971SMitchell Horne.It Li mask= Ns Ar qualifier 91b2934971SMitchell HorneMany event specifiers for AMD K8 PMCs need to be additionally 92b2934971SMitchell Hornequalified using a mask qualifier. 93b2934971SMitchell HorneThese additional qualifiers are event-specific and are documented 94b2934971SMitchell Hornealong with their associated event specifiers below. 95b2934971SMitchell Horne.It Li os 96b2934971SMitchell HorneConfigure the PMC to count events happening at privilege level 0. 97b2934971SMitchell Horne.It Li usr 98b2934971SMitchell HorneConfigure the PMC to count events occurring at privilege levels 1, 2 99b2934971SMitchell Horneor 3. 100b2934971SMitchell Horne.El 101b2934971SMitchell Horne.Pp 102b2934971SMitchell HorneIf neither of the 103b2934971SMitchell Horne.Dq Li os 104b2934971SMitchell Horneor 105b2934971SMitchell Horne.Dq Li usr 106b2934971SMitchell Hornequalifiers were specified, the default is to enable both. 107b2934971SMitchell Horne.Ss AMD K8 Event Specifiers 108b2934971SMitchell HorneThe event specifiers supported on AMD K8 PMCs are: 109b2934971SMitchell Horne.Bl -tag -width indent 110b2934971SMitchell Horne.It Li k8-bu-cpu-clk-unhalted 111b2934971SMitchell Horne.Pq Event 76H 112b2934971SMitchell HorneCount the number of clock cycles when the CPU is not in the HLT or 113b2934971SMitchell HorneSTPCLK states. 114b2934971SMitchell Horne.It Li k8-bu-fill-request-l2-miss Op Li ,mask= Ns Ar qualifier 115b2934971SMitchell Horne.Pq Event 7EH 116b2934971SMitchell HorneCount fill requests that missed in the L2 cache. 117b2934971SMitchell HorneThis event may be further qualified using 118b2934971SMitchell Horne.Ar qualifier , 119b2934971SMitchell Hornewhich is a 120b2934971SMitchell Horne.Ql + 121b2934971SMitchell Horneseparated set of the following keywords: 122b2934971SMitchell Horne.Pp 123b2934971SMitchell Horne.Bl -tag -width indent -compact 124b2934971SMitchell Horne.It Li dc-fill 125b2934971SMitchell HorneCount data cache fill requests. 126b2934971SMitchell Horne.It Li ic-fill 127b2934971SMitchell HorneCount instruction cache fill requests. 128b2934971SMitchell Horne.It Li tlb-reload 129b2934971SMitchell HorneCount TLB reloads. 130b2934971SMitchell Horne.El 131b2934971SMitchell Horne.Pp 132b2934971SMitchell HorneThe default is to count all types of requests. 133b2934971SMitchell Horne.It Li k8-bu-fill-into-l2 Op Li ,mask= Ns Ar qualifier 134b2934971SMitchell Horne.Pq Event 7FH 135b2934971SMitchell HorneThe number of lines written to and from the L2 cache. 136b2934971SMitchell HorneThe event may be further qualified by using 137b2934971SMitchell Horne.Ar qualifier , 138b2934971SMitchell Hornewhich is a 139b2934971SMitchell Horne.Ql + 140b2934971SMitchell Horneseparated set of the following keywords: 141b2934971SMitchell Horne.Pp 142b2934971SMitchell Horne.Bl -tag -width indent -compact 143b2934971SMitchell Horne.It Li dirty-l2-victim 144b2934971SMitchell HorneCount lines written into L2 cache due to victim writebacks from the 145b2934971SMitchell HorneIcache or Dcache, TLB page table walks or hardware data prefetches. 146b2934971SMitchell Horne.It Li victim-from-l2 147b2934971SMitchell HorneCount writebacks of dirty lines from L2 to the system. 148b2934971SMitchell Horne.El 149b2934971SMitchell Horne.It Li k8-bu-internal-l2-request Op Li ,mask= Ns Ar qualifier 150b2934971SMitchell Horne.Pq Event 7DH 151b2934971SMitchell HorneCount internally generated requests to the L2 cache. 152b2934971SMitchell HorneThis event may be further qualified using 153b2934971SMitchell Horne.Ar qualifier , 154b2934971SMitchell Hornewhich is a 155b2934971SMitchell Horne.Ql + 156b2934971SMitchell Horneseparated set of the following keywords: 157b2934971SMitchell Horne.Pp 158b2934971SMitchell Horne.Bl -tag -width indent -compact 159b2934971SMitchell Horne.It Li cancelled 160b2934971SMitchell HorneCount cancelled requests. 161b2934971SMitchell Horne.It Li dc-fill 162b2934971SMitchell HorneCount data cache fill requests. 163b2934971SMitchell Horne.It Li ic-fill 164b2934971SMitchell HorneCount instruction cache fill requests. 165b2934971SMitchell Horne.It Li tag-snoop 166b2934971SMitchell HorneCount tag snoop requests. 167b2934971SMitchell Horne.It Li tlb-reload 168b2934971SMitchell HorneCount TLB reloads. 169b2934971SMitchell Horne.El 170b2934971SMitchell Horne.Pp 171b2934971SMitchell HorneThe default is to count all types of requests. 172b2934971SMitchell Horne.It Li k8-dc-access 173b2934971SMitchell Horne.Pq Event 40H 174b2934971SMitchell HorneCount data cache accesses including microcode scratch pad accesses. 175b2934971SMitchell Horne.It Li k8-dc-copyback Op Li ,mask= Ns Ar qualifier 176b2934971SMitchell Horne.Pq Event 44H 177b2934971SMitchell HorneCount data cache copyback operations. 178b2934971SMitchell HorneThis event may be further qualified using 179b2934971SMitchell Horne.Ar qualifier , 180b2934971SMitchell Hornewhich is a 181b2934971SMitchell Horne.Ql + 182b2934971SMitchell Horneseparated set of the following keywords: 183b2934971SMitchell Horne.Pp 184b2934971SMitchell Horne.Bl -tag -width indent -compact 185b2934971SMitchell Horne.It Li exclusive 186b2934971SMitchell HorneCount operations for lines in the 187b2934971SMitchell Horne.Dq exclusive 188b2934971SMitchell Hornestate. 189b2934971SMitchell Horne.It Li invalid 190b2934971SMitchell HorneCount operations for lines in the 191b2934971SMitchell Horne.Dq invalid 192b2934971SMitchell Hornestate. 193b2934971SMitchell Horne.It Li modified 194b2934971SMitchell HorneCount operations for lines in the 195b2934971SMitchell Horne.Dq modified 196b2934971SMitchell Hornestate. 197b2934971SMitchell Horne.It Li owner 198b2934971SMitchell HorneCount operations for lines in the 199b2934971SMitchell Horne.Dq owner 200b2934971SMitchell Hornestate. 201b2934971SMitchell Horne.It Li shared 202b2934971SMitchell HorneCount operations for lines in the 203b2934971SMitchell Horne.Dq shared 204b2934971SMitchell Hornestate. 205b2934971SMitchell Horne.El 206b2934971SMitchell Horne.Pp 207b2934971SMitchell HorneThe default is to count operations for lines in all the 208b2934971SMitchell Horneabove states. 209b2934971SMitchell Horne.It Li k8-dc-dcache-accesses-by-locks Op Li ,mask= Ns Ar qualifier 210b2934971SMitchell Horne.Pq Event 4CH 211b2934971SMitchell HorneCount data cache accesses by lock instructions. 212b2934971SMitchell HorneThis event is only available on processors of revision C or later 213b2934971SMitchell Hornevintage. 214b2934971SMitchell HorneThis event may be further qualified using 215b2934971SMitchell Horne.Ar qualifier , 216b2934971SMitchell Hornewhich is a 217b2934971SMitchell Horne.Ql + 218b2934971SMitchell Horneseparated set of the following keywords: 219b2934971SMitchell Horne.Pp 220b2934971SMitchell Horne.Bl -tag -width indent -compact 221b2934971SMitchell Horne.It Li accesses 222b2934971SMitchell HorneCount data cache accesses by lock instructions. 223b2934971SMitchell Horne.It Li misses 224b2934971SMitchell HorneCount data cache misses by lock instructions. 225b2934971SMitchell Horne.El 226b2934971SMitchell Horne.Pp 227b2934971SMitchell HorneThe default is to count all accesses. 228b2934971SMitchell Horne.It Li k8-dc-dispatched-prefetch-instructions Op Li ,mask= Ns Ar qualifier 229b2934971SMitchell Horne.Pq Event 4BH 230b2934971SMitchell HorneCount the number of dispatched prefetch instructions. 231b2934971SMitchell HorneThis event may be further qualified using 232b2934971SMitchell Horne.Ar qualifier , 233b2934971SMitchell Hornewhich is a 234b2934971SMitchell Horne.Ql + 235b2934971SMitchell Horneseparated set of the following keywords: 236b2934971SMitchell Horne.Pp 237b2934971SMitchell Horne.Bl -tag -width indent -compact 238b2934971SMitchell Horne.It Li load 239b2934971SMitchell HorneCount load operations. 240b2934971SMitchell Horne.It Li nta 241b2934971SMitchell HorneCount non-temporal operations. 242b2934971SMitchell Horne.It Li store 243b2934971SMitchell HorneCount store operations. 244b2934971SMitchell Horne.El 245b2934971SMitchell Horne.Pp 246b2934971SMitchell HorneThe default is to count all operations. 247b2934971SMitchell Horne.It Li k8-dc-l1-dtlb-miss-and-l2-dtlb-hit 248b2934971SMitchell Horne.Pq Event 45H 249b2934971SMitchell HorneCount L1 DTLB misses that are L2 DTLB hits. 250b2934971SMitchell Horne.It Li k8-dc-l1-dtlb-miss-and-l2-dtlb-miss 251b2934971SMitchell Horne.Pq Event 46H 252b2934971SMitchell HorneCount L1 DTLB misses that are also misses in the L2 DTLB. 253b2934971SMitchell Horne.It Li k8-dc-microarchitectural-early-cancel-of-an-access 254b2934971SMitchell Horne.Pq Event 49H 255b2934971SMitchell HorneCount microarchitectural early cancels of data cache accesses. 256b2934971SMitchell Horne.It Li k8-dc-microarchitectural-late-cancel-of-an-access 257b2934971SMitchell Horne.Pq Event 48H 258b2934971SMitchell HorneCount microarchitectural late cancels of data cache accesses. 259b2934971SMitchell Horne.It Li k8-dc-misaligned-data-reference 260b2934971SMitchell Horne.Pq Event 47H 261b2934971SMitchell HorneCount misaligned data references. 262b2934971SMitchell Horne.It Li k8-dc-miss 263b2934971SMitchell Horne.Pq Event 41H 264b2934971SMitchell HorneCount data cache misses. 265b2934971SMitchell Horne.It Li k8-dc-one-bit-ecc-error Op Li ,mask= Ns Ar qualifier 266b2934971SMitchell Horne.Pq Event 4AH 267b2934971SMitchell HorneCount one bit ECC errors found by the scrubber. 268b2934971SMitchell HorneThis event may be further qualified using 269b2934971SMitchell Horne.Ar qualifier , 270b2934971SMitchell Hornewhich is a 271b2934971SMitchell Horne.Ql + 272b2934971SMitchell Horneseparated set of the following keywords: 273b2934971SMitchell Horne.Pp 274b2934971SMitchell Horne.Bl -tag -width indent -compact 275b2934971SMitchell Horne.It Li scrubber 276b2934971SMitchell HorneCount scrubber detected errors. 277b2934971SMitchell Horne.It Li piggyback 278b2934971SMitchell HorneCount piggyback scrubber errors. 279b2934971SMitchell Horne.El 280b2934971SMitchell Horne.Pp 281b2934971SMitchell HorneThe default is to count both kinds of errors. 282b2934971SMitchell Horne.It Li k8-dc-refill-from-l2 Op Li ,mask= Ns Ar qualifier 283b2934971SMitchell Horne.Pq Event 42H 284b2934971SMitchell HorneCount data cache refills from L2 cache. 285b2934971SMitchell HorneThis event may be further qualified using 286b2934971SMitchell Horne.Ar qualifier , 287b2934971SMitchell Hornewhich is a 288b2934971SMitchell Horne.Ql + 289b2934971SMitchell Horneseparated set of the following keywords: 290b2934971SMitchell Horne.Pp 291b2934971SMitchell Horne.Bl -tag -width indent -compact 292b2934971SMitchell Horne.It Li exclusive 293b2934971SMitchell HorneCount operations for lines in the 294b2934971SMitchell Horne.Dq exclusive 295b2934971SMitchell Hornestate. 296b2934971SMitchell Horne.It Li invalid 297b2934971SMitchell HorneCount operations for lines in the 298b2934971SMitchell Horne.Dq invalid 299b2934971SMitchell Hornestate. 300b2934971SMitchell Horne.It Li modified 301b2934971SMitchell HorneCount operations for lines in the 302b2934971SMitchell Horne.Dq modified 303b2934971SMitchell Hornestate. 304b2934971SMitchell Horne.It Li owner 305b2934971SMitchell HorneCount operations for lines in the 306b2934971SMitchell Horne.Dq owner 307b2934971SMitchell Hornestate. 308b2934971SMitchell Horne.It Li shared 309b2934971SMitchell HorneCount operations for lines in the 310b2934971SMitchell Horne.Dq shared 311b2934971SMitchell Hornestate. 312b2934971SMitchell Horne.El 313b2934971SMitchell Horne.Pp 314b2934971SMitchell HorneThe default is to count operations for lines in all the 315b2934971SMitchell Horneabove states. 316b2934971SMitchell Horne.It Li k8-dc-refill-from-system Op Li ,mask= Ns Ar qualifier 317b2934971SMitchell Horne.Pq Event 43H 318b2934971SMitchell HorneCount data cache refills from system memory. 319b2934971SMitchell HorneThis event may be further qualified using 320b2934971SMitchell Horne.Ar qualifier , 321b2934971SMitchell Hornewhich is a 322b2934971SMitchell Horne.Ql + 323b2934971SMitchell Horneseparated set of the following keywords: 324b2934971SMitchell Horne.Pp 325b2934971SMitchell Horne.Bl -tag -width indent -compact 326b2934971SMitchell Horne.It Li exclusive 327b2934971SMitchell HorneCount operations for lines in the 328b2934971SMitchell Horne.Dq exclusive 329b2934971SMitchell Hornestate. 330b2934971SMitchell Horne.It Li invalid 331b2934971SMitchell HorneCount operations for lines in the 332b2934971SMitchell Horne.Dq invalid 333b2934971SMitchell Hornestate. 334b2934971SMitchell Horne.It Li modified 335b2934971SMitchell HorneCount operations for lines in the 336b2934971SMitchell Horne.Dq modified 337b2934971SMitchell Hornestate. 338b2934971SMitchell Horne.It Li owner 339b2934971SMitchell HorneCount operations for lines in the 340b2934971SMitchell Horne.Dq owner 341b2934971SMitchell Hornestate. 342b2934971SMitchell Horne.It Li shared 343b2934971SMitchell HorneCount operations for lines in the 344b2934971SMitchell Horne.Dq shared 345b2934971SMitchell Hornestate. 346b2934971SMitchell Horne.El 347b2934971SMitchell Horne.Pp 348b2934971SMitchell HorneThe default is to count operations for lines in all the 349b2934971SMitchell Horneabove states. 350b2934971SMitchell Horne.It Li k8-fp-cycles-with-no-fpu-ops-retired 351b2934971SMitchell Horne.Pq Event 01H 352b2934971SMitchell HorneCount cycles when no FPU ops were retired. 353b2934971SMitchell HorneThis event is supported in revision B and later CPUs. 354b2934971SMitchell Horne.It Li k8-fp-dispatched-fpu-fast-flag-ops 355b2934971SMitchell Horne.Pq Event 02H 356b2934971SMitchell HorneCount dispatched FPU ops that use the fast flag interface. 357b2934971SMitchell HorneThis event is supported in revision B and later CPUs. 358b2934971SMitchell Horne.It Li k8-fp-dispatched-fpu-ops Op Li ,mask= Ns Ar qualifier 359b2934971SMitchell Horne.Pq Event 00H 360b2934971SMitchell HorneCount the number of dispatched FPU ops. 361b2934971SMitchell HorneThis event is supported in revision B and later CPUs. 362b2934971SMitchell HorneThis event may be further qualified using 363b2934971SMitchell Horne.Ar qualifier , 364b2934971SMitchell Hornewhich is a 365b2934971SMitchell Horne.Ql + 366b2934971SMitchell Horneseparated set of the following keywords: 367b2934971SMitchell Horne.Pp 368b2934971SMitchell Horne.Bl -tag -width indent -compact 369b2934971SMitchell Horne.It Li add-pipe-excluding-junk-ops 370b2934971SMitchell HorneCount add pipe ops excluding junk ops. 371b2934971SMitchell Horne.It Li add-pipe-junk-ops 372b2934971SMitchell HorneCount junk ops in the add pipe. 373b2934971SMitchell Horne.It Li multiply-pipe-excluding-junk-ops 374b2934971SMitchell HorneCount multiply pipe ops excluding junk ops. 375b2934971SMitchell Horne.It Li multiply-pipe-junk-ops 376b2934971SMitchell HorneCount junk ops in the multiply pipe. 377b2934971SMitchell Horne.It Li store-pipe-excluding-junk-ops 378b2934971SMitchell HorneCount store pipe ops excluding junk ops 379b2934971SMitchell Horne.It Li store-pipe-junk-ops 380b2934971SMitchell HorneCount junk ops in the store pipe. 381b2934971SMitchell Horne.El 382b2934971SMitchell Horne.Pp 383b2934971SMitchell HorneThe default is to count all types of ops. 384b2934971SMitchell Horne.It Li k8-fr-decoder-empty 385b2934971SMitchell Horne.Pq Event D0H 386b2934971SMitchell HorneCount cycles when there was nothing to dispatch (i.e., the decoder 387b2934971SMitchell Hornewas empty). 388b2934971SMitchell Horne.It Li k8-fr-dispatch-stall-for-segment-load 389b2934971SMitchell Horne.Pq Event D4H 390b2934971SMitchell HorneCount dispatch stalls for segment loads. 391b2934971SMitchell Horne.It Li k8-fr-dispatch-stall-for-serialization 392b2934971SMitchell Horne.Pq Event D3H 393b2934971SMitchell HorneCount dispatch stalls for serialization. 394b2934971SMitchell Horne.It Li k8-fr-dispatch-stall-from-branch-abort-to-retire 395b2934971SMitchell Horne.Pq Event D2H 396b2934971SMitchell HorneCount dispatch stalls from branch abort to retiral. 397b2934971SMitchell Horne.It Li k8-fr-dispatch-stall-when-fpu-is-full 398b2934971SMitchell Horne.Pq Event D7H 399b2934971SMitchell HorneCount dispatch stalls when the FPU is full. 400b2934971SMitchell Horne.It Li k8-fr-dispatch-stall-when-ls-is-full 401b2934971SMitchell Horne.Pq Event D8H 402b2934971SMitchell HorneCount dispatch stalls when the load/store unit is full. 403b2934971SMitchell Horne.It Li k8-fr-dispatch-stall-when-reorder-buffer-is-full 404b2934971SMitchell Horne.Pq Event D5H 405b2934971SMitchell HorneCount dispatch stalls when the reorder buffer is full. 406b2934971SMitchell Horne.It Li k8-fr-dispatch-stall-when-reservation-stations-are-full 407b2934971SMitchell Horne.Pq Event D6H 408b2934971SMitchell HorneCount dispatch stalls when reservation stations are full. 409b2934971SMitchell Horne.It Li k8-fr-dispatch-stall-when-waiting-far-xfer-or-resync-branch-pending 410b2934971SMitchell Horne.Pq Event DAH 411b2934971SMitchell HorneCount dispatch stalls when a far control transfer or a resync branch 412b2934971SMitchell Horneis pending. 413b2934971SMitchell Horne.It Li k8-fr-dispatch-stall-when-waiting-for-all-to-be-quiet 414b2934971SMitchell Horne.Pq Event D9H 415b2934971SMitchell HorneCount dispatch stalls when waiting for all to be quiet. 416b2934971SMitchell Horne.\" XXX What does "waiting for all to be quiet" mean? 417b2934971SMitchell Horne.It Li k8-fr-dispatch-stalls 418b2934971SMitchell Horne.Pq Event D1H 419b2934971SMitchell HorneCount all dispatch stalls. 420b2934971SMitchell Horne.It Li k8-fr-fpu-exceptions Op Li ,mask= Ns Ar qualifier 421b2934971SMitchell Horne.Pq Event DBH 422b2934971SMitchell HorneCount FPU exceptions. 423b2934971SMitchell HorneThis event is supported in revision B and later CPUs. 424b2934971SMitchell HorneThis event may be further qualified using 425b2934971SMitchell Horne.Ar qualifier , 426b2934971SMitchell Hornewhich is a 427b2934971SMitchell Horne.Ql + 428b2934971SMitchell Horneseparated set of the following keywords: 429b2934971SMitchell Horne.Pp 430b2934971SMitchell Horne.Bl -tag -width indent -compact 431b2934971SMitchell Horne.It Li sse-and-x87-microtraps 432b2934971SMitchell HorneCount SSE and x87 microtraps. 433b2934971SMitchell Horne.It Li sse-reclass-microfaults 434b2934971SMitchell HorneCount SSE reclass microfaults 435b2934971SMitchell Horne.It Li sse-retype-microfaults 436b2934971SMitchell HorneCount SSE retype microfaults 437b2934971SMitchell Horne.It Li x87-reclass-microfaults 438b2934971SMitchell HorneCount x87 reclass microfaults. 439b2934971SMitchell Horne.El 440b2934971SMitchell Horne.Pp 441b2934971SMitchell HorneThe default is to count all types of exceptions. 442b2934971SMitchell Horne.It Li k8-fr-interrupts-masked-cycles 443b2934971SMitchell Horne.Pq Event CDH 444b2934971SMitchell HorneCount cycles when interrupts were masked (by CPU RFLAGS field IF was zero). 445b2934971SMitchell Horne.It Li k8-fr-interrupts-masked-while-pending-cycles 446b2934971SMitchell Horne.Pq Event CEH 447b2934971SMitchell HorneCount cycles while interrupts were masked while pending (i.e., cycles 448b2934971SMitchell Hornewhen INTR was asserted while CPU RFLAGS field IF was zero). 449b2934971SMitchell Horne.It Li k8-fr-number-of-breakpoints-for-dr0 450b2934971SMitchell Horne.Pq Event DCH 451b2934971SMitchell HorneCount the number of breakpoints for DR0. 452b2934971SMitchell Horne.It Li k8-fr-number-of-breakpoints-for-dr1 453b2934971SMitchell Horne.Pq Event DDH 454b2934971SMitchell HorneCount the number of breakpoints for DR1. 455b2934971SMitchell Horne.It Li k8-fr-number-of-breakpoints-for-dr2 456b2934971SMitchell Horne.Pq Event DEH 457b2934971SMitchell HorneCount the number of breakpoints for DR2. 458b2934971SMitchell Horne.It Li k8-fr-number-of-breakpoints-for-dr3 459b2934971SMitchell Horne.Pq Event DFH 460b2934971SMitchell HorneCount the number of breakpoints for DR3. 461b2934971SMitchell Horne.It Li k8-fr-retired-branches 462b2934971SMitchell Horne.Pq Event C2H 463b2934971SMitchell HorneCount retired branches including exceptions and interrupts. 464b2934971SMitchell Horne.It Li k8-fr-retired-branches-mispredicted 465b2934971SMitchell Horne.Pq Event C3H 466b2934971SMitchell HorneCount mispredicted retired branches. 467b2934971SMitchell Horne.It Li k8-fr-retired-far-control-transfers 468b2934971SMitchell Horne.Pq Event C6H 469b2934971SMitchell HorneCount retired far control transfers (which are always mispredicted). 470b2934971SMitchell Horne.It Li k8-fr-retired-fastpath-double-op-instructions Op Li ,mask= Ns Ar qualifier 471b2934971SMitchell Horne.Pq Event CCH 472b2934971SMitchell HorneCount retired fastpath double op instructions. 473b2934971SMitchell HorneThis event is supported in revision B and later CPUs. 474b2934971SMitchell HorneThis event may be further qualified using 475b2934971SMitchell Horne.Ar qualifier , 476b2934971SMitchell Hornewhich is a 477b2934971SMitchell Horne.Ql + 478b2934971SMitchell Horneseparated set of the following keywords: 479b2934971SMitchell Horne.Pp 480b2934971SMitchell Horne.Bl -tag -width indent -compact 481b2934971SMitchell Horne.It Li low-op-pos-0 482b2934971SMitchell HorneCount instructions with the low op in position 0. 483b2934971SMitchell Horne.It Li low-op-pos-1 484b2934971SMitchell HorneCount instructions with the low op in position 1. 485b2934971SMitchell Horne.It Li low-op-pos-2 486b2934971SMitchell HorneCount instructions with the low op in position 2. 487b2934971SMitchell Horne.El 488b2934971SMitchell Horne.Pp 489b2934971SMitchell HorneThe default is to count all types of instructions. 490b2934971SMitchell Horne.It Li k8-fr-retired-fpu-instructions Op Li ,mask= Ns Ar qualifier 491b2934971SMitchell Horne.Pq Event CBH 492b2934971SMitchell HorneCount retired FPU instructions. 493b2934971SMitchell HorneThis event is supported in revision B and later CPUs. 494b2934971SMitchell HorneThis event may be further qualified using 495b2934971SMitchell Horne.Ar qualifier , 496b2934971SMitchell Hornewhich is a 497b2934971SMitchell Horne.Ql + 498b2934971SMitchell Horneseparated set of the following keywords: 499b2934971SMitchell Horne.Pp 500b2934971SMitchell Horne.Bl -tag -width indent -compact 501b2934971SMitchell Horne.It Li mmx-3dnow 502b2934971SMitchell HorneCount MMX and 3DNow!\& instructions. 503b2934971SMitchell Horne.It Li packed-sse-sse2 504b2934971SMitchell HorneCount packed SSE and SSE2 instructions. 505b2934971SMitchell Horne.It Li scalar-sse-sse2 506b2934971SMitchell HorneCount scalar SSE and SSE2 instructions 507b2934971SMitchell Horne.It Li x87 508b2934971SMitchell HorneCount x87 instructions. 509b2934971SMitchell Horne.El 510b2934971SMitchell Horne.Pp 511b2934971SMitchell HorneThe default is to count all types of instructions. 512b2934971SMitchell Horne.It Li k8-fr-retired-near-returns 513b2934971SMitchell Horne.Pq Event C8H 514b2934971SMitchell HorneCount retired near returns. 515b2934971SMitchell Horne.It Li k8-fr-retired-near-returns-mispredicted 516b2934971SMitchell Horne.Pq Event C9H 517b2934971SMitchell HorneCount mispredicted near returns. 518b2934971SMitchell Horne.It Li k8-fr-retired-resyncs 519b2934971SMitchell Horne.Pq Event C7H 520b2934971SMitchell HorneCount retired resyncs (non-control transfer branches). 521b2934971SMitchell Horne.It Li k8-fr-retired-taken-branches 522b2934971SMitchell Horne.Pq Event C4H 523b2934971SMitchell HorneCount retired taken branches. 524b2934971SMitchell Horne.It Li k8-fr-retired-taken-branches-mispredicted 525b2934971SMitchell Horne.Pq Event C5H 526b2934971SMitchell HorneCount retired taken branches that were mispredicted. 527b2934971SMitchell Horne.It Li k8-fr-retired-taken-branches-mispredicted-by-addr-miscompare 528b2934971SMitchell Horne.Pq Event CAH 529b2934971SMitchell HorneCount retired taken branches that were mispredicted only due to an 530b2934971SMitchell Horneaddress miscompare. 531b2934971SMitchell Horne.It Li k8-fr-retired-taken-hardware-interrupts 532b2934971SMitchell Horne.Pq Event CFH 533b2934971SMitchell HorneCount retired taken hardware interrupts. 534b2934971SMitchell Horne.It Li k8-fr-retired-uops 535b2934971SMitchell Horne.Pq Event C1H 536b2934971SMitchell HorneCount retired uops. 537b2934971SMitchell Horne.It Li k8-fr-retired-x86-instructions 538b2934971SMitchell Horne.Pq Event C0H 539b2934971SMitchell HorneCount retired x86 instructions including exceptions and interrupts. 540b2934971SMitchell Horne.It Li k8-ic-fetch 541b2934971SMitchell Horne.Pq Event 80H 542b2934971SMitchell HorneCount instruction cache fetches. 543b2934971SMitchell Horne.It Li k8-ic-instruction-fetch-stall 544b2934971SMitchell Horne.Pq Event 87H 545b2934971SMitchell HorneCount cycles in stalls due to instruction fetch. 546b2934971SMitchell Horne.It Li k8-ic-l1-itlb-miss-and-l2-itlb-hit 547b2934971SMitchell Horne.Pq Event 84H 548b2934971SMitchell HorneCount L1 ITLB misses that are L2 ITLB hits. 549b2934971SMitchell Horne.It Li k8-ic-l1-itlb-miss-and-l2-itlb-miss 550b2934971SMitchell Horne.Pq Event 85H 551b2934971SMitchell HorneCount ITLB misses that miss in both L1 and L2 ITLBs. 552b2934971SMitchell Horne.It Li k8-ic-microarchitectural-resync-by-snoop 553b2934971SMitchell Horne.Pq Event 86H 554b2934971SMitchell HorneCount microarchitectural resyncs caused by snoops. 555b2934971SMitchell Horne.It Li k8-ic-miss 556b2934971SMitchell Horne.Pq Event 81H 557b2934971SMitchell HorneCount instruction cache misses. 558b2934971SMitchell Horne.It Li k8-ic-refill-from-l2 559b2934971SMitchell Horne.Pq Event 82H 560b2934971SMitchell HorneCount instruction cache refills from L2 cache. 561b2934971SMitchell Horne.It Li k8-ic-refill-from-system 562b2934971SMitchell Horne.Pq Event 83H 563b2934971SMitchell HorneCount instruction cache refills from system memory. 564b2934971SMitchell Horne.It Li k8-ic-return-stack-hits 565b2934971SMitchell Horne.Pq Event 88H 566b2934971SMitchell HorneCount hits to the return stack. 567b2934971SMitchell Horne.It Li k8-ic-return-stack-overflow 568b2934971SMitchell Horne.Pq Event 89H 569b2934971SMitchell HorneCount overflows of the return stack. 570b2934971SMitchell Horne.It Li k8-ls-buffer2-full 571b2934971SMitchell Horne.Pq Event 23H 572b2934971SMitchell HorneCount load/store buffer2 full events. 573b2934971SMitchell Horne.It Li k8-ls-locked-operation Op Li ,mask= Ns Ar qualifier 574b2934971SMitchell Horne.Pq Event 24H 575b2934971SMitchell HorneCount locked operations. 576b2934971SMitchell HorneFor revision C and later CPUs, the following qualifiers are supported: 577b2934971SMitchell Horne.Pp 578b2934971SMitchell Horne.Bl -tag -width indent -compact 579b2934971SMitchell Horne.It Li cycles-in-request 580b2934971SMitchell HorneCount the number of cycles in the lock request/grant stage. 581b2934971SMitchell Horne.It Li cycles-to-complete 582b2934971SMitchell HorneCount the number of cycles a lock takes to complete once it is 583b2934971SMitchell Hornenon-speculative and is the older load/store operation. 584b2934971SMitchell Horne.It Li locked-instructions 585b2934971SMitchell HorneCount the number of lock instructions executed. 586b2934971SMitchell Horne.El 587b2934971SMitchell Horne.Pp 588b2934971SMitchell HorneThe default is to count the number of lock instructions executed. 589b2934971SMitchell Horne.It Li k8-ls-microarchitectural-late-cancel 590b2934971SMitchell Horne.Pq Event 25H 591b2934971SMitchell HorneCount microarchitectural late cancels of operations in the load/store 592b2934971SMitchell Horneunit. 593b2934971SMitchell Horne.It Li k8-ls-microarchitectural-resync-by-self-modifying-code 594b2934971SMitchell Horne.Pq Event 21H 595b2934971SMitchell HorneCount microarchitectural resyncs caused by self-modifying code. 596b2934971SMitchell Horne.It Li k8-ls-microarchitectural-resync-by-snoop 597b2934971SMitchell Horne.Pq Event 22H 598b2934971SMitchell HorneCount microarchitectural resyncs caused by snoops. 599b2934971SMitchell Horne.It Li k8-ls-retired-cflush-instructions 600b2934971SMitchell Horne.Pq Event 26H 601b2934971SMitchell HorneCount retired CFLUSH instructions. 602b2934971SMitchell Horne.It Li k8-ls-retired-cpuid-instructions 603b2934971SMitchell Horne.Pq Event 27H 604b2934971SMitchell HorneCount retired CPUID instructions. 605b2934971SMitchell Horne.It Li k8-ls-segment-register-load Op Li ,mask= Ns Ar qualifier 606b2934971SMitchell Horne.Pq Event 20H 607b2934971SMitchell HorneCount segment register loads. 608b2934971SMitchell HorneThis event may be further qualified using 609b2934971SMitchell Horne.Ar qualifier , 610b2934971SMitchell Hornewhich is a 611b2934971SMitchell Horne.Ql + 612b2934971SMitchell Horneseparated set of the following keywords: 613b2934971SMitchell Horne.Bl -tag -width indent -compact 614b2934971SMitchell Horne.It Li cs 615b2934971SMitchell HorneCount CS register loads. 616b2934971SMitchell Horne.It Li ds 617b2934971SMitchell HorneCount DS register loads. 618b2934971SMitchell Horne.It Li es 619b2934971SMitchell HorneCount ES register loads. 620b2934971SMitchell Horne.It Li fs 621b2934971SMitchell HorneCount FS register loads. 622b2934971SMitchell Horne.It Li gs 623b2934971SMitchell HorneCount GS register loads. 624b2934971SMitchell Horne.\" .It Li hs 625b2934971SMitchell Horne.\" Count HS register loads. 626b2934971SMitchell Horne.\" XXX "HS" register? 627b2934971SMitchell Horne.It Li ss 628b2934971SMitchell HorneCount SS register loads. 629b2934971SMitchell Horne.El 630b2934971SMitchell Horne.Pp 631b2934971SMitchell HorneThe default is to count all types of loads. 632b2934971SMitchell Horne.It Li k8-nb-ht-bus0-bandwidth Op Li ,mask= Ns Ar qualifier 633b2934971SMitchell Horne.It Li k8-nb-ht-bus1-bandwidth Op Li ,mask= Ns Ar qualifier 634b2934971SMitchell Horne.It Li k8-nb-ht-bus2-bandwidth Op Li ,mask= Ns Ar qualifier 635b2934971SMitchell Horne.Pq Events F6H, F7H and F8H respectively 636b2934971SMitchell HorneCount events on the HyperTransport(tm) buses. 637b2934971SMitchell HorneThese events may be further qualified using 638b2934971SMitchell Horne.Ar qualifier , 639b2934971SMitchell Hornewhich is a 640b2934971SMitchell Horne.Ql + 641b2934971SMitchell Horneseparated set of the following keywords: 642b2934971SMitchell Horne.Pp 643b2934971SMitchell Horne.Bl -tag -width indent -compact 644b2934971SMitchell Horne.It Li buffer-release 645b2934971SMitchell HorneCount buffer release messages sent. 646b2934971SMitchell Horne.It Li command 647b2934971SMitchell HorneCount command messages sent. 648b2934971SMitchell Horne.It Li data 649b2934971SMitchell HorneCount data messages sent. 650b2934971SMitchell Horne.It Li nop 651b2934971SMitchell HorneCount nop messages sent. 652b2934971SMitchell Horne.El 653b2934971SMitchell Horne.Pp 654b2934971SMitchell HorneThe default is to count all types of messages. 655b2934971SMitchell Horne.It Li k8-nb-memory-controller-bypass-saturation Op Li ,mask= Ns Ar qualifier 656b2934971SMitchell Horne.Pq Event E4H 657b2934971SMitchell HorneCount memory controller bypass counter saturation events. 658b2934971SMitchell HorneThis event may be further qualified using 659b2934971SMitchell Horne.Ar qualifier , 660b2934971SMitchell Hornewhich is a 661b2934971SMitchell Horne.Ql + 662b2934971SMitchell Horneseparated set of the following keywords: 663b2934971SMitchell Horne.Pp 664b2934971SMitchell Horne.Bl -tag -width indent -compact 665b2934971SMitchell Horne.It Li dram-controller-interface-bypass 666b2934971SMitchell HorneCount DRAM controller interface bypass. 667b2934971SMitchell Horne.It Li dram-controller-queue-bypass 668b2934971SMitchell HorneCount DRAM controller queue bypass. 669b2934971SMitchell Horne.It Li memory-controller-hi-pri-bypass 670b2934971SMitchell HorneCount memory controller high priority bypasses. 671b2934971SMitchell Horne.It Li memory-controller-lo-pri-bypass 672b2934971SMitchell HorneCount memory controller low priority bypasses. 673b2934971SMitchell Horne.El 674b2934971SMitchell Horne.It Li k8-nb-memory-controller-dram-slots-missed 675b2934971SMitchell Horne.Pq Event E2H 676b2934971SMitchell HorneCount memory controller DRAM command slots missed (in MemClks). 677b2934971SMitchell Horne.It Li k8-nb-memory-controller-page-access-event Op Li ,mask= Ns Ar qualifier 678b2934971SMitchell Horne.Pq Event E0H 679b2934971SMitchell HorneCount memory controller page access events. 680b2934971SMitchell HorneThis event may be further qualified using 681b2934971SMitchell Horne.Ar qualifier , 682b2934971SMitchell Hornewhich is a 683b2934971SMitchell Horne.Ql + 684b2934971SMitchell Horneseparated set of the following keywords: 685b2934971SMitchell Horne.Pp 686b2934971SMitchell Horne.Bl -tag -width indent -compact 687b2934971SMitchell Horne.It Li page-conflict 688b2934971SMitchell HorneCount page conflicts. 689b2934971SMitchell Horne.It Li page-hit 690b2934971SMitchell HorneCount page hits. 691b2934971SMitchell Horne.It Li page-miss 692b2934971SMitchell HorneCount page misses. 693b2934971SMitchell Horne.El 694b2934971SMitchell Horne.Pp 695b2934971SMitchell HorneThe default is to count all types of events. 696b2934971SMitchell Horne.It Li k8-nb-memory-controller-page-table-overflow 697b2934971SMitchell Horne.Pq Event E1H 698b2934971SMitchell HorneCount memory control page table overflow events. 699b2934971SMitchell Horne.It Li k8-nb-memory-controller-turnaround Op Li ,mask= Ns Ar qualifier 700b2934971SMitchell Horne.Pq Event E3H 701b2934971SMitchell HorneCount memory control turnaround events. 702b2934971SMitchell HorneThis event may be further qualified using 703b2934971SMitchell Horne.Ar qualifier , 704b2934971SMitchell Hornewhich is a 705b2934971SMitchell Horne.Ql + 706b2934971SMitchell Horneseparated set of the following keywords: 707b2934971SMitchell Horne.Pp 708b2934971SMitchell Horne.Bl -tag -width indent -compact 709b2934971SMitchell Horne.\" XXX doc is unclear whether these are cycle counts or event counts 710b2934971SMitchell Horne.It Li dimm-turnaround 711b2934971SMitchell HorneCount DIMM turnarounds. 712b2934971SMitchell Horne.It Li read-to-write-turnaround 713b2934971SMitchell HorneCount read to write turnarounds. 714b2934971SMitchell Horne.It Li write-to-read-turnaround 715b2934971SMitchell HorneCount write to read turnarounds. 716b2934971SMitchell Horne.El 717b2934971SMitchell Horne.Pp 718b2934971SMitchell HorneThe default is to count all types of events. 719b2934971SMitchell Horne.It Li k8-nb-probe-result Op Li ,mask= Ns Ar qualifier 720b2934971SMitchell Horne.Pq Event ECH 721b2934971SMitchell HorneCount probe events. 722b2934971SMitchell HorneThis event may be further qualified using 723b2934971SMitchell Horne.Ar qualifier , 724b2934971SMitchell Hornewhich is a 725b2934971SMitchell Horne.Ql + 726b2934971SMitchell Horneseparated set of the following keywords: 727b2934971SMitchell Horne.Pp 728b2934971SMitchell Horne.Bl -tag -width indent -compact 729b2934971SMitchell Horne.It Li probe-hit 730b2934971SMitchell HorneCount all probe hits. 731b2934971SMitchell Horne.It Li probe-hit-dirty-no-memory-cancel 732b2934971SMitchell HorneCount probe hits without memory cancels. 733b2934971SMitchell Horne.It Li probe-hit-dirty-with-memory-cancel 734b2934971SMitchell HorneCount probe hits with memory cancels. 735b2934971SMitchell Horne.It Li probe-miss 736b2934971SMitchell HorneCount probe misses. 737b2934971SMitchell Horne.El 738b2934971SMitchell Horne.It Li k8-nb-sized-commands Op Li ,mask= Ns Ar qualifier 739b2934971SMitchell Horne.Pq Event EBH 740b2934971SMitchell HorneCount sized commands issued. 741b2934971SMitchell HorneThis event may be further qualified using 742b2934971SMitchell Horne.Ar qualifier , 743b2934971SMitchell Hornewhich is a 744b2934971SMitchell Horne.Ql + 745b2934971SMitchell Horneseparated set of the following keywords: 746b2934971SMitchell Horne.Pp 747b2934971SMitchell Horne.Bl -tag -width indent -compact 748b2934971SMitchell Horne.It Li nonpostwrszbyte 749b2934971SMitchell Horne.It Li nonpostwrszdword 750b2934971SMitchell Horne.It Li postwrszbyte 751b2934971SMitchell Horne.It Li postwrszdword 752b2934971SMitchell Horne.It Li rdszbyte 753b2934971SMitchell Horne.It Li rdszdword 754b2934971SMitchell Horne.It Li rdmodwr 755b2934971SMitchell Horne.El 756b2934971SMitchell Horne.Pp 757b2934971SMitchell HorneThe default is to count all types of commands. 758b2934971SMitchell Horne.El 759b2934971SMitchell Horne.Ss Event Name Aliases 760b2934971SMitchell HorneThe following table shows the mapping between the PMC-independent 761b2934971SMitchell Hornealiases supported by 762b2934971SMitchell Horne.Lb libpmc 763b2934971SMitchell Horneand the underlying hardware events used. 764b2934971SMitchell Horne.Bl -column "branch-mispredicts" "Description" 765b2934971SMitchell Horne.It Em Alias Ta Em Event 766b2934971SMitchell Horne.It Li branches Ta Li k8-fr-retired-taken-branches 767b2934971SMitchell Horne.It Li branch-mispredicts Ta Li k8-fr-retired-taken-branches-mispredicted 768b2934971SMitchell Horne.It Li dc-misses Ta Li k8-dc-miss 769b2934971SMitchell Horne.It Li ic-misses Ta Li k8-ic-miss 770b2934971SMitchell Horne.It Li instructions Ta Li k8-fr-retired-x86-instructions 771b2934971SMitchell Horne.It Li interrupts Ta Li k8-fr-taken-hardware-interrupts 772b2934971SMitchell Horne.It Li unhalted-cycles Ta Li k8-bu-cpu-clk-unhalted 773b2934971SMitchell Horne.El 774b2934971SMitchell Horne.Sh SEE ALSO 775b2934971SMitchell Horne.Xr pmc 3 , 776b2934971SMitchell Horne.Xr pmc.atom 3 , 777b2934971SMitchell Horne.Xr pmc.core 3 , 778b2934971SMitchell Horne.Xr pmc.core2 3 , 779b2934971SMitchell Horne.Xr pmc.iaf 3 , 780b2934971SMitchell Horne.Xr pmc.soft 3 , 781b2934971SMitchell Horne.Xr pmc.tsc 3 , 782b2934971SMitchell Horne.Xr pmclog 3 , 783b2934971SMitchell Horne.Xr hwpmc 4 784b2934971SMitchell Horne.Sh HISTORY 785b2934971SMitchell HorneThe 786b2934971SMitchell Horne.Nm pmc 787b2934971SMitchell Hornelibrary first appeared in 788b2934971SMitchell Horne.Fx 6.0 . 789b2934971SMitchell Horne.Sh AUTHORS 790b2934971SMitchell HorneThe 791b2934971SMitchell Horne.Lb libpmc 792b2934971SMitchell Hornelibrary was written by 793b2934971SMitchell Horne.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 794